URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
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/t6507lp/trunk/rtl/verilog
- from Rev 128 to Rev 129
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Rev 128 → Rev 129
/t6507lp_alu_wrapper.v
42,27 → 42,29
//////////////////////////////////////////////////////////////////////////// |
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`include "timescale.v" |
`include "T6507LP_ALU.v" |
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module wrapper_alu(); |
module t6507lp_alu_wrapper(); |
parameter [3:0] DATA_SIZE = 4'd8; |
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001; |
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// all inputs are regs |
reg clk; |
reg n_rst_i; |
reg reset_n; |
reg alu_enable; |
reg alu_opcode; |
reg alu_a; |
reg [DATA_SIZE_:0] alu_opcode; |
reg [DATA_SIZE_:0] alu_a; |
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// all outputs are wires |
wire alu_result; |
wire alu_status; |
wire alu_x; |
wire alu_y; |
wire [DATA_SIZE_:0] alu_result; |
wire [DATA_SIZE_:0] alu_status; |
wire [DATA_SIZE_:0] alu_x; |
wire [DATA_SIZE_:0] alu_y; |
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initial clk = 0; |
always #10 clk <= ~clk; |
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//always #100 $write("working"); |
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T6507LP_ALU T6507LP_ALU ( |
.clk_i (clk), |