URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl/verilog
- from Rev 145 to Rev 146
- ↔ Reverse comparison
Rev 145 → Rev 146
/t6507lp_fsm_tb.v
62,7 → 62,7
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integer my_i; |
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`include "T6507LP_Package.v" |
`include "t6507lp_package.v" |
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t6507lp_fsm #(8,13) t6507lp_fsm( |
.clk(clk), |
/t6507lp_fsm.v
101,7 → 101,7
localparam RESET = 5'b11111; |
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// OPCODES TODO: verify how this get synthesised |
`include "T6507LP_Package.v" |
`include "t6507lp_package.v" |
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// mem_rw signals |
localparam MEM_READ = 1'b0; |
198,6 → 198,8
end |
end |
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reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles |
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always @ (posedge clk or negedge reset_n) begin // sequencial always block |
if (reset_n == 1'b0) begin |
// all registers must assume default values |
211,12 → 213,14
address <= 13'h0000; |
mem_rw <= MEM_READ; |
data_out <= 8'h00; |
rst_counter <= 0; |
end |
else begin |
state <= next_state; |
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case (state) |
RESET: begin // The processor was reset |
rst_counter <= rst_counter + 1; |
sp <= 9'b100000000; // this prevents flipflops with different drivers |
//$write("under reset"); |
end |
580,7 → 584,9
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case (state) |
RESET: begin |
next_state = FETCH_OP; |
if (rst_counter == 6) begin |
next_state = FETCH_OP; |
end |
end |
FETCH_OP: begin |
next_state = FETCH_LOW; |