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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 149 to Rev 150
    ↔ Reverse comparison
  •

Rev 149 → Rev 150

/t6507lp_alu.v
72,7 → 72,7
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0) begin
$display("RESTART");
//$display("RESTART");
alu_result <= 0;
alu_status[C] <= 0;
alu_status[N] <= 0;
163,7 → 163,13
end
PLP_IMP, RTI_IMP :
begin
alu_status <= alu_a;
alu_status[C] <= alu_a[C];
alu_status[Z] <= alu_a[Z];
alu_status[I] <= alu_a[I];
alu_status[D] <= alu_a[D];
alu_status[B] <= alu_a[B];
alu_status[V] <= alu_a[V];
alu_status[N] <= alu_a[N];
end
BIT_ZPG, BIT_ABS :
begin
188,12 → 194,16
always @ (*) begin
bcd1 = A;
bcd2 = alu_a;
//result = alu_result;
//STATUS[C] = STATUS[C];
//STATUS[V] = STATUS[V];
//STATUS[B] = STATUS[B];
//STATUS[I] = STATUS[I];
//STATUS[D] = STATUS[D];
result = alu_result;
STATUS[N] = alu_status[N];
STATUS[C] = alu_status[C];
STATUS[V] = alu_status[V];
STATUS[B] = alu_status[B];
STATUS[I] = alu_status[I];
STATUS[D] = alu_status[D];
STATUS[Z] = alu_status[Z];
STATUS[N] = alu_status[N];
STATUS[5] = alu_status[5];
 
case (alu_opcode)
// BIT - Bit Test
336,8 → 346,8
STATUS[C] = 1;
end
end
$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
//$display("op1 = %h op2 = %h result = %h", bcd1, bcd2, result);
//$display("V = %b C = %b D = %b", STATUS[V], STATUS[C], STATUS[D]);
end
// AND - Logical AND
/t6507lp_alu_tb.v
44,14 → 44,14
$display("alu_status %b %b ", alu_status, alu_status_expected);
$display("alu_x %h %h ", alu_x, alu_x_expected );
$display("alu_y %h %h ", alu_y, alu_y_expected );
if ((alu_result_expected != alu_result) || (alu_status_expected != alu_status) || (alu_x_expected != alu_x) || (alu_y_expected != alu_y))
if ((alu_result_expected == alu_result) && (alu_status_expected == alu_status) && (alu_x_expected == alu_x) && (alu_y_expected == alu_y))
begin
$display("ERROR at instruction %h",alu_opcode);
$finish;
$display("Instruction %h... OK!", alu_opcode);
end
else
begin
$display("Instruction %h... OK!", alu_opcode);
$display("ERROR at instruction %h",alu_opcode);
$finish;
end
end
endtask
67,7 → 67,7
clk = 0;
reset_n = 0;
@(negedge clk);
@(negedge clk);
//@(negedge clk);
reset_n = 1;
alu_enable = 1;
alu_result_expected = 8'h00;

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