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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 163 to Rev 164
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Rev 163 → Rev 164

/t6507lp_alu.v
68,8 → 68,10
reg [7:0] op2;
reg [7:0] bcdl;
reg [7:0] bcdh;
reg [7:0] bcdh2;
reg [7:0] AL;
reg [7:0] AH;
 
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
321,17 → 323,17
// TODO: verify synthesis for % operand
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
if (alu_status[D] == 1) begin
bcdl = A[3:0] + alu_a[3:0] + alu_status[C];
bcdh = A[7:4] + alu_a[7:4];
if (bcdl > 9) begin
bcdh = bcdh + bcdl[5:4];
bcdl = bcdl % 10;
AL = A[3:0] + alu_a[3:0] + alu_status[C];
AH = A[7:4] + alu_a[7:4];
if (AL > 9) begin
bcdh = AH + (AL / 10);
bcdl = AL % 10;
end
if (bcdh > 9) begin
if (AH > 9) begin
STATUS[C] = 1;
bcdh = bcdh % 10;
bcdh2 = bcdh % 10;
end
result = {bcdh[3:0],bcdl[3:0]};
result = {bcdh2[3:0],bcdl[3:0]};
end
else
{STATUS[C],result} = op1 + op2 + alu_status[C];
/t6507lp_alu_tb.v
19,9 → 19,14
reg [7:0] alu_x_expected;
reg [7:0] alu_y_expected;
 
reg c_aux;
reg C_in;
reg [7:0] temp;
reg sign;
reg [3:0] AL;
reg [3:0] AH;
reg [3:0] BL;
reg [3:0] BH;
reg [7:0] alu_result_expected_temp;
 
t6507lp_alu DUT (
.clk (clk),
105,7 → 110,7
check();
end
 
/* // BCD
// BCD
// LDA
alu_a = 0;
alu_opcode = LDA_IMM;
114,8 → 119,14
@(negedge clk);
alu_result_expected = 8'h00;
// NV1BDIZC
alu_status_expected = 8'b00101010;
alu_status_expected[N] = 0;
alu_status_expected[Z] = 1;
check();
// SED
alu_opcode = SED_IMP;
@(negedge clk);
alu_status_expected[D] = 1;
check();
 
// ADC
alu_opcode = ADC_IMM;
123,17 → 134,43
begin
alu_a = $random;
@(negedge clk);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], DUT.result);
$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], DUT.result);
sign = alu_result_expected[7];
{alu_status_expected[C], alu_result_expected} = alu_a + alu_result_expected + alu_status_expected[C];
AL = alu_a[3:0];
AH = alu_a[7:4];
BL = alu_result_expected[3:0];
BH = alu_result_expected[7:4];
if ( AL > 9 ) begin
AL = AL - 10;
AH = AH + 1;
end
if (AH > 9) begin
AH = AH - 10;
end
if ( BL > 9 ) begin
BL = BL - 10;
BH = BH + 1;
end
if ( BH > 9 ) begin
BH = BH - 10;
end
{C_in,alu_result_expected_temp[3:0]} = AL + BL + alu_status_expected[C];
{alu_status_expected[C],alu_result_expected_temp[7:4]} = AH + BH + C_in;
if ( alu_result_expected_temp[3:0] > 9 ) begin
alu_result_expected[3:0] = alu_result_expected_temp[3:0] - 10;
alu_result_expected[7:4] = alu_result_expected_temp[7:4] + 1;
end
if ( alu_result_expected_temp[7:4] > 9 ) begin
alu_result_expected[7:4] = alu_result_expected_temp[7:4] - 10;
end
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
check();
end
*/
 
// ASL
alu_opcode = ASL_ABS;

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