OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 178 to Rev 179
    ↔ Reverse comparison
  •

Rev 178 → Rev 179

/t6507lp_alu.v
418,6 → 418,32
// SBC - Subtract with Carry
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
if (alu_status[D] == 1) begin
op2 = ~op2;
AL = A[3:0] + alu_a[3:0] + alu_status[C];
AH = A[7:4] + alu_a[7:4];
if (AL > 9) begin
bcdh = AH + (AL / 10);
bcdl = AL % 10;
end
else begin
bcdh = AH;
bcdl = AL;
end
if (bcdh > 9) begin
STATUS[C] = 1;
bcdh2 = bcdh % 10;
end
else begin
STATUS[C] = 0;
bcdh2 = bcdh;
end
result = {bcdh2[3:0],bcdl[3:0]};
end
else begin
//$display("MODO NORMAL");
{STATUS[C],result} = op1 + op2 + alu_status[C];
end
/* if (alu_status[D] == 1) begin
bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
bcdh = op1[7:4] - op2[7:4];
if (bcdl > 9) begin
435,7 → 461,7
result = op1 + op2 + alu_status[C];
STATUS[C] = ~result[7];
end
*/
if ((op1[7] == sign) && (op1[7] != result[7]))
STATUS[V] = 1;
/t6507lp_alu_tb.v
110,7 → 110,6
check;
end
 
/*
// BCD
// LDA
alu_a = 0;
171,9 → 170,14
alu_status_expected[N] = alu_result_expected[7];
alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
check;
end
*/
end
$stop
// CLD
alu_opcode = CLD_IMP;
@(negedge clk);
alu_status_expected[D] = 0;
check;
 
// ASL
alu_opcode = ASL_ABS;
for (i = 0; i < 1000; i = i + 1)
210,11 → 214,11
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
$display("result_expected = %d",alu_result_expected);
//$display("result_expected = %d",alu_result_expected);
alu_result_expected = alu_a ^ alu_result_expected;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
$display("result_expected = %d", alu_result_expected);
//$display("result_expected = %d", alu_result_expected);
check;
end
 
271,7 → 275,7
alu_a = i;
@(negedge clk);
alu_x_expected = alu_a;
$display("alu_x_expected = %h", alu_x_expected);
//$display("alu_x_expected = %h", alu_x_expected);
//alu_result_expected = i;
alu_status_expected[Z] = (alu_x_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_x_expected[7];
288,7 → 292,7
alu_a = i;
@(negedge clk);
alu_y_expected = alu_a;
$display("alu_y_expected = %h", alu_y_expected);
//$display("alu_y_expected = %h", alu_y_expected);
//alu_result_expected = i;
alu_status_expected[Z] = (alu_y_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_y_expected[7];
318,7 → 322,7
begin
alu_a = i;
@(negedge clk);
$display("alu_x_expected = %h", alu_x_expected);
//$display("alu_x_expected = %h", alu_x_expected);
//alu_result_expected = i;
//alu_x_expected = alu_a;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
333,7 → 337,7
begin
alu_a = i;
@(negedge clk);
$display("alu_y_expected = %h", alu_y_expected);
//$display("alu_y_expected = %h", alu_y_expected);
//alu_result_expected = i;
//alu_y_expected = alu_a;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.