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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 192 to Rev 193
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  •

Rev 192 → Rev 193

/t2600.v
44,7 → 44,35
 
`include "timescale.v"
 
// CPU
// RIOT
module t2600(clk, reset_n);
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
localparam [3:0] RIOT_ADDR_SIZE = 4'd7;
localparam [3:0] TIA_ADDR_SIZE = 4'd6;
 
input clk;
input reset_n;
 
t6507lp #(DATA_SIZE, ADDR_SIZE) t6507lp (
.clk (clk),
.reset_n (reset_n),
.data_in (data_in),
.rw_mem (rw_mem),
.data_out (data_out),
.address (address)
);
t6532 #(DATA_SIZE, RIOT_ADDR_SIZE) t6532 (
.clk (clk),
.io_lines (io_lines),
.enable (enable),
.address (address),
.data (data)
);
 
 
// VIDEO
// BUS CONTROLLER
 
endmodule
 
/t6532.v
44,7 → 44,7
 
`include "timescale.v"
 
module t6532(clk, io_lines, enable, address, data);
module t6532(clk, io_lines, enable, rw_mem, address, data);
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd7; // this is the *local* addr_size
 
51,11 → 51,43
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
 
 
input clk;
input [15:0] io_lines;
input enable;
input rw_mem;
input [ADDR_SIZE_:0] address;
inout [DATA_SIZE_:0] data;
 
wire [DATA_SIZE_:0] ram [127:0];
wire [DATA_SIZE_:0] io_ports [3:0]; // porta, portaddr, portb, portbddr
 
reg [DATA_SIZE_:0] data_drv;
 
assign data = (rw_mem) ? 8'bZ: data_drv; // if i am writing the bus receives the data from cpu
 
t6532_io t6532_io (
.clk (clk),
.io_lines (io_lines),
.ddra (io_ports[1]),
.A (io_ports[0]),
.B (io_ports[2])
);
 
always @(clk) begin
if (enable && rw_mem) begin
case (address)
8'h80: data_drv <= io_ports[0];
default: ;
endcase
end
end
 
always @(*) begin
io_ports [3] = 8'h00; // portb ddr is always input
end
 
// io
// timer
// ram
endmodule
/t6532_io.v
0,0 → 1,83
////////////////////////////////////////////////////////////////////////////
//// ////
//// t6532 IP Core ////
//// ////
//// This file is part of the t2600 project ////
//// http://www.opencores.org/cores/t2600/ ////
//// ////
//// Description ////
//// 6532 i/o ////
//// ////
//// TODO: ////
//// - Code the i/o ////
//// ////
//// Author(s): ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
// iolines[0] = B.D0
// iolines[15] = A.D7
// check the spec
 
module t6532_io(clk, io_lines, ddra, A, B);
input clk;
input [15:0] io_lines;
input [15:0] ddra;
output reg [7:0] A; // this is hex 280.
output reg [7:0] B; // console switches. input port only. this is hex 282.
 
always @ (clk) begin
B[0] <= ~io_lines[0]; // these two are not actually switches
B[1] <= ~io_lines[1];
if (io_lines[3]) begin // these are.
B[3] <= !B[3];
end
if (io_lines[6]) begin
B[6] <= !B[6];
end
if (io_lines[7]) begin
B[7] <= !B[7];
end
 
A[0] <= (ddra[0] == 0) ? io_lines[8] : A[0];
A[1] <= (ddra[1] == 0) ? io_lines[9] : A[1];
A[2] <= (ddra[2] == 0) ? io_lines[10] : A[2];
A[3] <= (ddra[3] == 0) ? io_lines[11] : A[3];
A[4] <= (ddra[4] == 0) ? io_lines[12] : A[4];
A[5] <= (ddra[5] == 0) ? io_lines[13] : A[5];
A[6] <= (ddra[6] == 0) ? io_lines[14] : A[6];
A[7] <= (ddra[7] == 0) ? io_lines[15] : A[7];
end
 
endmodule
 

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