URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
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- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl/verilog
- from Rev 203 to Rev 204
- ↔ Reverse comparison
Rev 203 → Rev 204
/t6532.v
82,14 → 82,17
always @(posedge clk or negedge reset_n) begin // I/O handling |
if (reset_n == 1'b0) begin |
port_a <= 8'h00; |
port_b <= 8'h00; |
port_b <= 8'b00001000; // D3=1, color! |
ddra <= 8'h00; |
end |
else begin |
port_b[0] <= ~io_lines[0]; // these two are not actually switches |
port_b[1] <= ~io_lines[1]; |
|
if (io_lines[3]) begin // these are. |
if (io_lines[0]) begin // these are switches |
port_b[0] <= !port_b[0]; |
end |
if (io_lines[1]) begin |
port_b[1] <= !port_b[1]; |
end |
if (io_lines[3]) begin |
port_b[3] <= !port_b[3]; |
end |
if (io_lines[6]) begin |
129,11 → 132,14
10'h282: data_drv <= port_b; |
10'h283: data_drv <= 8'h00; // portb ddr is always input |
10'h284: data_drv <= timer; |
default: data_drv <= ram[address[6:0]]; |
default: data_drv <= ram[address]; |
endcase |
end |
else if (writing) begin // writing! |
case (address) |
case (address) |
10'h281: begin |
ddra <= data; |
end |
10'h294: begin |
c1_timer <= 1'b1; |
c8_timer <= 1'b0; |
150,7 → 156,7
c1024_timer <= 1'b0; |
timer <= data; |
flipped <= 1'b0; |
counter <= 11'd8; |
counter <= 11'd7; |
end |
10'h296: begin |
c1_timer <= 1'b0; |
159,7 → 165,7
c1024_timer <= 1'b0; |
timer <= data; |
flipped <= 1'b0; |
counter <= 11'd64; |
counter <= 11'd63; |
end |
10'h297: begin |
c1_timer <= 1'b0; |
168,38 → 174,41
c1024_timer <= 1'b1; |
timer <= data; |
flipped <= 1'b0; |
counter <= 11'd1024; |
counter <= 11'd1023; |
end |
default: begin |
ram[address[6:0]] <= data; |
ram[address] <= data; |
end |
endcase |
end |
|
if (!writing_at_timer) begin |
if (counter == 11'd0) begin |
if (flipped || timer == 8'd0) begin // finished counting |
counter <= 11'd0; |
timer <= timer - 8'd1; |
flipped <= 1'b1; |
end |
else begin |
if (counter == 11'd0) begin |
timer <= timer - 8'd1; |
|
if (timer == 8'd0) begin |
flipped <= 1'b1; |
if (c1_timer) begin |
counter <= 11'd0; |
end |
if (c8_timer) begin |
counter <= 11'd7; |
end |
if (c64_timer) begin |
counter <= 11'd63; |
end |
if (c1024_timer) begin |
counter <= 11'd1023; |
end |
end |
|
if (c1_timer || flipped) begin |
counter <= 11'd1; |
else begin |
counter <= counter - 11'd1; |
end |
if (c8_timer) begin |
counter <= 11'd8; |
end |
if (c64_timer) begin |
counter <= 11'd64; |
end |
if (c1024_timer) begin |
counter <= 11'd1024; |
end |
end |
else begin |
counter <= counter - 11'd1; |
end |
end |
end |
end |
/t6532_tb.v
83,7 → 83,7
initial begin |
clk = 1'b0; |
reset_n = 1'b0; |
io_lines = 15'd0; |
io_lines = 16'd0; |
enable = 1'b0; |
mem_rw = MEM_READ; |
address = 0; |
90,9 → 90,64
|
@(negedge clk) // will wait for next negative edge of the clock (t=20) |
reset_n=1'b1; |
|
|
#4000; |
@(negedge clk) // testing the port_b. all switches must change! |
io_lines = 16'h00FF; |
|
@(negedge clk) // testing the port_b. all switches must change! |
io_lines = 16'h00FF; |
|
@(negedge clk) // testing the port_a. all switches must change since ddra = 0. (0 == input) |
io_lines = 16'hFF00; |
|
@(negedge clk) // setting ddra = FF. (output) |
enable = 1'b1; |
io_lines = 16'hFF00; |
address = 10'h281; |
mem_rw = MEM_WRITE; |
data_drv = 8'hFF; |
|
@(negedge clk) // testing port_a again. no switching this time! |
enable = 1'b0; |
io_lines = 16'h0000; |
address = 0; |
mem_rw = MEM_READ; |
|
@(negedge clk) // writing at the memory |
enable = 1'b1; |
address = 10'd255; |
mem_rw = MEM_WRITE; |
data_drv = 8'h11; |
|
@(negedge clk) // reading memory (output) |
enable = 1'b1; |
address = 10'd255; |
mem_rw = MEM_READ; |
|
@(negedge clk) // using the timer to count 100*1 cycle. |
enable = 1'b1; |
address = 10'h294; |
mem_rw = MEM_WRITE; |
data_drv = 8'd100; |
|
@(negedge clk); |
mem_rw = MEM_READ; |
enable = 1'b0; |
#2040; |
|
@(negedge clk) // using the timer to count 10*8 cycles. |
enable = 1'b1; |
address = 10'h295; |
mem_rw = MEM_WRITE; |
data_drv = 8'd10; |
|
@(negedge clk); |
mem_rw = MEM_READ; |
enable = 1'b0; |
#1640; |
|
|
|
$finish; // to shut down the simulation |
end //initial |
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