URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl/verilog
- from Rev 212 to Rev 214
- ↔ Reverse comparison
Rev 212 → Rev 214
/t2600.v
70,9 → 70,36
.data (data) |
); |
|
t2600_bus t2600_bus ( |
.address (address), |
.data_from_cpu (data_from_cpu), |
.cpu_rw_mem (cpu_rw_mem), |
.riot_data (riot_data), |
.rom_data (rom_data), |
.tia_data (tia_data), |
.address_riot (address_riot), |
.address_rom (address_rom), |
.address_tia (address_tia), |
.data_to_cpu (data_to_cpu), |
.enable_riot (enable_riot), |
.enable_rom (enable_rom), |
.enable_tia (enable_tia), |
.rw_mem (rw_mem) |
); |
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T2600_KB T2600_KB ( |
.CLK (clk), |
.RST (reset_n), |
.io_lines (io_lines), |
.KC (kc), |
.KD (kd) |
); |
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// VIDEO |
// BUS CONTROLLER |
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endmodule |
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/t2600_kb_tb.v
47,22 → 47,39
// all inputs are regs |
reg clk; |
reg reset_n; |
reg kd; |
reg kc; |
// all outputs are wires |
wire [15:0] io_lines; |
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always #10 clk <= ~clk; |
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initial clk = 0; |
always #10 clk <= ~clk; |
initial begin |
clk = 1'b0; |
reset_n = 1'b1; |
kd = 1'b0; |
kc = 1'b0; |
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always @(posedge clk) begin |
//$display("reset is %b", reset_n); |
//$display("alu_enable is %b", alu_enable); |
//$display("alu_opcode is %h", alu_opcode); |
//$display("alu_a is %d", alu_a); |
#10; |
reset_n = 1'b0; |
|
#40000; |
$finish; |
end |
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t2600_kb t2600_kb ( |
|
always @(clk) begin |
kc = $random; |
kd = $random; |
end |
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T2600_KB T2600_KB ( |
.CLK (clk), |
.RST (reset_n), |
.io_lines (alu_enable) |
.io_lines (io_lines), |
.KC (kc), |
.KD (kd) |
); |
|
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endmodule |