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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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    /t6507lp/trunk/rtl/verilog
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Rev 237 → Rev 238

/t6507lp_alu.v
44,60 → 44,52
 
`include "timescale.v"
 
module t6507lp_alu(
clk,
reset_n,
alu_enable,
alu_result,
alu_status,
alu_opcode,
alu_a,
alu_x,
alu_y
);
module t6507lp_alu(clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y);
 
`include "t6507lp_package.v"
 
localparam DATA_SIZE = 8;
localparam [3:0] BCD_HIGH_LIMIT = 4'd9;
localparam [3:0] BCD_FIX = 8'd6;
 
input wire clk;
input wire reset_n;
input wire alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
output reg [7:0] alu_x;
output reg [7:0] alu_y;
input wire [DATA_SIZE - 1:0] alu_opcode;
input wire [DATA_SIZE - 1:0] alu_a;
output reg [DATA_SIZE - 1:0] alu_result;
output reg [DATA_SIZE - 1:0] alu_status;
output reg [DATA_SIZE - 1:0] alu_x;
output reg [DATA_SIZE - 1:0] alu_y;
 
reg [7:0] A;
reg [7:0] STATUS;
reg [9:0] result;
reg [7:0] op1;
reg [7:0] op2;
reg [7:0] bcdl;
reg [7:0] bcdh;
reg [7:0] bcdh2;
reg [7:0] AL;
reg [7:0] AH;
reg C_aux;
reg sign;
reg [DATA_SIZE - 1:0] A;
reg [DATA_SIZE - 1:0] STATUS;
reg [DATA_SIZE + 1:0] result;
reg [DATA_SIZE - 1:0] op1;
reg [DATA_SIZE - 1:0] op2;
reg [DATA_SIZE - 1:0] bcdl;
reg [DATA_SIZE - 1:0] bcdh;
reg [DATA_SIZE - 1:0] bcdh2;
reg [DATA_SIZE - 1:0] AL;
reg [DATA_SIZE - 1:0] AH;
 
`include "t6507lp_package.v"
 
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0) begin
alu_result <= 0;
alu_status[C] <= 0;
alu_status[N] <= 0;
alu_status[V] <= 0;
alu_status[5] <= 1;
alu_status[Z] <= 1;
alu_status[I] <= 0;
alu_status[B] <= 0;
alu_status[D] <= 0;
A <= 0;
alu_x <= 0;
alu_y <= 0;
if (reset_n == 1'b0) begin
alu_result <= 10'd0;
alu_status[C] <= 1'b0;
alu_status[N] <= 1'b0;
alu_status[V] <= 1'b0;
alu_status[5] <= 1'b1;
alu_status[Z] <= 1'b1;
alu_status[I] <= 1'b0;
alu_status[B] <= 1'b0;
alu_status[D] <= 1'b0;
A <= 8'd0;
alu_x <= 8'd0;
alu_y <= 8'd0;
end
else if ( alu_enable == 1 ) begin
else if ( alu_enable == 1'b1 ) begin
case (alu_opcode)
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY,
ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS,
145,28 → 137,28
alu_y <= result[7:0];
end
SEC_IMP : begin
alu_status[C] <= 1;
alu_status[C] <= 1'b1;
end
SED_IMP : begin
alu_status[D] <= 1;
alu_status[D] <= 1'b1;
end
SEI_IMP : begin
alu_status[I] <= 1;
alu_status[I] <= 1'b1;
end
CLC_IMP : begin
alu_status[C] <= 0;
alu_status[C] <= 1'b0;
end
CLD_IMP : begin
alu_status[D] <= 0;
alu_status[D] <= 1'b0;
end
CLI_IMP : begin
alu_status[I] <= 0;
alu_status[I] <= 1'b0;
end
CLV_IMP : begin
alu_status[V] <= 0;
alu_status[V] <= 1'b0;
end
BRK_IMP : begin
alu_status[B] <= 1;
alu_status[B] <= 1'b1;
end
PLP_IMP, RTI_IMP : begin
alu_status[C] <= alu_a[C];
176,7 → 168,7
alu_status[B] <= alu_a[B];
alu_status[V] <= alu_a[V];
alu_status[N] <= alu_a[N];
alu_status[5] <= 1;
alu_status[5] <= 1'b1;
end
BIT_ZPG, BIT_ABS : begin
alu_status[Z] <= STATUS[Z];
192,6 → 184,11
alu_status <= STATUS;
end
default : begin
alu_result <= 8'hFF;
alu_status <= 8'hFF;
A <= 8'hFF;
alu_x <= 8'hFF;
alu_y <= 8'hFF;
end
endcase
end
198,32 → 195,31
end
 
always @ (*) begin
if (alu_enable == 1) begin
op1 = A;
op2 = alu_a;
result = A[7:0];
result[9:8] = 0;
STATUS[N] = alu_status[N];
STATUS[C] = alu_status[C];
STATUS[V] = alu_status[V];
STATUS[B] = alu_status[B];
STATUS[I] = alu_status[I];
STATUS[D] = alu_status[D];
STATUS[Z] = alu_status[Z];
STATUS[5] = 1;
bcdl = 0;
bcdh = 0;
bcdh2 = 0;
AL = 0;
AH = 0;
sign = op2[7];
op1 = A;
op2 = alu_a;
result = {2'd0, A[7:0]};
result[9:8] = 2'b00;
STATUS[N] = alu_status[N];
STATUS[C] = alu_status[C];
STATUS[V] = alu_status[V];
STATUS[B] = alu_status[B];
STATUS[I] = alu_status[I];
STATUS[D] = alu_status[D];
STATUS[Z] = alu_status[Z];
STATUS[5] = 1'b1;
 
bcdl = 8'd0;
bcdh = 8'd0;
bcdh2 = 8'd0;
AL = 8'd0;
AH = 8'd0;
 
if (alu_enable == 1'b1) begin
case (alu_opcode)
// BIT - Bit Test
BIT_ZPG, BIT_ABS: begin
result[7:0] = A & alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
230,7 → 226,7
// PLA - Pull Accumulator
PLA_IMP : begin
result[7:0] = alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
241,7 → 237,7
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX,
STA_ABY, STA_IDX, STA_IDY : begin
result[7:0] = A;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
250,7 → 246,7
// TXS - Transfer X to Stack pointer
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
result[7:0] = alu_x;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
258,49 → 254,49
// TYA - Transfer Y to Accumulator
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
result[7:0] = alu_y;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
// INC - Increment memory
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
result[7:0] = alu_a + 1;
STATUS[Z] = (result == 0) ? 1 : 0;
result[7:0] = alu_a + 8'd1;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
// INX - Increment X Register
INX_IMP: begin
result[7:0] = alu_x + 1;
STATUS[Z] = (result == 0) ? 1 : 0;
result[7:0] = alu_x + 8'd1;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
// INY - Increment Y Register
INY_IMP : begin
result[7:0] = alu_y + 1;
STATUS[Z] = (result == 0) ? 1 : 0;
result[7:0] = alu_y + 8'd1;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
// DEC - Decrement memory
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
result[7:0] = alu_a - 1;
STATUS[Z] = (result == 0) ? 1 : 0;
result[7:0] = alu_a - 8'd1;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
// DEX - Decrement X register
DEX_IMP: begin
result[7:0] = alu_x - 1;
STATUS[Z] = (result == 0) ? 1 : 0;
result[7:0] = alu_x - 8'd1;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
// DEY - Decrement Y Register
DEY_IMP: begin
result[7:0] = alu_y - 1;
STATUS[Z] = (result == 0) ? 1 : 0;
result[7:0] = alu_y - 8'd1;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
308,19 → 304,19
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS,
ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
if (!alu_status[D]) begin
result = op1 + op2 + alu_status[C];
result = op1 + op2 + {7'd0, alu_status[C]}; // this looks so ugly but the operands are all 8 bits now
STATUS[N] = result[7];
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != result[7])) ? 1'b1 : 1'b0;
STATUS[C] = result[8];
end
else begin
AL = op1[3:0] + op2[3:0] + alu_status[C];
AL = op1[3:0] + op2[3:0] + {7'd0, alu_status[C]};
AH = op1[7:4] + op2[7:4];
STATUS[Z] = (AL == 0 && AH == 0) ? 1 : 0;
if (AL > 9) begin
bcdl = AL + 6;
bcdh = AH + 1;
STATUS[Z] = (AL == 0 && AH == 0) ? 1'b1 : 1'b0;
if (AL > {4'd0,BCD_HIGH_LIMIT}) begin
bcdl = AL + {4'd0, BCD_FIX};
bcdh = AH + 8'd1;
end
else begin
bcdl = AL;
327,15 → 323,15
bcdh = AH;
end
STATUS[N] = bcdh[3];
STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1 : 0;
if (bcdh > 9) begin
bcdh2 = bcdh + 6;
STATUS[V] = ((op1[7] == op2[7]) && (op1[7] != bcdh[3])) ? 1'b1 : 1'b0;
if (bcdh > {4'd0, BCD_HIGH_LIMIT}) begin
bcdh2 = bcdh + {4'd0, BCD_FIX};
end
else begin
bcdh2 = bcdh;
end
STATUS[C] = bcdh2[4] || bcdh2[5];
result[7:0] = {bcdh2[3:0],bcdl[3:0]};
result[7:0] = {bcdh2[3:0], bcdl[3:0]};
end
end
343,7 → 339,7
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX,
AND_IDY : begin
result[7:0] = A & alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
351,8 → 347,8
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX,
CMP_IDY : begin
result[7:0] = A - alu_a;
STATUS[C] = (A >= alu_a) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[C] = (A >= alu_a) ? 1'b1 : 1'b0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
360,7 → 356,7
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY,
EOR_IDX, EOR_IDY : begin
result[7:0] = A ^ alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
372,7 → 368,7
LDA_IDY, LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, LDY_IMM,
LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TSX_IMP : begin
result[7:0] = alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
380,7 → 376,7
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX,
ORA_IDY : begin
result[7:0] = A | alu_a;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
387,17 → 383,17
// SBC - Subtract with Carry
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX,
SBC_IDY : begin
result = op1 - op2 - (1 - alu_status[C]);
result = op1 - op2 - (1'b1 - alu_status[C]);
STATUS[N] = result[7];
STATUS[V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[V] = ((op1[7] ^ op2[7]) && (op1[7] ^ result[7])) ? 1'b1 : 1'b0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[C] = ~(result[8] || result[9]);
if (alu_status[D]) begin
AL = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
AL = op1[3:0] - op2[3:0] - (1'b1 - alu_status[C]);
AH = op1[7:4] - op2[7:4];
if (AL[4]) begin
bcdl = AL - 6;
bcdh = AH - 1;
bcdl = AL - {4'd0, BCD_FIX};
bcdh = AH - 8'd1;
end
else begin
bcdl = AL;
404,7 → 400,7
bcdh = AH;
end
if (bcdh[4]) begin
bcdh2 = bcdh - 6;
bcdh2 = bcdh - {4'd0, BCD_FIX};
end
else begin
bcdh2 = bcdh;
415,13 → 411,13
// ASL - Arithmetic Shift Left
ASL_ACC : begin
{STATUS[C],result[7:0]} = {A,1'b0};
STATUS[Z] = (result == 0) ? 1 : 0;
{STATUS[C],result[7:0]} = {A, 1'b0};
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
{STATUS[C],result[7:0]} = {alu_a,1'b0};
STATUS[Z] = (result == 0) ? 1 : 0;
{STATUS[C],result[7:0]} = {alu_a, 1'b0};
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
428,12 → 424,12
// LSR - Logical Shift Right
LSR_ACC: begin
{result[7:0],STATUS[C]} = {1'b0,A};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
{result[7:0],STATUS[C]} = {1'b0,alu_a};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
440,12 → 436,12
// ROL - Rotate Left
ROL_ACC : begin
{STATUS[C],result[7:0]} = {A,alu_status[C]};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
{STATUS[C],result[7:0]} = {alu_a,alu_status[C]};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
452,12 → 448,12
// ROR - Rotate Right
ROR_ACC : begin
{result[7:0],STATUS[C]} = {alu_status[C],A};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
{result[7:0], STATUS[C]} = {alu_status[C], alu_a};
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
464,8 → 460,8
// CPX - Compare X Register
CPX_IMM, CPX_ZPG, CPX_ABS : begin
result[7:0] = alu_x - alu_a;
STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[C] = (alu_x >= alu_a) ? 1'b1 : 1'b0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
472,12 → 468,14
// CPY - Compare Y Register
CPY_IMM, CPY_ZPG, CPY_ABS : begin
result[7:0] = alu_y - alu_a;
STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
STATUS[Z] = (result == 0) ? 1 : 0;
STATUS[C] = (alu_y >= alu_a) ? 1'b1 : 1'b0;
STATUS[Z] = (result == 0) ? 1'b1 : 1'b0;
STATUS[N] = result[7];
end
default: begin
result = 10'h3FF;
STATUS = 8'hFF;
end
endcase
end
/video.v
445,7 → 445,9
// 4 BK
if (CTRLPF[0] == 1'b1) begin// reflected PF
if (ENABL == 1'b1) begin // the ball is enabled
if (vert_counter == bl_position) begin
pixel = COLUPF;
end
end
else begin
if (vert_counter < 4) begin
489,15 → 491,11
end
end
end
// 1: ordem de avaliacao
// 2: pinta da cor do objeto
// 3: senao pinta de bk
 
pixel = 3'd4;
 
end
end
 
endmodule
 

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