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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 76 to Rev 77
    ↔ Reverse comparison
  •

Rev 76 → Rev 77

/t6507lp_fsm.v
129,7 → 129,7
else begin
state <= next_state;
control <= MEM_READ;
data_out = 8'hZ;
case (state)
RESET: begin
// The processor was reset
160,6 → 160,13
address <= next_pc;
temp_addr[7:0] <= data_in;
end
else if (zero_page) begin
pc <= next_pc;
address <= {{5{1'b0}},data_in};
if (write) begin
control <= MEM_WRITE;
end
end
end
FETCH_HIGH: begin
if (jump) begin
172,6 → 179,7
temp_addr[12:8] <= data_in[4:0];
address <= {data_in[4:0],temp_addr[7:0]};
control <= MEM_WRITE;
data_out <= alu_result;
end
else begin // read_modify_write or just read
pc <= next_pc;
207,7 → 215,6
WRITE_MEM: begin
pc <= pc;
address <= pc;
data_out = 8'hzz;
end
default: begin
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
235,13 → 242,11
end
FETCH_OP: begin
next_state = FETCH_LOW;
//address = pc;
end
FETCH_OP_CALC: begin
next_state = FETCH_LOW;
alu_opcode = ir;
alu_enable = 1'b1;
//address = next_pc;
 
end
FETCH_OP_CALC_PARAM: begin
249,7 → 254,6
alu_opcode = ir;
alu_enable = 1'b1;
alu_a = temp_data;
//address = next_pc;
end
FETCH_LOW: begin
if (accumulator || implied) begin
260,11 → 264,21
else if (immediate) begin
next_state = FETCH_OP_CALC_PARAM;
end
else if (zero_page) begin
if (read || read_modify_write) begin
next_state = READ_MEM;
end
else if (write) begin
next_state = WRITE_MEM;
end
else begin
$write("unknown behavior");
$finish(0);
end
end
else begin // at least the absolute address mode falls here
next_state = FETCH_HIGH;
end
//address = next_pc;
 
end
FETCH_HIGH: begin
if (jump) begin
304,7 → 318,7
endcase
end
 
// this always block is responsible for updating the address mode
// this always block is responsible for updating the address mode and the type of operation being done
always @ (*) begin //
absolute = 1'b0;
absolute_indexed = 1'b0;
356,7 → 370,7
indirect = 1'b1;
end
default: begin
$write("unknown OPCODE!");
$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
$finish();
end
endcase

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