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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl/verilog
    from Rev 95 to Rev 96
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  •

Rev 95 → Rev 96

/t6507lp_fsm_tb.v
125,7 → 125,7
fake_mem[36] = 8'h00;
fake_mem[37] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed.
fake_mem[38] = 8'h01;
fake_mem[39] = 8'h00;
fake_mem[39] = 8'd35;
fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed.
fake_mem[41] = 8'hff;
fake_mem[42] = 8'h00;
139,6 → 139,8
fake_mem[47] = 8'h0a;
fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
fake_mem[59] = 8'hff;
fake_mem[254] = 8'hff;
fake_mem[255] = 8'h11;
fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
fake_mem[316] = 8'hff;
fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
152,10 → 154,17
fake_mem[323] = STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored
fake_mem[324] = 8'hff;
fake_mem[325] = STA_IDX; // testing IDX mode WRITE TYPE, page not crossed;
fake_mem[326] = 8'hff;
//fake_mem[321] = LDA_IDX; // testing IDX mode READ TYPE, page crossed;
//fake_mem[322] = 8'hff;
 
fake_mem[326] = 8'h00;
fake_mem[327] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed;
fake_mem[328] = 8'h00;
fake_mem[329] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed but pointer overflowed.
fake_mem[330] = 8'hff;
/* testing IDY mode READ TYPE, page crossed.
address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
this is probably not an issue */
fake_mem[331] = LDA_IDY;
fake_mem[332] = 8'hfe;
// FALTOU O WRITE INDIRETO Y!
@(negedge clk) // will wait for next negative edge of the clock (t=20)
reset_n=1'b1;
/t6507lp_fsm.v
9,7 → 9,7
//// 6507 FSM ////
//// ////
//// TODO: ////
//// - Code the indexed indirect mode ////
//// - Fix relative mode, bit 7 means negative ////
//// - Code the indirect indexed mode ////
//// - Code the absolute indirect mode ////
//// ////
101,7 → 101,7
reg [ADDR_SIZE_:0] temp_addr; // temporary address
reg [DATA_SIZE_:0] temp_data; // temporary data
 
reg [3:0] state, next_state; // current and next state registers
reg [4:0] state, next_state; // current and next state registers
// TODO: not sure if this will be 4 bits wide. as of march 9th this was 4bit wide.
 
// wiring that simplifies the FSM logic
146,13 → 146,23
end // solution: add a temp reg i guess
end
else if (state == READ_FROM_POINTER) begin
{page_crossed, address_plus_index[7:0]} = temp_data + index;
address_plus_index[12:8] = 5'b00000;
if (indirectx) begin
{page_crossed, address_plus_index[7:0]} = temp_data + index;
address_plus_index[12:8] = 5'b00000;
end
else begin // indirecty falls here
address_plus_index[7:0] = temp_data + 8'h01;
address_plus_index[12:8] = 5'b00000;
end
end
else if (state == READ_FROM_POINTER_X) begin
{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
address_plus_index[12:8] = 5'b00000;
end
else if (state == READ_FROM_POINTER_X1) begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
end
end
 
always @ (posedge clk or negedge reset_n) begin // sequencial always block
228,7 → 238,7
temp_addr <= {{5{1'b0}}, data_in};
control <= MEM_READ;
end
else if (indirectx) begin
else if (indirectx || indirecty) begin
pc <= next_pc;
address <= data_in;
temp_data <= data_in;
370,9 → 380,15
end
READ_FROM_POINTER: begin
pc <= pc;
address <= address_plus_index;
//temp_addr[7:0] <= data_in;
control <= MEM_READ;
if (indirectx) begin
address <= address_plus_index;
end
else begin // indirecty falls here
address <= address_plus_index;
temp_addr <= {{5{1'b0}}, data_in};
end
end
READ_FROM_POINTER_X: begin
pc <= pc;
382,11 → 398,20
end
READ_FROM_POINTER_X1: begin
pc <= pc;
address <= {data_in[5:0], temp_addr[7:0]};
if (write) begin
control <= MEM_WRITE;
if (indirectx) begin
address <= {data_in[5:0], temp_addr[7:0]};
if (write) begin
control <= MEM_WRITE;
data_out <= alu_result;
end
else begin
control <= MEM_READ;
end
end
else begin
else begin // indirecty falls here
address <= address_plus_index;
temp_addr[12:8] <= data_in;
control <= MEM_READ;
end
end
465,24 → 490,34
else if (relative) begin
next_state = FETCH_OP_EVAL_BRANCH;
end
else if (indirectx) begin
else if (indirectx || indirecty) begin
next_state = READ_FROM_POINTER;
end
end
READ_FROM_POINTER: begin
next_state = READ_FROM_POINTER_X;
if (indirectx) begin
next_state = READ_FROM_POINTER_X;
end
else begin // indirecty falls here
next_state = READ_FROM_POINTER_X1;
end
end
READ_FROM_POINTER_X: begin
next_state = READ_FROM_POINTER_X1;
end
READ_FROM_POINTER_X1: begin
if (read || read_modify_write) begin
next_state = READ_MEM;
if (indirecty) begin
next_state = READ_MEM_FIX_ADDR;
end
else if (write) begin
alu_opcode = ir;
alu_enable = 1'b1;
next_state = WRITE_MEM;
else begin
if (read || read_modify_write) begin
next_state = READ_MEM;
end
else if (write) begin
alu_opcode = ir;
alu_enable = 1'b1;
next_state = WRITE_MEM;
end
end
end
FETCH_OP_EVAL_BRANCH: begin

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