URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl/verilog
- from Rev 97 to Rev 98
- ↔ Reverse comparison
Rev 97 → Rev 98
/t6507lp_fsm_tb.v
6,10 → 6,12
//// http://www.opencores.org/cores/t6507lp/ //// |
//// //// |
//// Description //// |
//// 6507 FSM //// |
//// 6507 FSM testbench //// |
//// //// |
//// TODO: //// |
//// - Perform simple tests before going into serious verification //// |
//// - Test indirect indexed mode //// |
//// - Test absolute indirect mode //// |
//// - Test special stack instructions //// |
//// //// |
//// Author(s): //// |
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com //// |
56,7 → 58,7
reg [7:0] alu_y; |
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wire [12:0] address; |
wire control; // one bit is enough? read = 0, write = 1 |
wire control; |
wire [7:0] data_out; |
wire [7:0] alu_opcode; |
wire [7:0] alu_a; |
64,7 → 66,7
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integer i; |
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`include "../T6507LP_Package.v" |
`include "../T6507LP_Package.v" // TODO: remove this include |
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t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y); |
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