URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
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- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl
- from Rev 144 to Rev 145
- ↔ Reverse comparison
Rev 144 → Rev 145
/verilog/t6507lp_alu.v
167,11 → 167,10
alu_status[V] <= alu_a[6]; |
alu_status[N] <= alu_a[7]; |
end |
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : |
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX, ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : |
begin |
alu_result <= result; |
alu_status <= STATUS; |
|
end |
default : begin |
//$display("ERROR"); |
391,18 → 390,22
|
// ASL - Arithmetic Shift Left |
ASL_ACC : begin |
{STATUS[C],result} = A << 1; |
//{STATUS[C],result} = A << 1; |
{STATUS[C],result} = {A,1'b0}; |
end |
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin |
{STATUS[C],result} = alu_a << 1; |
//{STATUS[C],result} = alu_a << 1; |
{STATUS[C],result} = {alu_a,1'b0}; |
end |
|
// LSR - Logical Shift Right |
LSR_ACC: begin |
{result, STATUS[C]} = A >> 1; |
//{result, STATUS[C]} = A >> 1; |
{result,STATUS[C]} = {1'b0,A}; |
end |
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin |
{result, STATUS[C]} = alu_a >> 1; |
//{result, STATUS[C]} = alu_a >> 1; |
{result,STATUS[C]} = {1'b0,alu_a}; |
end |
|
// ROL - Rotate Left |
/verilog/t6507lp_alu_tb.v
102,10 → 102,38
check(); |
end |
|
// ADC |
alu_opcode = ASL_ABS; |
for (i = 0; i < 1000; i = i + 1) |
begin |
alu_a = i; |
@(negedge clk); |
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); |
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y); |
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result); |
{alu_status_expected[C], alu_result_expected} = {alu_a,1'b0}; |
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; |
alu_status_expected[N] = alu_result_expected[7]; |
check(); |
end |
|
// LDA |
alu_a = 0; |
alu_opcode = LDA_IMM; |
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); |
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result); |
@(negedge clk); |
alu_result_expected = 8'h00; |
// NV1BDIZC |
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0; |
alu_status_expected[N] = alu_result_expected[7]; |
check(); |
|
// SBC |
alu_opcode = SBC_IMM; |
for (i = 0; i < 1000; i = i + 1) |
begin |
alu_a = 1; |
@(negedge clk); |
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable); |
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y); |