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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl
    from Rev 154 to Rev 156
    ↔ Reverse comparison
  •

Rev 154 → Rev 156

/verilog/t6507lp_alu.v
327,6 → 327,8
STATUS[V] = 1;
else
STATUS[V] = 0;
$display("op1 + op2 + C = result + C (V)");
$display("%d + %d + %b = %d + %b (%b)", op1, op2, alu_status[C],result,STATUS[C],STATUS[V]);
 
if (alu_status[D] == 1) begin
if (result[3:0] > 9) begin
352,7 → 354,9
 
// EOR - Exclusive OR
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
result = A ^ alu_a ;
result = A ^ alu_a;
$display("op1 ^ op2 = result");
$display("%d ^ %d = %d", op1, op2, result);
end
 
// LDA - Load Accumulator
/verilog/t6507lp_alu_tb.v
21,6 → 21,7
 
reg c_aux;
reg [7:0] temp;
reg sign;
 
t6507lp_alu DUT (
.clk (clk),
96,10 → 97,11
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], DUT.result);
sign = alu_result_expected[7];
{alu_status_expected[C], alu_result_expected} = alu_a + alu_result_expected + alu_status_expected[C];
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
check();
end
 
119,6 → 121,35
end
 
// LDA
alu_a = 137;
alu_opcode = LDA_IMM;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
@(negedge clk);
alu_result_expected = 8'd137;
// NV1BDIZC
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
check();
// EOR
alu_opcode = EOR_IMM;
for (i = 0; i < 1000; i = i + 1)
begin
alu_a = i;
@(negedge clk);
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
$display("result_expected = %d",alu_result_expected);
alu_result_expected = alu_a ^ alu_result_expected;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
$display("result_expected = %d", alu_result_expected);
check();
end
 
// LDA
alu_a = 0;
alu_opcode = LDA_IMM;
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
139,10 → 170,11
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);
//$display("DUT.A = %h DUT.X = %h DUT.Y = %h", DUT.A, DUT.X, DUT.Y);
//$display("op1 = %d op2 = %d c = %d d = %d n = %d v = %d result = %d", alu_a, DUT.A, alu_status[C], alu_status[D], alu_status[N], alu_status[V], alu_result);
sign = alu_result_expected[7];
{alu_status_expected[C], alu_result_expected} = alu_result_expected - alu_a - ~alu_status_expected[C];
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
alu_status_expected[V] = ((alu_a[7] == DUT.A[7]) && (alu_a[7] != alu_result_expected[7]));
alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
check();
end
 
294,7 → 326,7
begin
alu_a = i;
@(negedge clk);
alu_result_expected = i & alu_result_expected;
alu_result_expected = alu_a & alu_result_expected;
alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
alu_status_expected[N] = alu_result_expected[7];
//$display("i = %d alu_opcode = %h alu_enable = %d", i, alu_opcode, alu_enable);

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