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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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    /t6507lp/trunk/rtl
    from Rev 210 to Rev 211
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Rev 210 → Rev 211

/verilog/t2600_kb_tb.v
0,0 → 1,68
////////////////////////////////////////////////////////////////////////////
//// ////
//// T2600LP IP Core ////
//// ////
//// This file is part of the T2600LP project ////
//// http://www.opencores.org/cores/t2600/ ////
//// ////
//// Description ////
//// t2600 keyboard controller ////
//// ////
//// TODO: ////
//// ////
//// Author(s): ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module t2600_kb_tb();
// all inputs are regs
reg clk;
reg reset_n;
// all outputs are wires
wire [15:0] io_lines;
initial clk = 0;
always #10 clk <= ~clk;
 
always @(posedge clk) begin
//$display("reset is %b", reset_n);
//$display("alu_enable is %b", alu_enable);
//$display("alu_opcode is %h", alu_opcode);
//$display("alu_a is %d", alu_a);
end
t2600_kb t2600_kb (
.CLK (clk),
.RST (reset_n),
.io_lines (alu_enable)
);
endmodule

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