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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk/rtl
    from Rev 212 to Rev 214
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Rev 212 → Rev 214

/verilog/t2600.v
70,9 → 70,36
.data (data)
);
 
t2600_bus t2600_bus (
.address (address),
.data_from_cpu (data_from_cpu),
.cpu_rw_mem (cpu_rw_mem),
.riot_data (riot_data),
.rom_data (rom_data),
.tia_data (tia_data),
.address_riot (address_riot),
.address_rom (address_rom),
.address_tia (address_tia),
.data_to_cpu (data_to_cpu),
.enable_riot (enable_riot),
.enable_rom (enable_rom),
.enable_tia (enable_tia),
.rw_mem (rw_mem)
);
 
T2600_KB T2600_KB (
.CLK (clk),
.RST (reset_n),
.io_lines (io_lines),
.KC (kc),
.KD (kd)
);
 
 
 
 
 
// VIDEO
// BUS CONTROLLER
 
endmodule
 
/verilog/t2600_kb_tb.v
47,22 → 47,39
// all inputs are regs
reg clk;
reg reset_n;
reg kd;
reg kc;
// all outputs are wires
wire [15:0] io_lines;
 
always #10 clk <= ~clk;
initial clk = 0;
always #10 clk <= ~clk;
initial begin
clk = 1'b0;
reset_n = 1'b1;
kd = 1'b0;
kc = 1'b0;
 
always @(posedge clk) begin
//$display("reset is %b", reset_n);
//$display("alu_enable is %b", alu_enable);
//$display("alu_opcode is %h", alu_opcode);
//$display("alu_a is %d", alu_a);
#10;
reset_n = 1'b0;
#40000;
$finish;
end
t2600_kb t2600_kb (
 
always @(clk) begin
kc = $random;
kd = $random;
end
 
 
T2600_KB T2600_KB (
.CLK (clk),
.RST (reset_n),
.io_lines (alu_enable)
.io_lines (io_lines),
.KC (kc),
.KD (kd)
);
 
 
endmodule
/vhdl/t2600_kb.vhd
28,16 → 28,16
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity t2600_kb is
entity T2600_KB is
Port ( CLK, RST, KD, KC: in std_logic;
--an: out std_logic_vector (3 downto 0);
--sseg: out std_logic_vector (6 downto 0);
io_lines: out std_logic_vector (15 downto 0)
);
end t2600_kb;
end T2600_KB;
 
architecture Behavioral of t2600_kb is
------------------------------------------------------------------------
124,10 → 124,10
io_lines(8) <= '1' when WaitReg = x"1d" else '0'; -- w
io_lines(7) <= '1' when WaitReg = x"05" else '0'; -- F1, p1 dif
io_lines(6) <= '1' when WaitReg = x"06" else '0'; -- F2, p0 dif
--io_lines(5) <= '1' when WaitReg = x"72" else '0'; -- not used
--io_lines(4) <= '1' when WaitReg = x"75" else '0'; -- not used
io_lines(5) <= '0'; -- not used
io_lines(4) <= '0'; -- not used
io_lines(3) <= '1' when WaitReg = x"04" else '0'; -- F3, color
--io_lines(2) <= '1' when WaitReg = x"1c" else '0'; -- not used
io_lines(2) <= '0'; -- not used
io_lines(1) <= '1' when WaitReg = x"0c" else '0'; -- F4, game select
io_lines(0) <= '1' when WaitReg = x"03" else '0'; -- F5, game select
 

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