URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk/rtl
- from Rev 222 to Rev 223
- ↔ Reverse comparison
Rev 222 → Rev 223
/verilog/vga_controller.v
46,15 → 46,15
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module vga_controller ( reset, clk_50, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS); |
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input reset, |
input clk_50, |
input [8:0] SW, |
output reg [3:0] VGA_R, |
output reg [3:0] VGA_G, |
output reg [3:0] VGA_B, |
output [9:0] LEDR, |
output reg VGA_VS, |
output reg VGA_HS |
input reset; |
input clk_50; |
input [8:0] SW; |
output reg [3:0] VGA_R; |
output reg [3:0] VGA_G; |
output reg [3:0] VGA_B; |
output [9:0] LEDR; |
output reg VGA_VS; |
output reg VGA_HS; |
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reg clk_25; |
/verilog/controller_test.v
45,7 → 45,7
`include "timescale.v" |
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//module vga_tester (reset_n, clk_50); |
module vga_tester(line, vert_counter); |
module controller_test(line, vert_counter); |
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//input reset_n; |
//input clk_50; |
86,11 → 86,9
if (reset_n == 0) begin |
clk_358 <= 1'b0; |
counter <= 4'd0; |
vert_counter <= 6'd0; |
red <= 4'b1010; |
green <= 4'b0001; |
blue <= 4'b1110; |
line <= 480'd0; |
end |
else begin |
if (counter == 4'h6) begin |
106,7 → 104,9
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always @ (posedge clk_358 or negedge reset_n) begin |
if (reset_n == 0) begin |
if (reset_n == 0) begin |
vert_counter <= 6'd0; |
line <= 480'd0; |
end |
else begin |
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122,7 → 122,7
vert_counter <= vert_counter + 5'd1; |
end |
end |
end |
end |
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always @(*) begin |
pixel0 = {red, green, blue}; |