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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk
    from Rev 145 to Rev 146
    ↔ Reverse comparison
  •

Rev 145 → Rev 146

/rtl/verilog/t6507lp_fsm_tb.v
62,7 → 62,7
 
integer my_i;
 
`include "T6507LP_Package.v"
`include "t6507lp_package.v"
 
t6507lp_fsm #(8,13) t6507lp_fsm(
.clk(clk),
/rtl/verilog/t6507lp_fsm.v
101,7 → 101,7
localparam RESET = 5'b11111;
 
// OPCODES TODO: verify how this get synthesised
`include "T6507LP_Package.v"
`include "t6507lp_package.v"
 
// mem_rw signals
localparam MEM_READ = 1'b0;
198,6 → 198,8
end
end
 
reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles
 
always @ (posedge clk or negedge reset_n) begin // sequencial always block
if (reset_n == 1'b0) begin
// all registers must assume default values
211,12 → 213,14
address <= 13'h0000;
mem_rw <= MEM_READ;
data_out <= 8'h00;
rst_counter <= 0;
end
else begin
state <= next_state;
 
case (state)
RESET: begin // The processor was reset
rst_counter <= rst_counter + 1;
sp <= 9'b100000000; // this prevents flipflops with different drivers
//$write("under reset");
end
580,7 → 584,9
 
case (state)
RESET: begin
next_state = FETCH_OP;
if (rst_counter == 6) begin
next_state = FETCH_OP;
end
end
FETCH_OP: begin
next_state = FETCH_LOW;
/fv/alu_chk.e
61,6 → 61,12
out("CYCLE ", count_cycles, ": just comparing");
};
RESET: {
reg_x = 0;
reg_y = 0;
reg_status = 8'b00100010;
reg_a = 0; // TODO: check this
reg_result = 0;
return;
};
default: {
70,8 → 76,7
// here i have already calculated. must compare!
//if (count_cycles > 3) {
if (reg_result != alu_result) {
if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
print inst;
print me;
print alu_result;
81,20 → 86,7
dut_error("WRONG!");
};
 
if (reg_x != alu_x) {
dut_error("WRONG!");
};
 
if (reg_y != alu_y) {
dut_error("WRONG!");
};
 
if (reg_status != alu_status) {
dut_error("WRONG!");
};
//};
}
};
};
 
execute() is {
153,8 → 145,10
};
 
exec_sum() is {
out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
reg_result = reg_a + inst.alu_a + reg_status[0:0];
update_c(reg_a, inst.alu_a, reg_status[0:0]);
update_v(reg_a, inst.alu_a, reg_result);
update_z(reg_result);
update_n(reg_result);
reg_a = reg_result;
162,15 → 156,6
//dut_error();
};
 
update_z(arg : byte) is {
if (arg == 0) {
reg_status[1:1] = 1;
}
else {
reg_status[1:1] = 0;
}
};
update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
if (arg1 + arg2 + arg3 > 256) {
reg_status[0:0] = 1;
180,6 → 165,25
}
};
 
update_v(op1 : byte, op2 : byte, res : byte) is {
if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
reg_status[6:6] = 1;
}
else {
reg_status[6:6] = 0;
};
};
 
update_z(arg : byte) is {
if (arg == 0) {
reg_status[1:1] = 1;
}
else {
reg_status[1:1] = 0;
}
};
 
 
update_n(arg : byte) is {
if (arg[7:7] == 1) {
reg_status[7:7] = 1;

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