URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk
- from Rev 169 to Rev 170
- ↔ Reverse comparison
Rev 169 → Rev 170
/fv/alu_opcodes.e
14,8 → 14,8
LDA_IDY = 8'hB1, LDX_IMM = 8'hA2, LDX_ZPG = 8'hA6, LDX_ZPY = 8'hB6, LDX_ABS = 8'hAE, LDX_ABY = 8'hBE, LDY_IMM = 8'hA0, LDY_ZPG = 8'hA4, |
LDY_ZPX = 8'hB4, LDY_ABS = 8'hAC, LDY_ABX = 8'hBC, LSR_ACC = 8'h4A, LSR_ZPG = 8'h46, LSR_ZPX = 8'h56, LSR_ABS = 8'h4E, LSR_ABX = 8'h5E, |
NOP_IMP = 8'hEA, ORA_IMM = 8'h09, ORA_ZPG = 8'h05, ORA_ZPX = 8'h15, ORA_ABS = 8'h0D, ORA_ABX = 8'h1D, ORA_ABY = 8'h19, ORA_IDX = 8'h01, |
ORA_IDY = 8'h11, PHA_IMP = 8'h48, PHP_IMP = 8'h08, PLA_IMP = 8'h68, PLP_IMP = 8'h28];//, ROL_ACC = 8'h2A, ROL_ZPG = 8'h26, ROL_ZPX = 8'h36, |
//ROL_ABS = 8'h2E, ROL_ABX = 8'h3E]; //, ROR_ACC = 8'h6A, ROR_ZPG = 8'h66, ROR_ZPX = 8'h76, ROR_ABS = 8'h6E, ROR_ABX = 8'h7E, RTI_IMP = 8'h40, |
ORA_IDY = 8'h11, PHA_IMP = 8'h48, PHP_IMP = 8'h08, PLA_IMP = 8'h68, PLP_IMP = 8'h28, ROL_ACC = 8'h2A, ROL_ZPG = 8'h26, ROL_ZPX = 8'h36, |
ROL_ABS = 8'h2E, ROL_ABX = 8'h3E]; //, ROR_ACC = 8'h6A, ROR_ZPG = 8'h66, ROR_ZPX = 8'h76, ROR_ABS = 8'h6E, ROR_ABX = 8'h7E, RTI_IMP = 8'h40, |
// RTS_IMP = 8'h60, SBC_IMM = 8'hE9, SBC_ZPG = 8'hE5, SBC_ZPX = 8'hF5, SBC_ABS = 8'hED, SBC_ABX = 8'hFD, SBC_ABY = 8'hF9, SBC_IDX = 8'hE1, |
// SBC_IDY = 8'hF1, SEC_IMP = 8'h38, SED_IMP = 8'hF8, SEI_IMP = 8'h78, STA_ZPG = 8'h85, STA_ZPX = 8'h95, STA_ABS = 8'h8D, STA_ABX = 8'h9D, |
// STA_ABY = 8'h99, STA_IDX = 8'h81, STA_IDY = 8'h91, STX_ZPG = 8'h86, STX_ZPY = 8'h96, STX_ABS = 8'h8E, STY_ZPG = 8'h84, STY_ZPX = 8'h94, |
/fv/alu_chk.e
242,11 → 242,11
reg_status[5:5] = 1; // this is always one |
}; |
|
//ROL_ACC: { exec_rol(reg_a); }; |
//ROL_ZPG: { exec_rol(inst.alu_a); }; |
//ROL_ZPX: { exec_rol(inst.alu_a); }; |
//ROL_ABS: { exec_rol(inst.alu_a); }; |
//ROL_ABX: { exec_rol(inst.alu_a); }; |
ROL_ACC: { exec_rol(reg_a); }; |
ROL_ZPG: { exec_rol(inst.alu_a); }; |
ROL_ZPX: { exec_rol(inst.alu_a); }; |
ROL_ABS: { exec_rol(inst.alu_a); }; |
ROL_ABX: { exec_rol(inst.alu_a); }; |
|
default: { |
out(inst.alu_opcode); |
263,9 → 263,9
arg1 = arg1 << 1; |
arg1[0:0] = oldcarry; |
|
reg_result = reg_a; |
update_z(reg_a); |
update_n(reg_a); |
reg_result = arg1; |
update_z(arg1); |
update_n(arg1); |
}; |
|
exec_or() is { |
366,6 → 366,8
var op1 : byte; |
var op2 : byte; |
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out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]); |
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op1 = inst.alu_a[3:0]; |
op2 = inst.alu_a[7:4]; |
|
375,10 → 377,16
op1 = reg_a[3:0] + op1 + reg_status[0:0]; |
op2 = reg_a[7:4] + op2; |
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print op1; |
print op2; |
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if (op1 >= 10) { |
op2 = op2 + op1/ 10; |
op1 = op1 % 10; |
op2 = op2 + 1; |
}; |
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print op1; |
print op2; |
|
if (op2 >= 10) { |
op2 = op2 % 10; |