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Rev 220 → Rev 221

/rtl/verilog/vga_controller.v
0,0 → 1,222
////////////////////////////////////////////////////////////////////////////
//// ////
//// t2600 IP Core ////
//// ////
//// This file is part of the t2600 project ////
//// http://www.opencores.org/cores/t2600/ ////
//// ////
//// Description ////
//// VGA controller ////
//// ////
//// TODO: ////
//// - Feed the controller with data ////
//// ////
//// Author(s): ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
//// ////
////////////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module vga_controller (
input reset,
input clk_50,
input [8:0] SW,
output reg [3:0] VGA_R,
output reg [3:0] VGA_G,
output reg [3:0] VGA_B,
output [9:0] LEDR,
output reg VGA_VS,
output reg VGA_HS
);
 
reg clk_25;
reg [9:0] hc;
reg [9:0] vc;
reg vsenable;
wire vidon;
 
assign LEDR = SW;
 
always @ (posedge clk_50 or negedge reset)
begin
if (!reset) begin
clk_25 <= 0;
end
else begin
clk_25 <= !clk_25;
end
end
 
always @ (posedge clk_25 or negedge reset)
begin
if (!reset) begin
hc <= 0;
VGA_HS <= 1;
vsenable <= 0;
end
else if (hc < 640) begin
hc <= hc + 1;
vsenable <= 0;
VGA_HS <= 1;
end
else if (hc < 640 + 16) begin
VGA_HS <= 1;
hc <= hc + 1;
vsenable <= 0;
end
else if (hc < 640 + 16 + 96) begin
VGA_HS <= 0;
hc <= hc + 1;
vsenable <= 0;
end
else if (hc < 640 + 16 + 96 + 48) begin
VGA_HS <= 1;
hc <= hc + 1;
vsenable <= 0;
end
else begin
VGA_HS <= 1;
hc <= 0;
vsenable <= 1;
end
end
 
always @ (posedge clk_25 or negedge reset)
begin
if (!reset) begin
vc <= 0;
VGA_VS <= 1;
end
else begin
if (vsenable == 1) begin
vc <= vc + 1;
end
if (vc < 480) begin
VGA_VS <= 1;
end
else if (vc < 480 + 11) begin
VGA_VS <= 1;
end
else if (vc < 480 + 11 + 2) begin
VGA_VS <= 0;
end
else if (vc < 480 + 11 + 2 + 31) begin
VGA_VS <= 1;
end
else begin
vc <= 0;
VGA_VS <= 1;
end
end
end
 
always @ (posedge clk_25)
begin
if (vidon == 1) begin
if (hc < 320) begin
if (vc < 240) begin
VGA_R[0] <= 1;
VGA_G[0] <= 1;
VGA_B[0] <= 1;
VGA_R[1] <= 1;
VGA_G[1] <= 1;
VGA_B[1] <= 1;
VGA_R[2] <= 1;
VGA_G[2] <= 1;
VGA_B[2] <= 1;
VGA_R[3] <= 1;
VGA_G[3] <= 1;
VGA_B[3] <= 1;
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 1;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 1;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 1;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 1;
end
end
else begin
if (vc < 240) begin
VGA_R[0] <= 1;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 1;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 1;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 1;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 1;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 1;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 1;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 1;
VGA_B[3] <= 0;
end
end
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
end
 
assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
 
endmodule
/rtl/verilog/video.v
74,6 → 74,10
reg [6:0] COLUPF; // color-lum playfield
reg [6:0] COLUBK; // color-lum background
reg [4:0] CTRLPF; // control playfield ball size & collisions
// D0 = REF (reflect playfield)
// D1 = SCORE (left half of playfield gets color of player 0, right half gets color of player 1)
// D2 = PFP (playfield gets priority over players so they can move behind the playfield)
// D4 & D5 = BALL SIZE
reg REFP0; // reflect player 0
reg REFP1; // reflect player 1
reg [3:0] PF0; // playfield register byte 0
107,7 → 111,6
reg RESMP1; // reset missile 1 to player 1
reg HMOVE; // s t r o b e apply horizontal motion
reg HMCLR; // s t r o b e clear horizontal motion registers
reg CXCLR ; // s t r o b e clear collision latches
 
reg [1:0] CXM0P; // read collision MO P1 M0 P0
reg [1:0] CXM1P; // read collision M1 P0 M1 P1
282,8 → 285,15
6'h2b: begin
HMCLR <= 1'b1; // STROBE
end
6'h2c: begin
CXCLR <= 1'b1; // STROBE
6'h2c: begin // cxclr STROBE
CXM0P <= 2'b0; // read collision MO P1 M0 P0
CXM1P <= 2'b0; // read collision M1 P0 M1 P1
CXP0FB <= 2'b0; // read collision P0 PF P0 BL
CXP1FB <= 2'b0; // read collision P1 PF P1 BL
CXM0FB <= 2'b0; // read collision M0 PF M0 BL
CXM1FB <= 2'b0; // read collision M1 PF M1 BL
CXBLPF <= 2'b0; // read collision BL PF unused
CXPPMM <= 2'b0; // read collision P0 P1 M0 M1
end
default: begin
end

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