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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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  • This comparison shows the changes necessary to convert path 
    /t6507lp/trunk
    from Rev 69 to Rev 70
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Rev 69 → Rev 70

/rtl/verilog/t6507lp_fsm.v
109,7 → 109,7
wire [ADDR_SIZE-1:0] next_pc;
assign next_pc = pc + 13'b0000000000001;
 
always @ (posedge clk_in or negedge rst_in_n) begin
always @ (posedge clk_in or negedge rst_in_n) begin // sequencial always block
if (rst_in_n == 1'b0) begin
// TODO: all internal flip-flops must assume default values
130,17 → 130,19
FETCH_OP: begin // this state is the simplest one. it is a simple fetch that must be done when the cpu was reset or
// the last cycle was a memory write.
pc <= next_pc;
ir <= data_in;
end
FETCH_OP_CALC: begin // this is the pipeline happening!
pc <= next_pc;
ir <= data_in;
end
FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
if (accumulator || implied) begin
pc <= pc; // is this necessary?
pc <= pc; // is this better?
end
else begin
else if (immediate) begin
pc <= next_pc;
ir <= data_in; // opcode must be saved in the instruction register
temp_data <= data_in; // the follow-up byte is saved in temp_data
end
end
default: begin
152,14 → 154,59
end
end
 
always @ (*) begin // this is the next_state logic and output logic always block
address = pc;
control = MEM_READ;
data_out = 8'h00;
alu_opcode = 8'h00;
alu_a = 8'h00;
alu_enable = 1'b0;
always @ (posedge clk_in or negedge rst_in_n) begin
if (rst_in_n == 1'b0) begin
// TODO: all outputs must assume default values
address <= 0;
control <= 0; // one bit is enough? read = 0, write = 1
data_out <= 0;
alu_opcode <= 0;
alu_a <= 0;
alu_enable <= 0;
end
else begin
 
address <= pc;
case (state)
RESET: begin
// The processor was reset. No output whatsoever.
end
FETCH_OP: begin
// it is a simple fetch. no output change.
end
FETCH_OP_CALC: begin // this is the pipeline happening!
alu_opcode <= ir;
alu_a <= temp_data;
alu_enable <= 1'b1;
end
FETCH_LOW: begin // in this state the opcode is already known so truly execution begins
if (accumulator || implied) begin
alu_opcode <= ir;
alu_enable <= 1'b1;
end
else begin // nothing?
end
end
default: begin
$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef
$finish(0);
end
endcase
end
 
end
 
always @ (*) begin // this is the next_state logic always block
//address = pc;
//control = MEM_READ;
//data_out = 8'h00;
//alu_opcode = 8'h00;
//alu_a = 8'h00;
//alu_enable = 1'b0;
 
next_state = RESET; // this prevents the latch
 
begin
172,13 → 219,13
end
FETCH_OP_CALC: begin
next_state = FETCH_LOW;
alu_opcode = ir;
alu_enable = 1'b1;
//alu_opcode = ir;
//alu_enable = 1'b1;
end
FETCH_LOW: begin
if (accumulator || implied) begin
alu_opcode = data_in;
alu_enable = 1'b1;
//alu_opcode = data_in;
//alu_enable = 1'b1;
next_state = FETCH_OP;
end
else if (immediate) begin
212,46 → 259,45
write = 1'b0;
jump = 1'b0;
if (state == FETCH_LOW) begin
case (data_in)
BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
implied = 1'b1;
end
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
accumulator = 1'b1;
end
ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
immediate = 1'b1;
end
ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
zero_page = 1'b1;
end
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin
zero_page_indexed = 1'b1;
end
BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
relative = 1'b1;
end
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
absolute = 1'b1;
end
ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
absolute_indexed = 1'b1;
end
ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
indirect = 1'b1;
end
endcase
case (ir)
BRK_IMP, CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, NOP_IMP, PHA_IMP, PHP_IMP, PLA_IMP,
PLP_IMP, RTI_IMP, RTS_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, TAY_IMP, TSX_IMP, TXA_IMP, TXS_IMP, TYA_IMP: begin
implied = 1'b1;
end
ASL_ACC, LSR_ACC, ROL_ACC, ROR_ACC: begin
accumulator = 1'b1;
end
ADC_IMM, AND_IMM, CMP_IMM, CPX_IMM, CPY_IMM, EOR_IMM, LDA_IMM, LDX_IMM, LDY_IMM, ORA_IMM, SBC_IMM: begin
immediate = 1'b1;
end
ADC_ZPG, AND_ZPG, ASL_ZPG, BIT_ZPG, CMP_ZPG, CPX_ZPG, CPY_ZPG, DEC_ZPG, EOR_ZPG, INC_ZPG, LDA_ZPG, LDX_ZPG, LDY_ZPG,
LSR_ZPG, ORA_ZPG, ROL_ZPG, ROR_ZPG, SBC_ZPG, STA_ZPG, STX_ZPG, STY_ZPG: begin
zero_page = 1'b1;
end
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
SBC_ZPX, STA_ZPX, LDX_ZPY, STX_ZPY, STY_ZPX: begin
zero_page_indexed = 1'b1;
end
BCC_REL, BCS_REL, BEQ_REL, BMI_REL, BNE_REL, BPL_REL, BVC_REL, BVS_REL: begin
relative = 1'b1;
end
ADC_ABS, AND_ABS, ASL_ABS, BIT_ABS, CMP_ABS, CPX_ABS, CPY_ABS, DEC_ABS, EOR_ABS, INC_ABS, JMP_ABS, JSR_ABS, LDA_ABS,
LDX_ABS, LDY_ABS, LSR_ABS, ORA_ABS, ROL_ABS, ROR_ABS, SBC_ABS, STA_ABS, STX_ABS, STY_ABS: begin
absolute = 1'b1;
end
ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
SBC_ABX, STA_ABX, ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
absolute_indexed = 1'b1;
end
ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX, ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY,
ORA_IDY, SBC_IDY, STA_IDY: begin // all these opcodes are 8'hX1; TODO: optimize this
indirect = 1'b1;
end
endcase
if (data_in == JMP_ABS || data_in == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
jump = 1'b1;
end
if (data_in == JMP_ABS || data_in == JMP_IND) begin // the opcodes are 8'h4C and 8'h6C
jump = 1'b1;
end
 
// if (data_in == )
275,8 → 321,6
LDY_ABX = 8'hBC;
*/
 
 
end
end // no way
endmodule
 

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