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Rev 74 → Rev 75

/rtl/verilog/T6507LP.v
52,7 → 52,7
input n_rst_i;
input clk_i;
input rw_i;
input rdy_i; // TODO: this is probably output
input rdy_i;
input [7:0] D_i; // data, 8 bits wide
output [7:0] D_o;
output [12:0] A_o; // address, 13 bits wide
73,6 → 73,9
);
 
T6507LP_ALU ALU (
.clk_i (clk_i),
.n_rst_i (n_rst_i),
.alu_enable (alu_enable),
.alu_result (alu_result),
.alu_status (alu_status),
.alu_opcode (alu_opcode),
/rtl/verilog/T6507LP_ALU.v
9,7 → 9,7
//// 6507 ALU ////
//// ////
//// To Do: ////
//// - All operations ////
//// - Search for TODO ////
//// ////
//// Author(s): ////
//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
46,405 → 46,321
 
// TODO: verify code identation
 
module T6507LP_ALU( alu_result, alu_status, alu_opcode, alu_a );
module T6507LP_ALU( clk_i, n_rst_i, alu_enable, alu_result, alu_status, alu_opcode, alu_a );
 
input [7:0] alu_opcode;
input [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
reg [7:0] A;
reg [7:0] X;
reg [7:0] Y;
reg [7:0] STATUS;
//wire temp;
reg dummy;
input wire clk_i;
input wire n_rst_i;
input wire alu_enable;
input wire [7:0] alu_opcode;
input wire [7:0] alu_a;
output reg [7:0] alu_result;
output reg [7:0] alu_status;
 
reg [7:0] A;
reg [7:0] X;
reg [7:0] Y;
 
reg [7:0] STATUS;
reg [7:0] result;
 
`include "T6507LP_Package.v"
 
//wire C;
//wire B;
//wire V;
//wire D;
//wire N;
//wire I; // is it necessary? don`t think so... but for now it will remain.
//wire Z;
//assign alu_status = {N, V, 1'b1, B, D, I, Z, C};
 
always @ (*)
always @ (posedge clk_i or negedge n_rst_i)
begin
alu_status = STATUS;
end
always @ (*) // is this necessary?
begin
//if (n_rst_i)
A = A;
X = X;
Y = Y;
STATUS = STATUS;
alu_result = A;
case (alu_opcode)
BIT_ZPG, BIT_ABS:
begin
alu_result = A & alu_a;
STATUS[N] = alu_result[7];
STATUS[V] = alu_result[6];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
BRK_IMP: begin // BREAK
STATUS[B] = 1'b1;
end
CLC_IMP: begin // CLC - Clear Carry Flag. 1 byte, 2 cycles.
STATUS[C] = 1'b0;
end
CLD_IMP: begin // CLD - Clear Decimal Flag. 1 byte, 2 cycles.
STATUS[D] = 1'b0;
end
CLI_IMP: begin // CLI - Clear Interrupt Disable. 1 byte, 2 cycles. // TODO: verify if this should be supported by 6507
STATUS[I] = 1'b0;
end
CLV_IMP: begin // CLV - Clear Overflow Flag. 1 byte, 2 cycles.
STATUS[V] = 1'b0;
end
NOP_IMP: begin // NOP - . 1 byte, 2 cycles.
// Do nothing :-D
end
PHA_IMP: begin // PHA - Push A. 1 byte, 2 cycles.
alu_result = A;
end
PHP_IMP: begin // PHP - Push Processor Status Register. 1 byte, 2 cycles.
//alu_result = STATUS;
end
PLA_IMP: begin // PHA - Pull A. 1 byte, 2 cycles.
A = alu_a;
end
PLP_IMP: begin // PHP - Pull Processor Status Register. 1 byte, 2 cycles.
STATUS = alu_a;
end
TAX_IMP: begin // TAX - Transfer Accumulator to X. 1 byte, 2 cycles.
X = A;
STATUS[N] = X[7];
if (X == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
TAY_IMP: begin // TAY - Transfer Accumulator to Y. 1 byte, 2 cycles.
Y = A;
STATUS[N] = Y[7];
if (Y == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
TSX_IMP: begin // TSX - Transfer Stack Pointer to X. 1 byte, 2 cycles.
X = alu_a;
STATUS[N] = X[7];
if (X == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
TXA_IMP: begin // TXA - Transfer X to Accumulator. 1 byte, 2 cycles.
A = X;
STATUS[N] = A[7];
if (A == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
 
end
TXS_IMP: begin // TXS - Transfer X to Stack pointer. 1 byte, 2 cycles.
STATUS = X;
end
TYA_IMP: begin // TYA - Transfer Y to Accumulator. 1 byte, 2 cycles.
A = Y;
STATUS[N] = A[7];
if (A == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
SEC_IMP: begin // SEC - Set Carry Flag. 1 byte, 2 cycles.
STATUS[C] = 1'b1;
end
SED_IMP: begin // SED - Set Decimal Flag. 1 byte, 2 cycles.
STATUS[D] = 1'b1;
end
SEI_IMP: begin // SEI - Set Interrupt Disable. 1 byte, 2 cycles. // TODO: verify if this should be supported by 6507
STATUS[I] = 1'b1;
end
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX :
begin // INC - Increment memory. 1 byte, 2 cycles.
add (alu_a,1'b1,1'b0,alu_result,dummy);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
INX_IMP: begin // INX - Increment X. 1 byte, 2 cycles.
add(X,1'b1,1'b0,alu_result,dummy);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
INY_IMP : begin // INY - Increment Y. 1 byte, 2 cycles.
add(Y,1'b1,1'b0,alu_result,dummy);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX :
begin // INC - Increment memory. 1 byte, 2 cycles.
sub(alu_a,1'b1,1'b0,alu_result,dummy);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
DEX_IMP: begin // DEX - Decrement X. 1 byte, 2 cycles.
sub(X,1'b1,1'b0,X,dummy);
STATUS[N] = X[7];
if (X == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
DEY_IMP: begin // DEY - Decrement Y. 1 byte, 2 cycles.
sub(Y,1'b1,1'b0,Y,dummy);
STATUS[N] = Y[7];
if (Y == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
add(A,alu_a,STATUS[C],alu_result,STATUS[C]);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
if ((A[7] == alu_a[7]) && (A[7] != alu_result[7]))
STATUS[V] = 1;
else
STATUS[V] = 0;
A = alu_result;
end
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
alu_result = A & alu_a;
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
A = alu_result;
end
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
sub(A,alu_a,STATUS[C],alu_result,STATUS[C]);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
alu_result = A ^ alu_a ;
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
A = alu_result;
end
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
A = alu_a;
STATUS[N] = A[7];
if (A == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY :
begin // INC - Increment memory. 1 byte, 2 cycles.
X = alu_a;
STATUS[N] = X[7];
if (X == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX :
begin // INC - Increment memory. 1 byte, 2 cycles.
Y = alu_a;
STATUS[N] = Y[7];
if (Y == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
alu_result = A;
end
STX_ZPG, STX_ZPY, STX_ABS :
begin // INC - Increment memory. 1 byte, 2 cycles.
alu_result = X;
end
STY_ZPG, STY_ZPX, STY_ABS :
begin // INC - Increment memory. 1 byte, 2 cycles.
alu_result = Y;
end
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
alu_result = A | alu_a;
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
A = alu_result;
end
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY :
begin // INC - Increment memory. 1 byte, 2 cycles.
sub(A,alu_a,STATUS[C],alu_result,STATUS[C]);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
if ((A[7] == alu_a[7]) && (A[7] != alu_result[7]))
STATUS[V] = 1;
else
STATUS[V] = 0;
A = alu_result;
end
ASL_ACC : begin // INC - Increment memory. 1 byte, 2 cycles.
{STATUS[C],A} = A << 1;
STATUS[N] = A[7];
if (A == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX :
begin // INC - Increment memory. 1 byte, 2 cycles.
{STATUS[C],alu_result} = alu_a << 1;
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
LSR_ACC: begin // INC - Increment memory. 1 byte, 2 cycles.
{A, STATUS[C]} = A >> 1;
STATUS[N] = A[7];
if (A == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX :
begin // INC - Increment memory. 1 byte, 2 cycles.
{alu_result, STATUS[C]} = alu_a >> 1;
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
ROL_ACC : begin // INC - Increment memory. 1 byte, 2 cycles.
{STATUS[C],A} = {A,STATUS[C]}; //TODO: does it really work?
STATUS[N] = A[7];
if (A == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX :
begin // INC - Increment memory. 1 byte, 2 cycles.
{STATUS[C],alu_result} = {alu_a,STATUS[C]}; //TODO: does it really work?
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
ROR_ACC : begin // INC - Increment memory. 1 byte, 2 cycles.
{A,STATUS[C]} = {STATUS[C],A}; //TODO: does it really work?
STATUS[N] = A[7];
if (A == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
begin // INC - Increment memory. 1 byte, 2 cycles.
{alu_result, STATUS[C]} = {STATUS[C], alu_a}; //TODO: does it really work?
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
CPX_IMM, CPX_ZPG, CPX_ABS :
if (n_rst_i == 0) begin
alu_result <= 0;
alu_status <= 8'b00100010;
A <= 0;
X <= 0;
Y <= 0;
end
else begin
alu_status <= STATUS;
alu_result <= result;
A <= A;
X <= X;
Y <= Y;
case (alu_opcode)
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY, AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY, ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY :
A <= result;
PLA_IMP :
begin
sub(X,alu_a,1'b0,alu_result,dummy);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
A <= alu_a;
end
CPY_IMM, CPY_ZPG, CPY_ABS :
begin
sub(Y,alu_a,1'b0,alu_result,dummy);
STATUS[N] = alu_result[7];
if (alu_result == 0)
STATUS[Z] = 1;
else
STATUS[Z] = 0;
end
 
default: begin // NON-DEFAULT OPCODES FALL HERE
end
endcase
end
 
task add;
input A, B, C_in;
output R;
output C_out;
begin
{C_out,R} = A + B + C_in;
end
endtask
 
task sub;
input A, B, B_in;
output R;
output B_out;
begin
{B_out,R} = A - B - ( 1 - B_in );
end
endtask
 
endmodule
end
 
always @ (*) begin
case (alu_opcode)
 
// BIT - Bit Test
BIT_ZPG, BIT_ABS:
begin
result = A & alu_a;
STATUS[V] = result[6];
end
 
// BRK - Force Interrupt
BRK_IMP: begin
STATUS[B] = 1'b1;
end
 
// CLC - Clear Carry Flag
CLC_IMP: begin
STATUS[C] = 1'b0;
end
// CLD - Clear Decimal Flag
CLD_IMP: begin
STATUS[D] = 1'b0;
end
 
// CLI - Clear Interrupt Disable.
// TODO: verify if this should be supported by 6507
CLI_IMP: begin
STATUS[I] = 1'b0;
end
 
// CLV - Clear Overflow Flag
CLV_IMP: begin
STATUS[V] = 1'b0;
end
 
// NOP - No Operation
//NOP_IMP: begin
// Do nothing :-D
//end
 
// PHA - Push A
PHA_IMP: begin
result = A;
end
 
// PHP - Push Processor Status Register
//PHP_IMP: begin
//alu_result = STATUS;
//end
 
// PHA - Pull A
//PLA_IMP: begin
//A = alu_a;
//end
 
// PHP - Pull Processor Status Register
PLP_IMP: begin
STATUS = alu_a;
end
 
// TAX - Transfer Accumulator to X
TAX_IMP: begin
result = A;
end
 
// TAY - Transfer Accumulator to Y
TAY_IMP: begin
result = A;
end
 
// TSX - Transfer Stack Pointer to X
TSX_IMP: begin
result = alu_a;
end
 
// TXA - Transfer X to Accumulator
TXA_IMP: begin
result = X;
end
 
// TXS - Transfer X to Stack pointer
TXS_IMP: begin
result = X;
end
 
// TYA - Transfer Y to Accumulator
TYA_IMP: begin
result = Y;
end
 
// SEC - Set Carry Flag
SEC_IMP: begin
STATUS[C] = 1'b1;
end
 
// SED - Set Decimal Flag
SED_IMP: begin
STATUS[D] = 1'b1;
end
 
// SEI - Set Interrupt Disable
SEI_IMP: begin
STATUS[I] = 1'b1;
end
 
// INC - Increment memory
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX :
begin
result = alu_a + 1;
end
 
// INX - Increment X Register
INX_IMP: begin
result = X + 1;
end
 
// INY - Increment Y Register
INY_IMP : begin
result = Y + 1;
end
 
// DEC - Decrement memory
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX :
begin
result = alu_a - 1;
end
 
// DEX - Decrement X register
DEX_IMP: begin
result = X - 1;
end
 
// DEY - Decrement Y Register
DEY_IMP: begin
result = Y - 1;
end
 
// ADC - Add with carry
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY :
begin
{STATUS[C],result} = A + alu_a + alu_status[C];
if ((A[7] == alu_a[7]) && (A[7] != alu_result[7]))
STATUS[V] = 1;
else
STATUS[V] = 0;
end
// AND - Logical AND
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY :
begin
result = A & alu_a;
end
 
// CMP - Compare
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY :
begin
{STATUS[C],result} = A - alu_a;// - !alu_status[C];
end
 
// EOR - Exclusive OR
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY :
begin
result = A ^ alu_a ;
end
 
// LDA - Load Accumulator
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY :
begin
result = alu_a;
end
 
// LDX - Load X Register
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY :
begin
result = alu_a;
end
 
// LDY - Load Y Register
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX :
begin
result = alu_a;
end
 
// STA - Store Accumulator
STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY :
begin
result = A;
end
 
// STX - Store X Register
STX_ZPG, STX_ZPY, STX_ABS :
begin
result = X;
end
// STY - Store Y Register
STY_ZPG, STY_ZPX, STY_ABS :
begin
result = Y;
end
 
// ORA - Logical OR
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY :
begin
result = A | alu_a;
end
 
// SBC - Subtract with Carry
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY :
begin
{STATUS[C],result} = A - alu_a - !alu_status[C];
if ((A[7] == alu_a[7]) && (A[7] != alu_result[7]))
STATUS[V] = 1;
else
STATUS[V] = 0;
end
 
// ASL - Arithmetic Shift Left
ASL_ACC : begin
{STATUS[C],result} = A << 1;
end
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX :
begin
{STATUS[C],result} = alu_a << 1;
end
 
// LSR - Logical Shift Right
LSR_ACC: begin
{result, STATUS[C]} = A >> 1;
end
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX :
begin
{result, STATUS[C]} = alu_a >> 1;
end
// ROL - Rotate Left
ROL_ACC : begin
{STATUS[C],result} = {A,alu_status[C]}; //TODO: does it really work?
end
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX :
begin
{STATUS[C],result} = {alu_a,alu_status[C]};
end
 
// ROR - Rotate Right
ROR_ACC : begin
{result,STATUS[C]} = {alu_status[C],A};
end
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
begin
{result, STATUS[C]} = {alu_status[C], alu_a};
end
 
// CPX - Compare X Register
CPX_IMM, CPX_ZPG, CPX_ABS :
begin
{STATUS[C],result} = X - alu_a;// - !alu_status[C];
end
 
// CPY - Compare Y Register
CPY_IMM, CPY_ZPG, CPY_ABS :
begin
{STATUS[C],result} = Y - alu_a;// - !alu_status[C];
end
 
default: begin // NON-DEFAULT OPCODES FALL HERE
end
endcase
end
 
endmodule
 

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