OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /t6507lp
    from Rev 152 to Rev 153
    Reverse comparison

Rev 152 → Rev 153

/trunk/rtl/verilog/t6507lp_alu_wrapper.v
65,10 → 65,10
always #10 clk <= ~clk;
 
always @(posedge clk) begin
$display("reset is %b", reset_n);
$display("alu_enable is %b", alu_enable);
$display("alu_opcode is %h", alu_opcode);
$display("alu_a is %d", alu_a);
//$display("reset is %b", reset_n);
//$display("alu_enable is %b", alu_enable);
//$display("alu_opcode is %h", alu_opcode);
//$display("alu_a is %d", alu_a);
end
t6507lp_alu t6507lp_alu (
/trunk/fv/alu_opcodes.e
3,7 → 3,7
type valid_opcodes : [
ADC_IMM = 8'h69, ADC_ZPG = 8'h65, ADC_ZPX = 8'h75, ADC_ABS = 8'h6D, ADC_ABX = 8'h7D, ADC_ABY = 8'h79, ADC_IDX = 8'h61, ADC_IDY = 8'h71,
AND_IMM = 8'h29, AND_ZPG = 8'h25, AND_ZPX = 8'h35, AND_ABS = 8'h2D, AND_ABX = 8'h3D, AND_ABY = 8'h39, AND_IDX = 8'h21, AND_IDY = 8'h31,
ASL_ACC = 8'h0A, ASL_ZPG = 8'h06, ASL_ZPX = 8'h16, ASL_ABS = 8'h0E, ASL_ABX = 8'h1E ]; //, BCC_REL = 8'h90, BCS_REL = 8'hB0, BEQ_REL = 8'hF0,
ASL_ACC = 8'h0A, ASL_ZPG = 8'h06, ASL_ZPX = 8'h16, ASL_ABS = 8'h0E, ASL_ABX = 8'h1E, BCC_REL = 8'h90, BCS_REL = 8'hB0, BEQ_REL = 8'hF0 ];
// BIT_ZPG = 8'h24, BIT_ABS = 8'h2C, BMI_REL = 8'h30, BNE_REL = 8'hD0, BPL_REL = 8'h10, BRK_IMP = 8'h00, BVC_REL = 8'h50, BVS_REL = 8'h70,
// CLC_IMP = 8'h18, CLD_IMP = 8'hD8, CLI_IMP = 8'h58, CLV_IMP = 8'hB8, CMP_IMM = 8'hC9, CMP_ZPG = 8'hC5, CMP_ZPX = 8'hD5, CMP_ABS = 8'hCD,
// CMP_ABX = 8'hDD, CMP_ABY = 8'hD9, CMP_IDX = 8'hC1, CMP_IDY = 8'hD1, CPX_IMM = 8'hE0, CPX_ZPG = 8'hE4, CPX_ABS = 8'hEC, CPY_IMM = 8'hC0,
/trunk/fv/alu_chk.e
21,8 → 21,8
store(input : alu_input_s) is {
count_cycles = count_cycles + 1;
 
out ("CYCLE ", count_cycles, " STORE:");
print input;
//out ("CYCLE ", count_cycles, " STORE:");
//print input;
 
if (first_cycle) {
inst = input;
33,10 → 33,6
next_inst = input;
};
 
 
if (count_cycles == 10000) {
dut_error();
}
};
 
compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
49,16 → 45,16
reg_result = 0;
}
else {
out ("CYCLE ", count_cycles, " COMPARE:");
print inst;
//out ("CYCLE ", count_cycles, " COMPARE:");
//print inst;
 
case inst.input_kind {
ENABLED_VALID: {
out("CYCLE ", count_cycles, ": executing and comparing");
//out("CYCLE ", count_cycles, ": executing and comparing");
execute();
};
DISABLED_VALID: {
out("CYCLE ", count_cycles, ": just comparing");
//out("CYCLE ", count_cycles, ": just comparing");
};
RESET: {
reg_x = 0;
77,8 → 73,9
// here i have already calculated. must compare!
if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
print inst;
out("#########################################################");
print me;
out("#########################################################");
print alu_result;
print alu_status;
print alu_x;
116,6 → 113,10
ASL_ABS: { exec_asl_mem(); };
ASL_ABX: { exec_asl_mem(); };
 
BCC_REL: {};
BCS_REL: {};
BEQ_REL: {};
 
default: {
//dut_error("unknown opcode");
}
145,7 → 146,7
};
 
exec_sum() is {
out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
reg_result = reg_a + inst.alu_a + reg_status[0:0];
update_c(reg_a, inst.alu_a, reg_status[0:0]);
update_v(reg_a, inst.alu_a, reg_result);
157,7 → 158,7
};
 
update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
if (arg1 + arg2 + arg3 > 256) {
if (arg1 + arg2 + arg3 > 255) {
reg_status[0:0] = 1;
}
else {

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.