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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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    /t6507lp
    from Rev 211 to Rev 212
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Rev 211 → Rev 212

/trunk/rtl/verilog/t6507lp_fsm.v
134,6 → 134,8
reg write;
reg jump;
reg jump_indirect;
reg index_is_x;
reg index_is_branch;
 
// regs for the special instructions
reg brk;
141,12 → 143,12
reg rts;
reg pha;
reg php;
reg pla;
reg pla;
reg plp;
reg jsr;
reg tsx;
reg txs;
reg nop;
reg nop;
 
wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC
assign next_pc = pc + 13'b0000000000001;
167,38 → 169,45
address_plus_index = 13'h000;
page_crossed = 1'b0;
 
if ( (state == READ_MEM_CALC_INDEX) || (state == READ_MEM_FIX_ADDR) || (state == FETCH_HIGH_CALC_INDEX) ) begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
end
else if (branch) begin
if (state == FETCH_OP_FIX_PC || state == FETCH_OP_EVAL_BRANCH) begin
{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
address_plus_index[12:8] = pc[12:8] + page_crossed; // warning: pc might feed these lines twice and cause branch failure
end // solution: add a temp reg i guess
end
else if (state == READ_FROM_POINTER) begin
if (indirectx) begin
{page_crossed, address_plus_index[7:0]} = temp_data + index;
address_plus_index[12:8] = 5'b00000;
case (state)
READ_MEM_FIX_ADDR, FETCH_HIGH_CALC_INDEX, READ_FROM_POINTER_X1: begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
end
else if (jump_indirect) begin
address_plus_index[7:0] = temp_addr[7:0] + 8'h01;
address_plus_index[12:8] = 5'b00000;
FETCH_OP_FIX_PC, FETCH_OP_EVAL_BRANCH: begin
if (branch) begin
{page_crossed, address_plus_index[7:0]} = pc[7:0] + index;
address_plus_index[12:8] = pc[12:8] + page_crossed;
// warning: pc might feed these lines twice and cause branch failure
end // solution: add a temp reg i guess
end
else begin // indirecty falls here
address_plus_index[7:0] = temp_data + 8'h01;
address_plus_index[12:8] = 5'b00000;
READ_FROM_POINTER: begin
if (indirectx) begin
{page_crossed, address_plus_index[7:0]} = temp_data + index;
//address_plus_index[12:8] = 5'b00000; // already assigned earlier at this block
end
else if (jump_indirect) begin
address_plus_index[7:0] = temp_addr[7:0] + 8'h01;
//address_plus_index[12:8] = 5'b00000;
end
else begin // indirecty falls here
address_plus_index[7:0] = temp_data + 8'h01;
//address_plus_index[12:8] = 5'b00000;
end
end
end
else if (state == READ_FROM_POINTER_X) begin
{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
address_plus_index[12:8] = 5'b00000;
end
else if (state == READ_FROM_POINTER_X1) begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
end
READ_FROM_POINTER_X: begin
{page_crossed, address_plus_index[7:0]} = temp_data + index + 8'h01;
//address_plus_index[12:8] = 5'b00000;
end
 
READ_MEM_CALC_INDEX: begin
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
//address_plus_index[12:8] = 5'b00000;
end
endcase
end
 
reg [2:0] rst_counter; // a counter to preserve the cpu idle for six cycles
217,6 → 226,7
mem_rw <= MEM_READ;
data_out <= 8'h00;
rst_counter <= 3'h0;
index <= 8'h00;
end
else begin
state <= next_state;
242,6 → 252,18
all instructions execute this cycle.
*/
FETCH_LOW: begin
//$display("index_is_x = %b",index_is_x);
if (index_is_x == 1'b1) begin
index <= alu_x;
//$display("alu_x = %d",alu_x);
end
else begin
index <= alu_y;
//$display("alu_y = %d",alu_y);
end
if (index_is_branch) begin
index <= temp_data;
end
if (accumulator || implied || txs || tsx) begin
pc <= pc; // is this better?
address <= pc;
882,8 → 904,10
relative = 1'b0;
zero_page = 1'b0;
zero_page_indexed = 1'b0;
//index_is_x = 1'b1;
index_is_branch = 1'b0;
index = 8'h00;
//index = 8'h00;
 
read = 1'b0;
read_modify_write = 1'b0;
926,15 → 950,18
ADC_ZPX, AND_ZPX, ASL_ZPX, CMP_ZPX, DEC_ZPX, EOR_ZPX, INC_ZPX, LDA_ZPX, LDY_ZPX, LSR_ZPX, ORA_ZPX, ROL_ZPX, ROR_ZPX,
SBC_ZPX, STA_ZPX, STY_ZPX: begin
zero_page_indexed = 1'b1;
index = alu_x;
index_is_x = 1'b1;
//index = alu_x;
end
LDX_ZPY, STX_ZPY: begin
zero_page_indexed = 1'b1;
index = alu_y;
index_is_x = 1'b0;
//index = alu_y;
end
BCC_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
if (!alu_status[C]) begin
branch = 1'b1;
945,7 → 972,8
end
BCS_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
 
if (alu_status[C]) begin
branch = 1'b1;
956,7 → 984,8
end
BEQ_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[Z]) begin
branch = 1'b1;
967,7 → 996,8
end
BNE_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[Z] == 1'b0) begin
branch = 1'b1;
978,7 → 1008,8
end
BPL_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
if (!alu_status[N]) begin
branch = 1'b1;
989,7 → 1020,8
end
BMI_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[N]) begin
branch = 1'b1;
1000,7 → 1032,8
end
BVC_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
if (!alu_status[V]) begin
branch = 1'b1;
1011,7 → 1044,8
end
BVS_REL: begin
relative = 1'b1;
index = temp_data;
index_is_branch = 1'b1;
//index = temp_data;
if (alu_status[V]) begin
branch = 1'b1;
1027,19 → 1061,23
ADC_ABX, AND_ABX, ASL_ABX, CMP_ABX, DEC_ABX, EOR_ABX, INC_ABX, LDA_ABX, LDY_ABX, LSR_ABX, ORA_ABX, ROL_ABX, ROR_ABX,
SBC_ABX, STA_ABX: begin
absolute_indexed = 1'b1;
index = alu_x;
index_is_x = 1'b1;
//index = alu_x;
end
ADC_ABY, AND_ABY, CMP_ABY, EOR_ABY, LDA_ABY, LDX_ABY, ORA_ABY, SBC_ABY, STA_ABY: begin
absolute_indexed = 1'b1;
index = alu_y;
index_is_x = 1'b0;
//index = alu_y;
end
ADC_IDX, AND_IDX, CMP_IDX, EOR_IDX, LDA_IDX, ORA_IDX, SBC_IDX, STA_IDX: begin
indirectx = 1'b1;
index = alu_x;
index_is_x = 1'b1;
//index = alu_x;
end
ADC_IDY, AND_IDY, CMP_IDY, EOR_IDY, LDA_IDY, ORA_IDY, SBC_IDY, STA_IDY: begin
indirecty = 1'b1;
index = alu_y;
index_is_x = 1'b0;
//index = alu_y;
end
JMP_ABS: begin
absolute = 1'b1;
1079,6 → 1117,7
txs = 1'b1;
end
default: begin
index_is_x = 1'b1;
//$write("state : %b", state);
if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc
//$write("\nunknown OPCODE!!!!! 0x%h\n", ir);
/trunk/fv/fsm_opcodes.e
4,8 → 4,8
ADC_ZPG = 8'h65,
ADC_ZPX = 8'h75,
ADC_ABS = 8'h6D,
//ADC_ABX = 8'h7D,
//ADC_ABY = 8'h79,
ADC_ABX = 8'h7D,
ADC_ABY = 8'h79,
//ADC_IDX = 8'h61,
//ADC_IDY = 8'h71,
AND_IMM = 8'h29,
12,13 → 12,13
AND_ZPG = 8'h25,
AND_ZPX = 8'h35,
AND_ABS = 8'h2D,
//AND_ABX = 8'h3D,
//AND_ABY = 8'h39,
AND_ABX = 8'h3D,
AND_ABY = 8'h39,
//AND_IDX = 8'h21,
//AND_IDY = 8'h31,
ASL_ACC = 8'h0A,
ASL_ZPG = 8'h06,
//ASL_ZPX = 8'h16,
ASL_ZPX = 8'h16,
ASL_ABS = 8'h0E,
//ASL_ABX = 8'h1E,
//BCC_REL = 8'h90,
40,8 → 40,8
CMP_ZPG = 8'hC5,
CMP_ZPX = 8'hD5,
CMP_ABS = 8'hCD,
//CMP_ABX = 8'hDD,
//CMP_ABY = 8'hD9,
CMP_ABX = 8'hDD,
CMP_ABY = 8'hD9,
//CMP_IDX = 8'hC1,
//CMP_IDY = 8'hD1,
CPX_IMM = 8'hE0,
51,7 → 51,7
//CPY_ZPG = 8'hC4,
//CPY_ABS = 8'hCC,
DEC_ZPG = 8'hC6,
//DEC_ZPX = 8'hD6,
DEC_ZPX = 8'hD6,
DEC_ABS = 8'hCE,
//DEC_ABX = 8'hDE,
DEX_IMP = 8'hCA,
60,12 → 60,12
EOR_ZPG = 8'h45,
EOR_ZPX = 8'h55,
EOR_ABS = 8'h4D,
//EOR_ABX = 8'h5D,
//EOR_ABY = 8'h59,
EOR_ABX = 8'h5D,
EOR_ABY = 8'h59,
//EOR_IDX = 8'h41,
//EOR_IDY = 8'h51,
INC_ZPG = 8'hE6,
//INC_ZPX = 8'hF6,
INC_ZPX = 8'hF6,
INC_ABS = 8'hEE,
//INC_ABX = 8'hFE,
INX_IMP = 8'hE8,
77,8 → 77,8
LDA_ZPG = 8'hA5,
LDA_ZPX = 8'hB5,
LDA_ABS = 8'hAD,
//LDA_ABX = 8'hBD,
//LDA_ABY = 8'hB9,
LDA_ABX = 8'hBD,
LDA_ABY = 8'hB9,
//LDA_IDX = 8'hA1,
//LDA_IDY = 8'hB1,
LDX_IMM = 8'hA2,
85,15 → 85,15
LDX_ZPG = 8'hA6,
LDX_ZPY = 8'hB6,
LDX_ABS = 8'hAE,
//LDX_ABY = 8'hBE,
LDX_ABY = 8'hBE,
LDY_IMM = 8'hA0,
LDY_ZPG = 8'hA4,
LDY_ZPX = 8'hB4,
LDY_ABS = 8'hAC,
//LDY_ABX = 8'hBC,
LDY_ABX = 8'hBC,
LSR_ACC = 8'h4A,
LSR_ZPG = 8'h46,
//LSR_ZPX = 8'h56,
LSR_ZPX = 8'h56,
LSR_ABS = 8'h4E,
//LSR_ABX = 8'h5E,
NOP_IMP = 8'hEA,
101,8 → 101,8
ORA_ZPG = 8'h05,
ORA_ZPX = 8'h15,
ORA_ABS = 8'h0D,
//ORA_ABX = 8'h1D,
//ORA_ABY = 8'h19,
ORA_ABX = 8'h1D,
ORA_ABY = 8'h19,
//ORA_IDX = 8'h01,
//ORA_IDY = 8'h11,
PHA_IMP = 8'h48,
111,12 → 111,12
PLP_IMP = 8'h28,
ROL_ACC = 8'h2A,
ROL_ZPG = 8'h26,
//ROL_ZPX = 8'h36,
ROL_ZPX = 8'h36,
ROL_ABS = 8'h2E,
//ROL_ABX = 8'h3E,
//ROR_ACC = 8'h6A,
ROR_ZPG = 8'h66,
//ROR_ZPX = 8'h76,
ROR_ZPX = 8'h76,
ROR_ABS = 8'h6E,
//ROR_ABX = 8'h7E,
RTI_IMP = 8'h40,
125,8 → 125,8
SBC_ZPG = 8'hE5,
SBC_ZPX = 8'hF5,
SBC_ABS = 8'hED,
//SBC_ABX = 8'hFD,
//SBC_ABY = 8'hF9,
SBC_ABX = 8'hFD,
SBC_ABY = 8'hF9,
//SBC_IDX = 8'hE1,
//SBC_IDY = 8'hF1,
SEC_IMP = 8'h38,
133,7 → 133,7
SED_IMP = 8'hF8,
SEI_IMP = 8'h78,
STA_ZPG = 8'h85,
//STA_ZPX = 8'h95,
STA_ZPX = 8'h95,
STA_ABS = 8'h8D,
//STA_ABX = 8'h9D,
//STA_ABY = 8'h99,
140,10 → 140,10
//STA_IDX = 8'h81,
//STA_IDY = 8'h91,
STX_ZPG = 8'h86,
//STX_ZPY = 8'h96,
STX_ZPY = 8'h96,
STX_ABS = 8'h8E,
STY_ZPG = 8'h84,
//STY_ZPX = 8'h94,
STY_ZPX = 8'h94,
STY_ABS = 8'h8C,
TAX_IMP = 8'hAA,
TAY_IMP = 8'hA8,
/trunk/fv/fsm_bfm.e
23,6 → 23,8
on main_clk {
var data : fsm_input_s;
var last_X : byte;
var last_Y : byte;
gen data;
 
--print mem[i];
51,8 → 53,15
data_in$ = mem[i].as_a(byte);
data.data_in = mem[i].as_a(byte);
--data_in$ = 8'hF8;
alu_x$ = data.alu_x;
alu_y$ = data.alu_y;
--print me.agent.chk.old_state;
--if (me.agent.chk.old_state == CYCLE_1) {
-- last_X = data.alu_x;
-- last_Y = data.alu_y;
--};
--alu_x$ = last_X;
--alu_y$ = last_Y;
alu_x$ = data.alu_x;
alu_y$ = data.alu_y;
if (data.reset_n == 1) {
i = i + 1;
/trunk/fv/fsm_chk.e
15,6 → 15,8
!SP : byte;
keep soft SP == 0;
 
!more_cycles : bool;
keep soft more_cycles == FALSE;
--!R : byte;
-- keep soft R == 0;
--!PS : byte;
146,6 → 148,10
new_state = CYCLE_2;
};
CYCLE_2 : {
X = input.alu_x;
Y = input.alu_y;
print X, Y;
outf("CYCLE_1\n");
case {
(
instruction == BRK_IMP ||
201,12 → 207,7
instruction == ROL_ZPG ||
instruction == ROR_ZPG ||
instruction == INC_ZPG ||
instruction == DEC_ZPG
) : {
new_state = CYCLE_3;
PCL = input.data_in;
};
(
instruction == DEC_ZPG ||
instruction == LDA_ZPX ||
instruction == LDX_ZPY ||
instruction == LDY_ZPX ||
215,14 → 216,51
instruction == ORA_ZPX ||
instruction == ADC_ZPX ||
instruction == SBC_ZPX ||
instruction == CMP_ZPX
instruction == CMP_ZPX ||
instruction == ASL_ZPX ||
instruction == LSR_ZPX ||
instruction == ROL_ZPX ||
instruction == ROR_ZPX ||
instruction == INC_ZPX ||
instruction == DEC_ZPX ||
instruction == STA_ZPX ||
instruction == STX_ZPY ||
instruction == STY_ZPX
) : {
new_state = CYCLE_3;
PCL = input.data_in;
X = alu_x;
Y = alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
};
(
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
instruction == EOR_ABY ||
instruction == AND_ABX ||
instruction == AND_ABY ||
instruction == ORA_ABX ||
instruction == ORA_ABY ||
instruction == ADC_ABX ||
instruction == ADC_ABY ||
instruction == SBC_ABX ||
instruction == SBC_ABY ||
instruction == CMP_ABX ||
instruction == CMP_ABY
) : {
new_state = CYCLE_3;
PCL = input.data_in;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_2\n");
};
(
instruction == TXS_IMP
) : {
new_state = CYCLE_1;
246,7 → 284,15
instruction == ROL_ZPG ||
instruction == ROR_ZPG ||
instruction == INC_ZPG ||
instruction == DEC_ZPG ||
instruction == DEC_ZPG
) : {
new_state = CYCLE_4;
};
//JSR_ABS : {
// new_state = CYCLE_4;
// PCH = input.data_in;
//};
(
instruction == LDA_ZPX ||
instruction == LDX_ZPY ||
instruction == LDY_ZPX ||
255,14 → 301,24
instruction == ORA_ZPX ||
instruction == ADC_ZPX ||
instruction == SBC_ZPX ||
instruction == CMP_ZPX
instruction == CMP_ZPX ||
instruction == ASL_ZPX ||
instruction == LSR_ZPX ||
instruction == ROL_ZPX ||
instruction == ROR_ZPX ||
instruction == INC_ZPX ||
instruction == DEC_ZPX ||
instruction == STA_ZPX ||
instruction == STX_ZPY ||
instruction == STY_ZPX
) : {
new_state = CYCLE_4;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
};
//JSR_ABS : {
// new_state = CYCLE_4;
// PCH = input.data_in;
//};
(
instruction == ADC_ABS ||
instruction == ASL_ABS ||
282,10 → 338,32
instruction == SBC_ABS ||
instruction == STA_ABS ||
instruction == STX_ABS ||
instruction == STY_ABS
instruction == STY_ABS ||
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
instruction == EOR_ABY ||
instruction == AND_ABX ||
instruction == AND_ABY ||
instruction == ORA_ABX ||
instruction == ORA_ABY ||
instruction == ADC_ABX ||
instruction == ADC_ABY ||
instruction == SBC_ABX ||
instruction == SBC_ABY ||
instruction == CMP_ABX ||
instruction == CMP_ABY
) : {
new_state = CYCLE_4;
PCH = input.data_in;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_3\n");
};
(
instruction == JMP_ABS
323,8 → 401,41
instruction == ROL_ZPG ||
instruction == ROR_ZPG ||
instruction == INC_ZPG ||
instruction == DEC_ZPG
instruction == DEC_ZPG ||
instruction == ASL_ZPX ||
instruction == LSR_ZPX ||
instruction == ROL_ZPX ||
instruction == ROR_ZPX ||
instruction == INC_ZPX ||
instruction == DEC_ZPX ||
(
more_cycles == TRUE &&
(
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
instruction == EOR_ABY ||
instruction == AND_ABX ||
instruction == AND_ABY ||
instruction == ORA_ABX ||
instruction == ORA_ABY ||
instruction == ADC_ABX ||
instruction == ADC_ABY ||
instruction == SBC_ABX ||
instruction == SBC_ABY ||
instruction == CMP_ABX ||
instruction == CMP_ABY
)
)
) : {
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_4\n");
new_state = CYCLE_5;
};
default : {
356,10 → 467,68
instruction == INC_ABS ||
instruction == LSR_ABS ||
instruction == ROL_ABS ||
instruction == ROR_ABS
instruction == ROR_ABS ||
instruction == ASL_ZPX ||
instruction == LSR_ZPX ||
instruction == ROL_ZPX ||
instruction == ROR_ZPX ||
instruction == INC_ZPX ||
instruction == DEC_ZPX
) : {
new_state = CYCLE_6;
};
(
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
instruction == EOR_ABY ||
instruction == AND_ABX ||
instruction == AND_ABY ||
instruction == ORA_ABX ||
instruction == ORA_ABY ||
instruction == ADC_ABX ||
instruction == ADC_ABY ||
instruction == SBC_ABX ||
instruction == SBC_ABY ||
instruction == CMP_ABX ||
instruction == CMP_ABY
) : {
new_state = CYCLE_1;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_5\n");
};
--(
-- instruction == LDA_ZPX ||
-- instruction == LDX_ZPY ||
-- instruction == LDY_ZPX ||
-- instruction == EOR_ZPX ||
-- instruction == AND_ZPX ||
-- instruction == ORA_ZPX ||
-- instruction == ADC_ZPX ||
-- instruction == SBC_ZPX ||
-- instruction == CMP_ZPX ||
-- instruction == ASL_ZPX ||
-- instruction == LSR_ZPX ||
-- instruction == ROL_ZPX ||
-- instruction == ROR_ZPX ||
-- instruction == INC_ZPX ||
-- instruction == DEC_ZPX ||
-- instruction == STA_ZPX ||
-- instruction == STX_ZPY ||
-- instruction == STY_ZPX
--) : {
-- new_state = CYCLE_1;
--X = input.alu_x;
--Y = input.alu_y;
--print input.alu_x, input.alu_y;
 
--};
default : {
new_state = CYCLE_1;
};
407,6 → 576,7
rst_counter = rst_counter + 1;
};
CYCLE_1 : {
more_cycles = FALSE;
print_state();
print addr;
last_instruction = instructions;
451,9 → 621,35
last_instruction == ADC_ZPG ||
last_instruction == SBC_ZPG ||
last_instruction == CMP_ZPG ||
last_instruction == BIT_ZPG
last_instruction == BIT_ZPG ||
last_instruction == LDA_ZPX ||
last_instruction == LDX_ZPY ||
last_instruction == LDY_ZPX ||
last_instruction == EOR_ZPX ||
last_instruction == AND_ZPX ||
last_instruction == ORA_ZPX ||
last_instruction == ADC_ZPX ||
last_instruction == SBC_ZPX ||
last_instruction == CMP_ZPX ||
last_instruction == LDA_ABX ||
last_instruction == LDA_ABY ||
last_instruction == LDX_ABY ||
last_instruction == LDY_ABX ||
last_instruction == EOR_ABX ||
last_instruction == EOR_ABY ||
last_instruction == AND_ABX ||
last_instruction == AND_ABY ||
last_instruction == ORA_ABX ||
last_instruction == ORA_ABY ||
last_instruction == ADC_ABX ||
last_instruction == ADC_ABY ||
last_instruction == SBC_ABX ||
last_instruction == SBC_ABY ||
last_instruction == CMP_ABX ||
last_instruction == CMP_ABY
) : {
if (alu_opcode != last_instruction) {
--print addr[7:0],X + PCL;
dut_error("alu_opcode is Wrong!");
};
if (alu_enable != 1) {
465,9 → 661,9
};
default : {
if (alu_opcode.as_a(byte) != 0) {
print alu_enable;
print alu_opcode;
print last_instruction;
--print alu_enable;
--print alu_opcode;
--print last_instruction;
dut_error("alu_opcode is Wrong!");
};
if (alu_enable != 0) {
554,7 → 750,41
instructions == ROL_ZPG ||
instructions == ROR_ZPG ||
instructions == INC_ZPG ||
instructions == DEC_ZPG
instructions == DEC_ZPG ||
instructions == LDA_ZPX ||
instructions == LDX_ZPY ||
instructions == LDY_ZPX ||
instructions == EOR_ZPX ||
instructions == AND_ZPX ||
instructions == ORA_ZPX ||
instructions == ADC_ZPX ||
instructions == SBC_ZPX ||
instructions == CMP_ZPX ||
instructions == ASL_ZPX ||
instructions == LSR_ZPX ||
instructions == ROL_ZPX ||
instructions == ROR_ZPX ||
instructions == INC_ZPX ||
instructions == DEC_ZPX ||
instructions == STX_ZPY ||
instructions == STY_ZPX ||
instructions == STA_ZPX ||
instructions == LDA_ABX ||
instructions == LDA_ABY ||
instructions == LDX_ABY ||
instructions == LDY_ABX ||
instructions == EOR_ABX ||
instructions == EOR_ABY ||
instructions == AND_ABX ||
instructions == AND_ABY ||
instructions == ORA_ABX ||
instructions == ORA_ABY ||
instructions == ADC_ABX ||
instructions == ADC_ABY ||
instructions == SBC_ABX ||
instructions == SBC_ABY ||
instructions == CMP_ABX ||
instructions == CMP_ABY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
564,22 → 794,16
};
PC = PC + 1;
};
-- TODO: STX and STY should not
-- TODO: they dont need access to alu at any cycle
-- TODO: because X and Y are available at alu_x and alu_y
(
instructions == STA_ABS ||
instructions == STX_ABS ||
instructions == STA_ZPG ||
instructions == STX_ABS ||
instructions == STY_ABS ||
instructions == STA_ZPG ||
instructions == STX_ZPG ||
instructions == STY_ZPG ||
instructions == LDA_ZPX ||
instructions == LDX_ZPY ||
instructions == LDY_ZPX ||
instructions == EOR_ZPX ||
instructions == AND_ZPX ||
instructions == ORA_ZPX ||
instructions == ADC_ZPX ||
instructions == SBC_ZPX ||
instructions == CMP_ZPX
instructions == STY_ZPG
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
712,7 → 936,26
// dut_error("ADDR should be equal PC!");
// };
//};
-- TODO: This is probably an error STA should not use ALU on the third cycle
(
instructions == STA_ZPX ||
instructions == STX_ZPY ||
instructions == STY_ZPX
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (addr != PCL) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == STA_ZPG ||
instructions == STX_ZPG ||
instructions == STY_ZPG
754,7 → 997,13
instructions == ORA_ZPX ||
instructions == ADC_ZPX ||
instructions == SBC_ZPX ||
instructions == CMP_ZPX
instructions == CMP_ZPX ||
instructions == ASL_ZPX ||
instructions == LSR_ZPX ||
instructions == ROL_ZPX ||
instructions == ROR_ZPX ||
instructions == INC_ZPX ||
instructions == DEC_ZPX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
788,7 → 1037,15
instructions == SBC_ABS ||
instructions == STA_ABS ||
instructions == STX_ABS ||
instructions == STY_ABS
instructions == STY_ABS ||
instructions == LDA_ABX ||
instructions == LDY_ABX ||
instructions == EOR_ABX ||
instructions == AND_ABX ||
instructions == ORA_ABX ||
instructions == ADC_ABX ||
instructions == SBC_ABX ||
instructions == CMP_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
803,8 → 1060,38
dut_error("MEM_RW should be 1 (WRITE)");
};
PC = PC + 1;
if (PCL + X > 255) {
more_cycles = TRUE;
};
};
(
instructions == LDA_ABY ||
instructions == LDX_ABY ||
instructions == AND_ABY ||
instructions == EOR_ABY ||
instructions == ORA_ABY ||
instructions == ADC_ABY ||
instructions == SBC_ABY ||
instructions == CMP_ABY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (addr != PC) {
dut_error("ADDR should be equal SP!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
PC = PC + 1;
if (PCL + Y > 255) {
more_cycles = TRUE;
};
};
(
instructions == LDA_ZPG ||
instructions == LDX_ZPG ||
instructions == LDY_ZPG ||
928,7 → 1215,13
instructions == ORA_ZPX ||
instructions == ADC_ZPX ||
instructions == SBC_ZPX ||
instructions == CMP_ZPX
instructions == CMP_ZPX ||
instructions == ASL_ZPX ||
instructions == LSR_ZPX ||
instructions == ROL_ZPX ||
instructions == ROR_ZPX ||
instructions == INC_ZPX ||
instructions == DEC_ZPX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
939,12 → 1232,21
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
--TODO: Isn`t it suppose to have ADDRH == 0????
if (addr != PCL + X) {
print addr[7:0], PCL+X, PCL, X, 't6507lp_fsm.index';
dut_error("ADDR should be equal SP!");
};
};
(
instructions == LDX_ZPY
instructions == LDA_ABX ||
instructions == LDY_ABX ||
instructions == EOR_ABX ||
instructions == AND_ABX ||
instructions == ORA_ABX ||
instructions == ADC_ABX ||
instructions == SBC_ABX ||
instructions == CMP_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
955,11 → 1257,55
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr != PCL + Y) {
dut_error("ADDR should be equal SP!");
if (PCL + X > 255) {
more_cycles = TRUE;
if (addr[7:0] != PCL + X - 256) {
--print addr[7:0], PCL + X - 256;
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
};
(
instructions == LDX_ZPY ||
instructions == LDA_ABY ||
instructions == LDX_ABY ||
instructions == EOR_ABY ||
instructions == AND_ABY ||
instructions == ORA_ABY ||
instructions == ADC_ABY ||
instructions == SBC_ABY ||
instructions == CMP_ABY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (PCL + Y > 255) {
more_cycles = TRUE;
if (addr[7:0] != PCL + Y - 256) {
print addr[7:0], PCL + Y - 256;
print PCL, Y;
print 't6507lp_fsm.index';
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR should be equal SP!");
};
};
};
(
instructions == ADC_ABS ||
instructions == AND_ABS ||
instructions == ASL_ABS ||
1036,6 → 1382,39
};
};
(
instructions == STA_ZPX ||
instructions == STY_ZPX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (addr != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == STX_ZPY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (addr != PCL + Y) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == PLA_IMP ||
instructions == PLP_IMP
) : {
1065,7 → 1444,7
dut_error("RTI_IMP is Wrong!");
};
if (addr != SP + 256) {
print addr, SP;
--print addr, SP;
dut_error("ADDR should be equal SP!");
};
SP = SP + 1;
1180,6 → 1559,80
};
};
(
instructions == LDA_ABX ||
instructions == LDY_ABX ||
instructions == EOR_ABX ||
instructions == AND_ABX ||
instructions == ORA_ABX ||
instructions == ADC_ABX ||
instructions == SBC_ABX ||
instructions == CMP_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR is wrong!");
};
if (addr[12:8] != PCH[4:0] + 1) {
dut_error("ADDR is wrong!");
};
};
(
instructions == LDX_ZPY ||
instructions == LDA_ABY ||
instructions == LDX_ABY ||
instructions == EOR_ABY ||
instructions == AND_ABY ||
instructions == ORA_ABY ||
instructions == ADC_ABY ||
instructions == SBC_ABY ||
instructions == CMP_ABY
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR is wrong!");
};
if (addr[12:8] != PCH[4:0] + 1) {
dut_error("ADDR is wrong!");
};
};
(
instructions == ASL_ZPX ||
instructions == LSR_ZPX ||
instructions == ROL_ZPX ||
instructions == ROR_ZPX ||
instructions == INC_ZPX ||
instructions == DEC_ZPX
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == ASL_ABS ||
instructions == DEC_ABS ||
instructions == INC_ABS ||
1277,6 → 1730,27
PC = PC + 1;
};
(
instructions == ASL_ZPX ||
instructions == LSR_ZPX ||
instructions == ROL_ZPX ||
instructions == ROR_ZPX ||
instructions == INC_ZPX ||
instructions == DEC_ZPX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == ASL_ABS ||
instructions == DEC_ABS ||
instructions == INC_ABS ||

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