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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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    /t6507lp
    from Rev 213 to Rev 214
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Rev 213 → Rev 214

/trunk/rtl/verilog/t2600.v
70,9 → 70,36
.data (data)
);
 
t2600_bus t2600_bus (
.address (address),
.data_from_cpu (data_from_cpu),
.cpu_rw_mem (cpu_rw_mem),
.riot_data (riot_data),
.rom_data (rom_data),
.tia_data (tia_data),
.address_riot (address_riot),
.address_rom (address_rom),
.address_tia (address_tia),
.data_to_cpu (data_to_cpu),
.enable_riot (enable_riot),
.enable_rom (enable_rom),
.enable_tia (enable_tia),
.rw_mem (rw_mem)
);
 
T2600_KB T2600_KB (
.CLK (clk),
.RST (reset_n),
.io_lines (io_lines),
.KC (kc),
.KD (kd)
);
 
 
 
 
 
// VIDEO
// BUS CONTROLLER
 
endmodule
 
/trunk/rtl/verilog/t2600_kb_tb.v
47,22 → 47,39
// all inputs are regs
reg clk;
reg reset_n;
reg kd;
reg kc;
// all outputs are wires
wire [15:0] io_lines;
 
always #10 clk <= ~clk;
initial clk = 0;
always #10 clk <= ~clk;
initial begin
clk = 1'b0;
reset_n = 1'b1;
kd = 1'b0;
kc = 1'b0;
 
always @(posedge clk) begin
//$display("reset is %b", reset_n);
//$display("alu_enable is %b", alu_enable);
//$display("alu_opcode is %h", alu_opcode);
//$display("alu_a is %d", alu_a);
#10;
reset_n = 1'b0;
#40000;
$finish;
end
t2600_kb t2600_kb (
 
always @(clk) begin
kc = $random;
kd = $random;
end
 
 
T2600_KB T2600_KB (
.CLK (clk),
.RST (reset_n),
.io_lines (alu_enable)
.io_lines (io_lines),
.KC (kc),
.KD (kd)
);
 
 
endmodule
/trunk/rtl/vhdl/t2600_kb.vhd
28,16 → 28,16
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity t2600_kb is
entity T2600_KB is
Port ( CLK, RST, KD, KC: in std_logic;
--an: out std_logic_vector (3 downto 0);
--sseg: out std_logic_vector (6 downto 0);
io_lines: out std_logic_vector (15 downto 0)
);
end t2600_kb;
end T2600_KB;
 
architecture Behavioral of t2600_kb is
------------------------------------------------------------------------
124,10 → 124,10
io_lines(8) <= '1' when WaitReg = x"1d" else '0'; -- w
io_lines(7) <= '1' when WaitReg = x"05" else '0'; -- F1, p1 dif
io_lines(6) <= '1' when WaitReg = x"06" else '0'; -- F2, p0 dif
--io_lines(5) <= '1' when WaitReg = x"72" else '0'; -- not used
--io_lines(4) <= '1' when WaitReg = x"75" else '0'; -- not used
io_lines(5) <= '0'; -- not used
io_lines(4) <= '0'; -- not used
io_lines(3) <= '1' when WaitReg = x"04" else '0'; -- F3, color
--io_lines(2) <= '1' when WaitReg = x"1c" else '0'; -- not used
io_lines(2) <= '0'; -- not used
io_lines(1) <= '1' when WaitReg = x"0c" else '0'; -- F4, game select
io_lines(0) <= '1' when WaitReg = x"03" else '0'; -- F5, game select
 
/trunk/fv/fsm_opcodes.e
6,7 → 6,7
ADC_ABS = 8'h6D,
ADC_ABX = 8'h7D,
ADC_ABY = 8'h79,
//ADC_IDX = 8'h61,
ADC_IDX = 8'h61,
//ADC_IDY = 8'h71,
AND_IMM = 8'h29,
AND_ZPG = 8'h25,
14,13 → 14,13
AND_ABS = 8'h2D,
AND_ABX = 8'h3D,
AND_ABY = 8'h39,
//AND_IDX = 8'h21,
AND_IDX = 8'h21,
//AND_IDY = 8'h31,
ASL_ACC = 8'h0A,
ASL_ZPG = 8'h06,
ASL_ZPX = 8'h16,
ASL_ABS = 8'h0E,
//ASL_ABX = 8'h1E,
ASL_ABX = 8'h1E,
//BCC_REL = 8'h90,
//BCS_REL = 8'hB0,
//BEQ_REL = 8'hF0,
42,7 → 42,7
CMP_ABS = 8'hCD,
CMP_ABX = 8'hDD,
CMP_ABY = 8'hD9,
//CMP_IDX = 8'hC1,
CMP_IDX = 8'hC1,
//CMP_IDY = 8'hD1,
CPX_IMM = 8'hE0,
//CPX_ZPG = 8'hE4,
53,7 → 53,7
DEC_ZPG = 8'hC6,
DEC_ZPX = 8'hD6,
DEC_ABS = 8'hCE,
//DEC_ABX = 8'hDE,
DEC_ABX = 8'hDE,
DEX_IMP = 8'hCA,
DEY_IMP = 8'h88,
EOR_IMM = 8'h49,
62,12 → 62,12
EOR_ABS = 8'h4D,
EOR_ABX = 8'h5D,
EOR_ABY = 8'h59,
//EOR_IDX = 8'h41,
EOR_IDX = 8'h41,
//EOR_IDY = 8'h51,
INC_ZPG = 8'hE6,
INC_ZPX = 8'hF6,
INC_ABS = 8'hEE,
//INC_ABX = 8'hFE,
INC_ABX = 8'hFE,
INX_IMP = 8'hE8,
INY_IMP = 8'hC8,
JMP_ABS = 8'h4C,
79,7 → 79,7
LDA_ABS = 8'hAD,
LDA_ABX = 8'hBD,
LDA_ABY = 8'hB9,
//LDA_IDX = 8'hA1,
LDA_IDX = 8'hA1,
//LDA_IDY = 8'hB1,
LDX_IMM = 8'hA2,
LDX_ZPG = 8'hA6,
95,7 → 95,7
LSR_ZPG = 8'h46,
LSR_ZPX = 8'h56,
LSR_ABS = 8'h4E,
//LSR_ABX = 8'h5E,
LSR_ABX = 8'h5E,
NOP_IMP = 8'hEA,
ORA_IMM = 8'h09,
ORA_ZPG = 8'h05,
103,7 → 103,7
ORA_ABS = 8'h0D,
ORA_ABX = 8'h1D,
ORA_ABY = 8'h19,
//ORA_IDX = 8'h01,
ORA_IDX = 8'h01,
//ORA_IDY = 8'h11,
PHA_IMP = 8'h48,
PHP_IMP = 8'h08,
113,12 → 113,12
ROL_ZPG = 8'h26,
ROL_ZPX = 8'h36,
ROL_ABS = 8'h2E,
//ROL_ABX = 8'h3E,
//ROR_ACC = 8'h6A,
ROL_ABX = 8'h3E,
ROR_ACC = 8'h6A,
ROR_ZPG = 8'h66,
ROR_ZPX = 8'h76,
ROR_ABS = 8'h6E,
//ROR_ABX = 8'h7E,
ROR_ABX = 8'h7E,
RTI_IMP = 8'h40,
RTS_IMP = 8'h60,
SBC_IMM = 8'hE9,
127,7 → 127,7
SBC_ABS = 8'hED,
SBC_ABX = 8'hFD,
SBC_ABY = 8'hF9,
//SBC_IDX = 8'hE1,
SBC_IDX = 8'hE1,
//SBC_IDY = 8'hF1,
SEC_IMP = 8'h38,
SED_IMP = 8'hF8,
137,7 → 137,7
STA_ABS = 8'h8D,
//STA_ABX = 8'h9D,
//STA_ABY = 8'h99,
//STA_IDX = 8'h81,
STA_IDX = 8'h81,
//STA_IDY = 8'h91,
STX_ZPG = 8'h86,
STX_ZPY = 8'h96,
/trunk/fv/fsm_chk.e
14,6 → 14,8
// keep soft SP == 9'b100000000;
!SP : byte;
keep soft SP == 0;
!pointer : byte;
keep soft pointer == 0;
 
!more_cycles : bool;
keep soft more_cycles == FALSE;
150,8 → 152,6
CYCLE_2 : {
X = input.alu_x;
Y = input.alu_y;
print X, Y;
outf("CYCLE_1\n");
case {
(
instruction == BRK_IMP ||
225,15 → 225,7
instruction == DEC_ZPX ||
instruction == STA_ZPX ||
instruction == STX_ZPY ||
instruction == STY_ZPX
) : {
new_state = CYCLE_3;
PCL = input.data_in;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
};
(
instruction == STY_ZPX ||
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == LDX_ABY ||
249,18 → 241,31
instruction == SBC_ABX ||
instruction == SBC_ABY ||
instruction == CMP_ABX ||
instruction == CMP_ABY
instruction == CMP_ABY ||
instruction == ASL_ABX ||
instruction == LSR_ABX ||
instruction == ROL_ABX ||
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX
) : {
new_state = CYCLE_3;
PCL = input.data_in;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_2\n");
};
(
instruction == LDA_IDX ||
instruction == STA_IDX ||
instruction == ORA_IDX ||
instruction == EOR_IDX ||
instruction == AND_IDX ||
instruction == ADC_IDX ||
instruction == CMP_IDX ||
instruction == SBC_IDX
) : {
new_state = CYCLE_3;
pointer = input.data_in;
};
(
instruction == TXS_IMP
) : {
new_state = CYCLE_1;
273,6 → 278,10
};
CYCLE_3 : {
case {
//JSR_ABS : {
// new_state = CYCLE_4;
// PCH = input.data_in;
//};
(
instruction == BRK_IMP ||
instruction == PLA_IMP ||
284,15 → 293,7
instruction == ROL_ZPG ||
instruction == ROR_ZPG ||
instruction == INC_ZPG ||
instruction == DEC_ZPG
) : {
new_state = CYCLE_4;
};
//JSR_ABS : {
// new_state = CYCLE_4;
// PCH = input.data_in;
//};
(
instruction == DEC_ZPG ||
instruction == LDA_ZPX ||
instruction == LDX_ZPY ||
instruction == LDY_ZPX ||
310,14 → 311,17
instruction == DEC_ZPX ||
instruction == STA_ZPX ||
instruction == STX_ZPY ||
instruction == STY_ZPX
instruction == STY_ZPX ||
instruction == LDA_IDX ||
instruction == STA_IDX ||
instruction == ORA_IDX ||
instruction == EOR_IDX ||
instruction == AND_IDX ||
instruction == ADC_IDX ||
instruction == CMP_IDX ||
instruction == SBC_IDX
) : {
new_state = CYCLE_4;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
};
(
instruction == ADC_ABS ||
354,16 → 358,16
instruction == SBC_ABX ||
instruction == SBC_ABY ||
instruction == CMP_ABX ||
instruction == CMP_ABY
instruction == CMP_ABY ||
instruction == ASL_ABX ||
instruction == LSR_ABX ||
instruction == ROL_ABX ||
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX
) : {
new_state = CYCLE_4;
PCH = input.data_in;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_3\n");
};
(
instruction == JMP_ABS
408,6 → 412,12
instruction == ROR_ZPX ||
instruction == INC_ZPX ||
instruction == DEC_ZPX ||
instruction == ASL_ABX ||
instruction == LSR_ABX ||
instruction == ROL_ABX ||
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX ||
(
more_cycles == TRUE &&
(
430,14 → 440,21
)
)
) : {
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_4\n");
new_state = CYCLE_5;
};
(
instruction == LDA_IDX ||
instruction == STA_IDX ||
instruction == ORA_IDX ||
instruction == EOR_IDX ||
instruction == AND_IDX ||
instruction == ADC_IDX ||
instruction == CMP_IDX ||
instruction == SBC_IDX
) : {
new_state = CYCLE_5;
PCL = input.data_in;
};
default : {
new_state = CYCLE_1;
};
473,62 → 490,29
instruction == ROL_ZPX ||
instruction == ROR_ZPX ||
instruction == INC_ZPX ||
instruction == DEC_ZPX
instruction == DEC_ZPX ||
instruction == ASL_ABX ||
instruction == LSR_ABX ||
instruction == ROL_ABX ||
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX
) : {
new_state = CYCLE_6;
};
(
instruction == LDA_ABX ||
instruction == LDA_ABY ||
instruction == LDX_ABY ||
instruction == LDY_ABX ||
instruction == EOR_ABX ||
instruction == EOR_ABY ||
instruction == AND_ABX ||
instruction == AND_ABY ||
instruction == ORA_ABX ||
instruction == ORA_ABY ||
instruction == ADC_ABX ||
instruction == ADC_ABY ||
instruction == SBC_ABX ||
instruction == SBC_ABY ||
instruction == CMP_ABX ||
instruction == CMP_ABY
instruction == LDA_IDX ||
instruction == STA_IDX ||
instruction == ORA_IDX ||
instruction == EOR_IDX ||
instruction == AND_IDX ||
instruction == ADC_IDX ||
instruction == CMP_IDX ||
instruction == SBC_IDX
) : {
new_state = CYCLE_1;
--X = input.alu_x;
--Y = input.alu_y;
--print X, Y;
--print input.alu_x, input.alu_y;
--print 't6507lp_fsm.index';
--outf("CYCLE_5\n");
new_state = CYCLE_6;
PCH = input.data_in;
};
--(
-- instruction == LDA_ZPX ||
-- instruction == LDX_ZPY ||
-- instruction == LDY_ZPX ||
-- instruction == EOR_ZPX ||
-- instruction == AND_ZPX ||
-- instruction == ORA_ZPX ||
-- instruction == ADC_ZPX ||
-- instruction == SBC_ZPX ||
-- instruction == CMP_ZPX ||
-- instruction == ASL_ZPX ||
-- instruction == LSR_ZPX ||
-- instruction == ROL_ZPX ||
-- instruction == ROR_ZPX ||
-- instruction == INC_ZPX ||
-- instruction == DEC_ZPX ||
-- instruction == STA_ZPX ||
-- instruction == STX_ZPY ||
-- instruction == STY_ZPX
--) : {
-- new_state = CYCLE_1;
--X = input.alu_x;
--Y = input.alu_y;
--print input.alu_x, input.alu_y;
 
--};
default : {
new_state = CYCLE_1;
};
548,6 → 532,16
new_state = CYCLE_1;
PCH = input.data_in;
};
(
instruction == ASL_ABX ||
instruction == LSR_ABX ||
instruction == ROL_ABX ||
instruction == ROR_ABX ||
instruction == INC_ABX ||
instruction == DEC_ABX
) : {
new_state = CYCLE_7;
};
default : {
new_state = CYCLE_1;
};
554,14 → 548,16
};
};
CYCLE_7 : {
//case (instruction) {
// BRK_IMP : {
// new_state = CYCLE_6;
// };
// default :
new_state = CYCLE_1;
PCH = input.data_in
case (instruction) {
BRK_IMP : {
new_state = CYCLE_1;
PCH = input.data_in;
};
default : {
new_state = CYCLE_1;
};
};
};
};
old_input = new_input;
new_input = input;
581,8 → 577,6
print addr;
last_instruction = instructions;
instructions = instruction;
//print instructions;
//print last_instruction;
if (mem_rw != 0) {
dut_error("Mem_rw is Wrong!");
};
646,10 → 640,16
last_instruction == SBC_ABX ||
last_instruction == SBC_ABY ||
last_instruction == CMP_ABX ||
last_instruction == CMP_ABY
last_instruction == CMP_ABY ||
last_instruction == LDA_IDX ||
last_instruction == ORA_IDX ||
last_instruction == EOR_IDX ||
last_instruction == AND_IDX ||
last_instruction == ADC_IDX ||
last_instruction == CMP_IDX ||
last_instruction == SBC_IDX
) : {
if (alu_opcode != last_instruction) {
--print addr[7:0],X + PCL;
dut_error("alu_opcode is Wrong!");
};
if (alu_enable != 1) {
659,11 → 659,23
dut_error("Address is Wrong!");
};
};
--(
--) : {
-- if (alu_opcode != last_instruction) {
-- dut_error("alu_opcode is Wrong!");
-- };
-- if (alu_enable != 1) {
-- dut_error("alu_enable is Wrong!");
-- };
-- if (addr[7:0] != PCL) {
-- dut_error("Address is Wrong!");
-- };
-- if (addr[12:8] != PCH[4:0]) {
-- dut_error("Address is Wrong!");
-- };
--};
default : {
if (alu_opcode.as_a(byte) != 0) {
--print alu_enable;
--print alu_opcode;
--print last_instruction;
dut_error("alu_opcode is Wrong!");
};
if (alu_enable != 0) {
784,7 → 796,21
instructions == SBC_ABX ||
instructions == SBC_ABY ||
instructions == CMP_ABX ||
instructions == CMP_ABY
instructions == CMP_ABY ||
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX ||
instructions == LDA_IDX ||
instructions == STA_IDX ||
instructions == ORA_IDX ||
instructions == EOR_IDX ||
instructions == AND_IDX ||
instructions == ADC_IDX ||
instructions == CMP_IDX ||
instructions == SBC_IDX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
842,6 → 868,7
instructions == LSR_ACC ||
instructions == PHA_IMP ||
instructions == ROL_ACC ||
instructions == ROR_ACC ||
instructions == SEC_IMP ||
instructions == SED_IMP ||
instructions == SEI_IMP ||
1019,6 → 1046,29
};
};
(
instructions == LDA_IDX ||
instructions == STA_IDX ||
instructions == ORA_IDX ||
instructions == EOR_IDX ||
instructions == AND_IDX ||
instructions == ADC_IDX ||
instructions == CMP_IDX ||
instructions == SBC_IDX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr != pointer) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == ADC_ABS ||
instructions == AND_ABS ||
instructions == ASL_ABS ||
1045,7 → 1095,13
instructions == ORA_ABX ||
instructions == ADC_ABX ||
instructions == SBC_ABX ||
instructions == CMP_ABX
instructions == CMP_ABX ||
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
1233,9 → 1289,15
dut_error("MEM_RW should be 0 (WRITE)");
};
--TODO: Isn`t it suppose to have ADDRH == 0????
if (addr != PCL + X) {
print addr[7:0], PCL+X, PCL, X, 't6507lp_fsm.index';
dut_error("ADDR should be equal SP!");
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
};
(
1246,7 → 1308,13
instructions == ORA_ABX ||
instructions == ADC_ABX ||
instructions == SBC_ABX ||
instructions == CMP_ABX
instructions == CMP_ABX ||
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
1260,7 → 1328,6
if (PCL + X > 255) {
more_cycles = TRUE;
if (addr[7:0] != PCL + X - 256) {
--print addr[7:0], PCL + X - 256;
dut_error("ADDR should be equal SP!");
};
}
1271,6 → 1338,36
};
};
(
instructions == LDA_IDX ||
instructions == STA_IDX ||
instructions == ORA_IDX ||
instructions == EOR_IDX ||
instructions == AND_IDX ||
instructions == ADC_IDX ||
instructions == CMP_IDX ||
instructions == SBC_IDX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (pointer + X > 255) {
if (addr[7:0] != pointer + X - 256) {
dut_error("ADDR is wrong");
};
}
else {
if (addr[7:0] != pointer + X) {
dut_error("ADDR is wrong");
};
};
};
(
instructions == LDX_ZPY ||
instructions == LDA_ABY ||
instructions == LDX_ABY ||
1293,9 → 1390,6
if (PCL + Y > 255) {
more_cycles = TRUE;
if (addr[7:0] != PCL + Y - 256) {
print addr[7:0], PCL + Y - 256;
print PCL, Y;
print 't6507lp_fsm.index';
dut_error("ADDR should be equal SP!");
};
}
1394,8 → 1488,15
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (addr != PCL + X) {
dut_error("ADDR should be equal SP!");
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
};
(
1410,8 → 1511,15
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (addr != PCL + Y) {
dut_error("ADDR should be equal SP!");
if (PCL + Y > 255) {
if (addr[7:0] != PCL + Y - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + Y) {
dut_error("ADDR should be equal SP!");
};
};
};
(
1444,7 → 1552,6
dut_error("RTI_IMP is Wrong!");
};
if (addr != SP + 256) {
--print addr, SP;
dut_error("ADDR should be equal SP!");
};
SP = SP + 1;
1506,6 → 1613,36
// SP = SP - 1;
//};
(
instructions == LDA_IDX ||
instructions == STA_IDX ||
instructions == ORA_IDX ||
instructions == EOR_IDX ||
instructions == AND_IDX ||
instructions == ADC_IDX ||
instructions == CMP_IDX ||
instructions == SBC_IDX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (pointer + X + 1 > 255) {
if (addr[7:0] != pointer + X + 1 - 256) {
dut_error("ADDR is wrong");
};
}
else {
if (addr[7:0] != pointer + X + 1) {
dut_error("ADDR is wrong");
};
};
};
(
instructions == RTI_IMP
) : {
if (alu_opcode != instructions) {
1566,7 → 1703,18
instructions == ORA_ABX ||
instructions == ADC_ABX ||
instructions == SBC_ABX ||
instructions == CMP_ABX
instructions == CMP_ABX ||
(
more_cycles == TRUE &&
(
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
)
)
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
1585,6 → 1733,30
};
};
(
more_cycles == FALSE &&
(
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
)
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
(
instructions == LDX_ZPY ||
instructions == LDA_ABY ||
instructions == LDX_ABY ||
1628,8 → 1800,15
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr != PCL + X) {
dut_error("ADDR should be equal SP!");
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
};
(
1696,6 → 1875,50
// PC[12:8] = PCH[4:0];
//};
(
instructions == LDA_IDX ||
instructions == ORA_IDX ||
instructions == EOR_IDX ||
instructions == AND_IDX ||
instructions == ADC_IDX ||
instructions == CMP_IDX ||
instructions == SBC_IDX
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL) {
dut_error("ADDR is wrong");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR is wrong");
};
};
(
instructions == STA_IDX ||
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL) {
dut_error("ADDR is wrong");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR is wrong");
};
};
(
instructions == RTI_IMP
) : {
if (alu_opcode.as_a(byte) != 0) {
1746,11 → 1969,72
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr != PCL + X) {
dut_error("ADDR should be equal SP!");
if (PCL + X > 255) {
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR should be equal SP!");
};
}
else {
if (addr[7:0] != PCL + X) {
dut_error("ADDR should be equal SP!");
};
};
};
(
more_cycles == TRUE &&
(
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
)
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR is wrong!");
};
if (addr[12:8] != PCH[4:0] + 1) {
dut_error("ADDR is wrong!");
};
};
(
more_cycles == FALSE &&
(
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
)
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL + X) {
dut_error("ADDR is wrong!");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR is wrong!");
};
};
(
instructions == ASL_ABS ||
instructions == DEC_ABS ||
instructions == INC_ABS ||
1781,6 → 2065,60
print addr;
case {
(
more_cycles == TRUE &&
(
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
)
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL + X - 256) {
dut_error("ADDR is wrong!");
};
if (addr[12:8] != PCH[4:0] + 1) {
dut_error("ADDR is wrong!");
};
};
(
more_cycles == FALSE &&
(
instructions == ASL_ABX ||
instructions == LSR_ABX ||
instructions == ROL_ABX ||
instructions == ROR_ABX ||
instructions == INC_ABX ||
instructions == DEC_ABX
)
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 0) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (addr[7:0] != PCL + X) {
dut_error("ADDR is wrong!");
};
if (addr[12:8] != PCH[4:0]) {
dut_error("ADDR is wrong!");
};
};
(
instructions == BRK_IMP
) : {
if (alu_opcode.as_a(byte) != 0) {

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