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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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    /t6507lp
    from Rev 226 to Rev 227
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Rev 226 → Rev 227

/trunk/rtl/verilog/vga_controller.v
44,9 → 44,9
 
`include "timescale.v"
 
module vga_controller ( reset, clk_50, line, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
module vga_controller ( reset_n, clk_50, line, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);
 
input reset;
input reset_n;
input clk_50;
input [8:0] SW;
input [479:0] line;
65,11 → 65,11
wire vidon;
 
assign LEDR[8:0] = SW;
assign LEDR[9] = reset;
assign LEDR[9] = reset_n;
 
always @ (posedge clk_50 or negedge reset)
always @ (posedge clk_50 or negedge reset_n)
begin
if (!reset) begin
if (!reset_n) begin
clk_25 <= 0;
end
else begin
77,9 → 77,9
end
end
 
always @ (posedge clk_25 or negedge reset)
always @ (posedge clk_25 or negedge reset_n)
begin
if (!reset) begin
if (!reset_n) begin
hc <= 0;
VGA_HS <= 1;
vsenable <= 0;
111,9 → 111,9
end
end
 
always @ (posedge clk_25 or negedge reset)
always @ (posedge clk_25 or negedge reset_n)
begin
if (!reset) begin
if (!reset_n) begin
vc <= 0;
VGA_VS <= 1;
end
142,141 → 142,50
 
always @ (posedge clk_25)
begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
if (vidon == 1) begin
if (hc < 40) begin
if (vert_counter < 10) begin
/*VGA_R[0] <= line[hc*12];
VGA_R[1] <= line[hc*12+1];
VGA_R[2] <= line[hc*12+2];
VGA_R[3] <= line[hc*12+3];
VGA_G[0] <= line[hc*12+4];
VGA_G[1] <= line[hc*12+5];
VGA_G[2] <= line[hc*12+6];
VGA_G[3] <= line[hc*12+7];
VGA_B[0] <= line[hc*12+8];
VGA_B[1] <= line[hc*12+9];
VGA_B[2] <= line[hc*12+10];
VGA_B[3] <= line[hc*12+11];*/
VGA_R[0] <= 1;
VGA_R[1] <= 0;
VGA_R[2] <= 1;
VGA_R[3] <= 0;
VGA_G[0] <= 1;
VGA_G[1] <= 0;
VGA_G[2] <= 1;
VGA_G[3] <= 0;
VGA_B[0] <= 1;
VGA_B[1] <= 0;
VGA_B[2] <= 1;
VGA_B[3] <= 0;
if (vc < 30) begin
if (vert_counter == 1) begin
/*VGA_R[0] <= line[hc*12];
VGA_R[1] <= line[hc*12+1];
VGA_R[2] <= line[hc*12+2];
VGA_R[3] <= line[hc*12+3];
VGA_G[0] <= line[hc*12+4];
VGA_G[1] <= line[hc*12+5];
VGA_G[2] <= line[hc*12+6];
VGA_G[3] <= line[hc*12+7];
VGA_B[0] <= line[hc*12+8];
VGA_B[1] <= line[hc*12+9];
VGA_B[2] <= line[hc*12+10];
VGA_B[3] <= line[hc*12+11];*/
VGA_R[0] <= 1;
VGA_R[1] <= 0;
VGA_R[2] <= 1;
VGA_R[3] <= 0;
VGA_G[0] <= 1;
VGA_G[1] <= 0;
VGA_G[2] <= 1;
VGA_G[3] <= 0;
VGA_B[0] <= 1;
VGA_B[1] <= 0;
VGA_B[2] <= 1;
VGA_B[3] <= 0;
end
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
/* if (vc < 240) begin
VGA_R[0] <= 1;
VGA_G[0] <= 1;
VGA_B[0] <= 1;
VGA_R[1] <= 1;
VGA_G[1] <= 1;
VGA_B[1] <= 1;
VGA_R[2] <= 1;
VGA_G[2] <= 1;
VGA_B[2] <= 1;
VGA_R[3] <= 1;
VGA_G[3] <= 1;
VGA_B[3] <= 1;
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 1;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 1;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 1;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 1;
end
end
else begin
if (vc < 240) begin
VGA_R[0] <= 1;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 1;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 1;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 1;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 1;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 1;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 1;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 1;
VGA_B[3] <= 0;
end
end
end
*/
end
else begin
VGA_R[0] <= 0;
VGA_G[0] <= 0;
VGA_B[0] <= 0;
VGA_R[1] <= 0;
VGA_G[1] <= 0;
VGA_B[1] <= 0;
VGA_R[2] <= 0;
VGA_G[2] <= 0;
VGA_B[2] <= 0;
VGA_R[3] <= 0;
VGA_G[3] <= 0;
VGA_B[3] <= 0;
end
end
 
assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
/trunk/rtl/verilog/controller_test.v
44,18 → 44,13
 
`include "timescale.v"
 
//module vga_tester (reset_n, clk_50);
module controller_test(reset, clk_50, line, vert_counter);
module controller_test(reset_n, clk_50, line, vert_counter);
 
input reset;
input reset_n;
input clk_50;
 
output reg [479:0] line;
output reg [4:0] vert_counter;
 
//reg reset_n;
//reg clk_50;
 
reg clk_358; // 3.58mhz
reg [3:0] counter;
 
73,18 → 68,10
reg [11:0] pixel7;
reg [11:0] pixel8;
reg [11:0] pixel9;
 
//always #10 clk_50 <= !clk_50;
 
//initial begin
//reset_n = 1'b0;
//clk_50 = 1'b0;
//#20;
//reset_n = 1'b1;
//end
 
always @ (posedge clk_50 or negedge reset) begin
if (reset == 0) begin
always @ (posedge clk_50 or negedge reset_n) begin
if (reset_n == 1'b0) begin
clk_358 <= 1'b0;
counter <= 4'd0;
red <= 4'b1010;
97,20 → 84,18
counter <= 4'd0;
end
else begin
counter <= counter + 4'd1;
counter <= counter + 4'd1;
end
end
red <= 4'b1010;
green <= 4'b0001;
blue <= 4'b1110;
end
end
 
 
 
always @ (posedge clk_358 or negedge reset) begin
if (reset == 0) begin
vert_counter <= 5'd0;
always @ (posedge clk_358 or negedge reset_n) begin
if (reset_n == 1'b0) begin
vert_counter <= 6'd0;
line <= 480'd0;
$write("NEVER!");
end
else begin
120,13 → 105,13
pixel0, pixel1, pixel2, pixel3, pixel4, pixel5, pixel6, pixel7, pixel8, pixel9};
 
if (vert_counter == 5'd29) begin
vert_counter <= 5'd0;
vert_counter <= 6'd0;
end
else begin
vert_counter <= vert_counter + 5'd1;
end
end
end
end
 
always @(*) begin
pixel0 = {red, green, blue};

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