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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /t6507lp
    from Rev 240 to Rev 241
    ↔ Reverse comparison
  •

Rev 240 → Rev 241

/trunk/fv/alu_opcodes.e
22,7 → 22,7
STY_ABS = 8'h8C, TAX_IMP = 8'hAA, TAY_IMP = 8'hA8, TSX_IMP = 8'hBA, TXA_IMP = 8'h8A, TXS_IMP = 8'h9A, TYA_IMP = 8'h98 ];
'>
 
JMP_IND = 8'h6C REMOVED FROM TEST SINCE THESE DO NOT GO TO THE ALU
JMP_IND = 8'h6C REMOVED FROM TEST SINCE THESE DO NOT GO TO THE ALU. these are kept here cause they might be reused in another test
JMP_ABS = 8'h4C
PHP_IMP = 8'h08
BCC_REL = 8'h90,
/trunk/fv/fsm_opcodes.e
72,7 → 72,7
INY_IMP = 8'hC8,
JMP_ABS = 8'h4C,
JMP_IND = 8'h6C,
//JSR_ABS = 8'h20,
JSR_ABS = 8'h20,
LDA_IMM = 8'hA9,
LDA_ZPG = 8'hA5,
LDA_ZPX = 8'hB5,
/trunk/fv/fsm_chk.e
166,10 → 166,10
) : {
new_state = CYCLE_3;
};
//JSR_ABS : {
// new_state = CYCLE_3;
// PCL = input.data_in;
//};
instruction == JSR_ABS : {
new_state = CYCLE_3;
PCL = input.data_in;
};
(
instruction == ADC_ABS ||
instruction == ASL_ABS ||
295,10 → 295,10
};
CYCLE_3 : {
case {
//JSR_ABS : {
// new_state = CYCLE_4;
// PCH = input.data_in;
//};
instruction == JSR_ABS : {
new_state = CYCLE_4;
//PCH = input.data_in;
};
(
instruction == BRK_IMP ||
instruction == PLA_IMP ||
422,9 → 422,9
};
CYCLE_4 : {
case {
//JSR_ABS : {
// new_state = CYCLE_5;
//};
instruction == JSR_ABS : {
new_state = CYCLE_5;
};
(
instruction == RTS_IMP ||
instruction == JMP_IND
518,9 → 518,9
};
CYCLE_5 : {
case {
//JSR_ABS : {
// new_state = CYCLE_6;
//};
instruction == JSR_ABS : {
new_state = CYCLE_6;
};
(
instruction == RTI_IMP
) : {
602,12 → 602,18
PCL = input.data_in;
};
(
instructions == RTI_IMP
instruction == RTI_IMP
) : {
new_state = CYCLE_1;
PCH = input.data_in;
};
(
instruction == JSR_ABS
) : {
new_state = CYCLE_1;
PCH = input.data_in;
};
(
instruction == ASL_ABX ||
instruction == LSR_ABX ||
instruction == ROL_ABX ||
911,7 → 917,8
instructions == ADC_IDY ||
instructions == CMP_IDY ||
instructions == SBC_IDY ||
instructions == JMP_IND
instructions == JMP_IND ||
instructions == JSR_ABS
) : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
1050,20 → 1057,20
};
SP = SP - 1;
};
//JSR_ABS : {
// if (alu_opcode.as_a(byte) != 0) {
// dut_error("Opcode is Wrong!");
// };
// if (mem_rw != 0) {
// dut_error("MEM_RW should be 1 (WRITE)");
// };
// if (alu_enable != 0) {
// dut_error("JSR_IMP is Wrong!");
// };
// if (addr != PC) {
// dut_error("ADDR should be equal PC!");
// };
//};
instructions == JSR_ABS : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (alu_enable != 0) {
dut_error("JSR_IMP is Wrong!");
};
if (addr != SP + 256) {
dut_error("ADDR should be equal PC!");
};
};
-- TODO: This is probably an error STA should not use ALU on the third cycle
(
instructions == STA_ZPX ||
1377,24 → 1384,24
};
SP = SP - 1;
};
//JSR_ABS : {
// if (alu_opcode.as_a(byte) != 0) {
// dut_error("Opcode is Wrong!");
// };
// if (mem_rw != 1) {
// dut_error("MEM_RW should be 1 (WRITE)");
// };
// if (alu_enable != 0) {
// dut_error("JSR_ABS is Wrong!");
// };
// if (data_out != PC[7:0]) {
// dut_error("JSR_ABS is Wrong!");
// };
// if (addr != SP + 256) {
// dut_error("ADDR should be equal SP!");
// };
// SP = SP - 1;
//};
instructions == JSR_ABS : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (alu_enable != 0) {
dut_error("JSR_ABS is Wrong!");
};
if (data_out[4:0] != PC[12:8]) {
dut_error("JSR_ABS is Wrong!");
};
if (addr != SP + 256) {
dut_error("ADDR should be equal SP!");
};
SP = SP - 1;
};
(
instructions == STA_ABX
) : {
1856,24 → 1863,24
PC[7:0] = PCL;
PC[12:8] = PCH[4:0];
};
//JSR_ABS : {
// if (alu_opcode.as_a(byte) != 0) {
// dut_error("Opcode is Wrong!");
// };
// if (mem_rw != 1) {
// dut_error("MEM_RW should be 1 (WRITE)");
// };
// if (alu_enable != 0) {
// dut_error("JSR_ABS is Wrong!");
// };
// if (data_out != PC[12:8]) {
// dut_error("JSR_ABS is Wrong!");
// };
// if (addr != SP + 256) {
// dut_error("ADDR should be equal SP!");
// };
// SP = SP - 1;
//};
instructions == JSR_ABS : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (mem_rw != 1) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (alu_enable != 0) {
dut_error("JSR_ABS is Wrong!");
};
if (data_out != PC[7:0]) {
dut_error("JSR_ABS is Wrong!");
};
if (addr != SP + 256) {
dut_error("ADDR should be equal SP!");
};
SP = SP - 1;
};
(
instructions == LDA_IDX ||
instructions == ORA_IDX ||
1909,7 → 1916,7
};
(
instructions == LDA_IDY ||
instructions == STA_IDY ||
//instructions == STA_IDY ||
instructions == ORA_IDY ||
instructions == EOR_IDY ||
instructions == AND_IDY ||
1967,6 → 1974,30
};
};
(
instructions == STA_IDY
) : {
if (alu_opcode != instructions) {
dut_error("Opcode is Wrong!");
};
if (alu_enable != 1) {
dut_error("ASL_ACC is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 0 (WRITE)");
};
if (pointer + Y > 255) {
if (addr[7:0] != pointer + Y - 256) {
dut_error("ADDR is wrong");
};
}
else {
if (addr[7:0] != pointer + Y) {
dut_error("ADDR is wrong");
};
};
};
 
(
instructions == STA_ABX
) : {
if (alu_opcode.as_a(byte) != 0) {
2240,22 → 2271,22
};
PC[7:0] = PCL;
};
//JSR_ABS : {
// if (alu_opcode.as_a(byte) != 0) {
// dut_error("Opcode is Wrong!");
// };
// if (mem_rw != 0) {
// dut_error("MEM_RW should be 1 (WRITE)");
// };
// if (alu_enable != 0) {
// dut_error("JSR_ABS is Wrong!");
// };
// if (addr != PC) {
// dut_error("ADDR should be equal SP!");
// };
// PC [7:0] = PCL;
// PC[12:8] = PCH[4:0];
//};
instructions == JSR_ABS : {
if (alu_opcode.as_a(byte) != 0) {
dut_error("Opcode is Wrong!");
};
if (mem_rw != 0) {
dut_error("MEM_RW should be 1 (WRITE)");
};
if (alu_enable != 0) {
dut_error("JSR_ABS is Wrong!");
};
if (addr != PC) {
dut_error("ADDR should be equal SP!");
};
PC [7:0] = PCL;
PC[12:8] = PCH[4:0];
};
(
instructions == LDA_IDX ||
instructions == ORA_IDX ||

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