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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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  • This comparison shows the changes necessary to convert path 
    /t6507lp
    from Rev 252 to Rev 253
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Rev 252 → Rev 253

/trunk/rtl/verilog/t6507lp_fsm.v
46,7 → 46,7
 
`include "timescale.v"
 
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, alu_x, alu_y, address, mem_rw, data_out, alu_opcode, alu_a, alu_enable);
module t6507lp_fsm(clk, reset_n, alu_result, alu_status, data_in, alu_x, alu_y, address, rw_mem, data_out, alu_opcode, alu_a, alu_enable);
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
 
61,7 → 61,7
input [DATA_SIZE_:0] alu_x; // alu x index register
input [DATA_SIZE_:0] alu_y; // alu y index register
output reg [ADDR_SIZE_:0] address; // system bus address
output reg mem_rw; // read = 0, write = 1
output reg rw_mem; // read = 0, write = 1
output reg [DATA_SIZE_:0] data_out; // data that will be written somewhere else
output reg [DATA_SIZE_:0] alu_opcode; // current opcode
output reg [DATA_SIZE_:0] alu_a; // extra operand sent to the alu
103,7 → 103,7
// OPCODES TODO: verify how this get synthesised
`include "t6507lp_package.v"
 
// mem_rw signals
// rw_mem signals
localparam MEM_READ = 1'b0;
localparam MEM_WRITE = 1'b1;
 
228,7 → 228,7
state <= RESET;
// registered outputs also receive default values
address <= 13'h0000;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
rst_counter <= 3'h0;
index <= 8'h00;
249,7 → 249,7
FETCH_OP, FETCH_OP_CALC_PARAM: begin // this is the pipeline happening!
pc <= next_pc;
address <= next_pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
ir <= data_in;
end
/*
272,7 → 272,7
if (accumulator || implied || txs || tsx) begin
pc <= pc; // is this better?
address <= pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
if (txs) begin
sp[7:0] <= alu_x;
282,13 → 282,13
else if (immediate || relative) begin
pc <= next_pc;
address <= next_pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
temp_data <= data_in; // the follow-up byte is saved in temp_data
end
else if (absolute || absolute_indexed || jump_indirect) begin
pc <= next_pc;
address <= next_pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
temp_addr <= {{5{1'b0}},data_in};
temp_data <= 8'h00;
end
298,11 → 298,11
temp_addr <= {{5{1'b0}},data_in};
 
if (write) begin
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
end
310,13 → 310,13
pc <= next_pc;
address <= {{5{1'b0}}, data_in};
temp_addr <= {{5{1'b0}}, data_in};
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
else if (indirectx || indirecty) begin
pc <= next_pc;
address <= data_in;
temp_data <= data_in;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
else begin // the special instructions will fall here: BRK, RTI, RTS...
if (brk) begin
323,30 → 323,30
pc <= next_pc;
address <= sp;
data_out <= {{3{1'b0}}, pc[12:8]};
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
end
else if (rti || rts) begin
address <= sp;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
else if (pha || php) begin
pc <= pc;
address <= sp;
data_out <= (pha) ? alu_result : alu_status;
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
end
else if (pla || plp) begin
pc <= pc;
address <= sp;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
else if (invalid) begin
address <= pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
else begin // jsr
address <= sp;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
temp_addr <= {{5{1'b0}}, data_in};
pc <= next_pc;
end
356,7 → 356,7
pc <= next_pc;
temp_addr[12:8] <= data_in[4:0];
address <= {data_in[4:0], address_plus_index[7:0]};
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
// this cycle fetchs the next operand while still evaluating if a branch occurred.
364,13 → 364,13
if (branch) begin
pc <= {{5{1'b0}}, address_plus_index[7:0]};
address <= {{5{1'b0}}, address_plus_index[7:0]};
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
else begin
pc <= next_pc;
address <= next_pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
ir <= data_in;
end
384,7 → 384,7
else begin
pc <= next_pc;
address <= next_pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
ir <= data_in;
end
end
393,7 → 393,7
if (jump) begin
pc <= {data_in[4:0], temp_addr[7:0]}; // PCL <= first byte, PCH <= second byte
address <= {data_in[4:0], temp_addr[7:0]};
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
else begin
401,7 → 401,7
pc <= next_pc;
temp_addr[12:8] <= data_in[4:0];
address <= {data_in[4:0],temp_addr[7:0]};
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin // read_modify_write or just read
408,7 → 408,7
pc <= next_pc;
temp_addr[12:8] <= data_in[4:0];
address <= {data_in[4:0],temp_addr[7:0]};
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
end
418,7 → 418,7
if (read_modify_write) begin
pc <= pc;
address <= temp_addr;
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
temp_data <= data_in;
data_out <= data_in; // writeback the same value
end
426,7 → 426,7
pc <= pc;
address <= pc;
temp_data <= data_in;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
end
435,11 → 435,11
temp_addr <= address_plus_index;
 
if (write) begin
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
 
446,7 → 446,7
end
READ_MEM_FIX_ADDR: begin
if (read) begin
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
 
if (page_crossed) begin // fix address
459,7 → 459,7
end
end
else if (write) begin
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
data_out <= alu_result;
address <= address_plus_index;
temp_addr <= address_plus_index;
466,7 → 466,7
 
end
else begin // read modify write
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
address <= address_plus_index;
temp_addr <= address_plus_index;
476,24 → 476,24
DUMMY_WRT_CALC: begin
pc <= pc;
address <= temp_addr;
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
WRITE_MEM: begin
pc <= pc;
address <= pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
data_out <= 8'h00;
end
READ_FROM_POINTER: begin
if (jump_indirect) begin
pc[7:0] <= data_in;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
address <= address_plus_index;
end
else begin
pc <= pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
if (indirectx) begin
address <= address_plus_index;
508,28 → 508,28
pc <= pc;
address <= address_plus_index;
temp_addr[7:0] <= data_in;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
READ_FROM_POINTER_X1: begin
if (jump_indirect) begin
pc[12:8] <= data_in[4:0];
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
address <= {data_in[4:0], pc[7:0]};
end
else if (indirectx) begin
address <= {data_in[4:0], temp_addr[7:0]};
if (write) begin
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
data_out <= alu_result;
end
else begin
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
end
else begin // indirecty falls here
address <= address_plus_index;
temp_addr[12:8] <= data_in;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
end
PUSH_PCH: begin // this is probably wrong
536,7 → 536,7
pc <= pc;
address <= sp_minus_one;
data_out <= pc[7:0];
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
sp <= sp_minus_one;
end
PUSH_PCL: begin
543,7 → 543,7
if (jsr) begin
pc <= pc;
address <= pc;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
sp <= sp_minus_one;
end
else begin
550,24 → 550,24
pc <= pc;
address <= sp_minus_one;
data_out <= alu_status;
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
sp <= sp_minus_one;
end
end
PUSH_STATUS: begin
address <= 13'h1FFE;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
sp <= sp_minus_one;
end
FETCH_PCL: begin
pc[7:0] <= data_in;
address <= 13'h1FFF;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
FETCH_PCH: begin
pc[12:8] <= data_in[4:0];
address <= {data_in[4:0], pc[7:0]};
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
end
INCREMENT_SP: begin
sp <= sp_plus_one;
595,7 → 595,7
pc <= pc;
address <= pc;
sp <= sp_minus_one;
mem_rw <= MEM_READ;
rw_mem <= MEM_READ;
temp_data <= data_in;
end
PULL_REGISTER: begin
605,7 → 605,7
end
DUMMY: begin
address <= sp;
mem_rw <= MEM_WRITE;
rw_mem <= MEM_WRITE;
end
default: begin
//$write("unknown state"); // TODO: check if synth really ignores this 2 lines. Otherwise wrap it with a `ifdef

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