OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /t6507lp
    from Rev 258 to Rev 259
    ↔ Reverse comparison
  •

Rev 258 → Rev 259

/trunk/syn/cadence/results/floorplan/t6507lp_io.fp.spr
1,6 → 1,6
Version 2.2
Micron 1000
13
16
VIA_C null M2 0 1 0 700 700 0 0 1 1 -350 -350 350 350
1
-750 -750 750 750
21,26 → 21,56
-10000 -4000 10000 4000
1
-10000 -4000 10000 4000
VIAGEN12W_9 VIAGEN12W M2 0 1 0 700 700 1400 1400 9 13 -5950 -8750 5950 8750
VIAGEN12W_8 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 13 -8750 -8750 8750 8750
1
-10000 -10300 10000 10300
1
-10000 -10300 10000 10300
VIAGEN12W_9 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 21 -8750 -14350 8750 14350
1
-10000 -16000 10000 16000
1
-10000 -16000 10000 16000
VIAGEN12W_10 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 9 -8750 -5950 8750 5950
1
-10000 -7000 10000 7000
1
-10000 -7000 10000 7000
VIAGEN12W_11 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 10 -8750 -6650 8750 6650
1
-10000 -8300 10000 8300
1
-10000 -8300 10000 8300
VIAGEN12W_12 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 12 -8750 -8050 8750 8050
1
-10000 -9500 10000 9500
1
-10000 -9500 10000 9500
VIAGEN12W_13 VIAGEN12W M2 0 1 0 700 700 1400 1400 9 13 -5950 -8750 5950 8750
1
-7000 -10000 7000 10000
1
-7000 -10000 7000 10000
VIAGEN12W_10 VIAGEN12W M2 0 1 0 700 700 1400 1400 8 9 -5250 -5950 5250 5950
VIAGEN12W_14 VIAGEN12W M2 0 1 0 700 700 1400 1400 9 1 -5950 -350 5950 350
1
-6500 -7000 6500 7000
-7000 -1400 7000 1400
1
-6500 -7000 6500 7000
VIAGEN12W_12 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 9 -8750 -5950 8750 5950
-7000 -1400 7000 1400
VIAGEN12W_15 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 1 -8750 -350 8750 350
1
-10000 -7000 10000 7000
-10000 -2000 10000 2000
1
-10000 -7000 10000 7000
-10000 -2000 10000 2000
VIAGEN32W_1 VIAGEN32W M3 0 1 0 700 700 1400 1400 13 4 -8750 -2450 8750 2450
1
-10000 -4000 10000 4000
1
-10000 -4000 10000 4000
VIAGEN12W_16 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 10 -8750 -6650 8750 6650
1
-10000 -7700 10000 7700
1
-10000 -7700 10000 7700
VIAGEN12_2 VIAGEN12 M2 0 1 0 700 700 1400 1400 5 5 -3150 -3150 3150 3150
1
-4000 -4000 4000 4000
51,378 → 81,354
-4000 -4000 4000 4000
1
-4000 -4000 4000 4000
VIAGEN12W_15 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 10 -8750 -6650 8750 6650
1
-10000 -7900 10000 7900
1
-10000 -7900 10000 7900
VIAGEN12W_16 VIAGEN12W M2 0 1 0 700 700 1400 1400 9 1 -5950 -350 5950 350
1
-7000 -1400 7000 1400
1
-7000 -1400 7000 1400
VIAGEN12W_17 VIAGEN12W M2 0 1 0 700 700 1400 1400 13 1 -8750 -350 8750 350
1
-10000 -2000 10000 2000
1
-10000 -2000 10000 2000
0 0 1 dummy_gnd
102 67 1 gnd!
458700 533600 22000 8000 M1 100 5 0
458700 495200 22000 8000 M1 100 5 0
458700 610400 22000 8000 M1 100 5 0
458700 572000 22000 8000 M1 100 5 0
458700 687200 22000 8000 M1 100 5 0
458700 648800 22000 8000 M1 100 5 0
458700 725600 22000 8000 M1 100 5 0
458700 764000 22000 8000 M1 100 5 0
458700 802400 22000 8000 M1 100 5 0
458700 840800 22000 8000 M1 100 5 0
428400 891000 50300 14000 M1 100 4 0
458700 879200 22000 8000 M1 100 5 0
428400 909000 50300 14000 M1 100 4 0
428400 927000 50300 14000 M1 100 4 0
428400 945000 50300 14000 M1 100 4 0
458700 956000 22000 8000 M1 100 5 0
458700 917600 22000 8000 M1 100 5 0
458700 458000 1152600 20000 M1 100 1 0
480700 572000 1108600 8000 M1 100 3 0
480700 610400 1108600 8000 M1 100 3 0
480700 648800 1108600 8000 M1 100 3 0
480700 687200 1108600 8000 M1 100 3 0
480700 495200 1108600 8000 M1 100 3 0
480700 533600 1108600 8000 M1 100 3 0
480700 840800 1108600 8000 M1 100 3 0
480700 879200 1108600 8000 M1 100 3 0
480700 917600 1108600 8000 M1 100 3 0
480700 956000 1108600 8000 M1 100 3 0
480700 725600 1108600 8000 M1 100 3 0
480700 764000 1108600 8000 M1 100 3 0
480700 802400 1108600 8000 M1 100 3 0
1589300 495200 22000 8000 M1 100 5 0
1589300 533600 22000 8000 M1 100 5 0
1589300 572000 22000 8000 M1 100 5 0
1589300 610400 22000 8000 M1 100 5 0
1589300 648800 22000 8000 M1 100 5 0
1589300 687200 22000 8000 M1 100 5 0
1589300 725600 22000 8000 M1 100 5 0
1589300 764000 22000 8000 M1 100 5 0
1589300 802400 22000 8000 M1 100 5 0
1589300 840800 22000 8000 M1 100 5 0
1589300 879200 22000 8000 M1 100 5 0
1589300 956000 22000 8000 M1 100 5 0
1589300 917600 22000 8000 M1 100 5 0
458700 458000 20000 1042400 M2 010 1 0
1591300 458000 20000 1042400 M2 010 1 0
458700 1071200 22000 8000 M1 100 5 0
458700 1032800 22000 8000 M1 100 5 0
458700 994400 22000 8000 M1 100 5 0
458700 1109600 22000 8000 M1 100 5 0
458700 1186400 22000 8000 M1 100 5 0
458700 1148000 22000 8000 M1 100 5 0
458700 1224800 22000 8000 M1 100 5 0
458700 1301600 22000 8000 M1 100 5 0
458700 1263200 22000 8000 M1 100 5 0
458700 1340000 22000 8000 M1 100 5 0
458700 1378400 22000 8000 M1 100 5 0
458700 1416800 22000 8000 M1 100 5 0
458700 1455200 22000 8000 M1 100 5 0
1001000 1480400 14000 46000 M2 010 4 0
1019000 1480400 14000 46000 M2 010 4 0
1019000 1526400 14000 5200 M1 010 4 0
1019000 1525000 14000 2800 M1 100 4 0
1001000 1526400 14000 5200 M1 010 4 0
1001000 1525000 14000 2800 M1 100 4 0
480700 1109600 1108600 8000 M1 100 3 0
480700 1148000 1108600 8000 M1 100 3 0
480700 1186400 1108600 8000 M1 100 3 0
480700 1224800 1108600 8000 M1 100 3 0
480700 994400 1108600 8000 M1 100 3 0
480700 1032800 1108600 8000 M1 100 3 0
480700 1071200 1108600 8000 M1 100 3 0
480700 1416800 1108600 8000 M1 100 3 0
480700 1455200 1108600 8000 M1 100 3 0
480700 1378400 1108600 8000 M1 100 3 0
480700 1263200 1108600 8000 M1 100 3 0
480700 1301600 1108600 8000 M1 100 3 0
480700 1340000 1108600 8000 M1 100 3 0
458700 1480400 1152600 20000 M1 100 1 0
1591300 1019000 50300 14000 M1 100 4 0
1591300 1001000 50300 14000 M1 100 4 0
1591300 1037000 50300 14000 M1 100 4 0
1589300 994400 22000 8000 M1 100 5 0
1589300 1032800 22000 8000 M1 100 5 0
1591300 1055000 50300 14000 M1 100 4 0
1589300 1071200 22000 8000 M1 100 5 0
1589300 1109600 22000 8000 M1 100 5 0
1589300 1148000 22000 8000 M1 100 5 0
1589300 1186400 22000 8000 M1 100 5 0
1589300 1224800 22000 8000 M1 100 5 0
1589300 1301600 22000 8000 M1 100 5 0
1589300 1263200 22000 8000 M1 100 5 0
1589300 1340000 22000 8000 M1 100 5 0
1589300 1378400 22000 8000 M1 100 5 0
1589300 1455200 22000 8000 M1 100 5 0
1589300 1416800 22000 8000 M1 100 5 0
1055000 1480400 14000 46000 M2 010 4 0
1037000 1480400 14000 46000 M2 010 4 0
1037000 1526400 14000 5200 M1 010 4 0
1037000 1525000 14000 2800 M1 100 4 0
1055000 1526400 14000 5200 M1 010 4 0
1055000 1525000 14000 2800 M1 100 4 0
458700 458000 2 0 1 0
458700 533600 3 0 5 0
458700 495200 3 0 5 0
458700 610400 3 0 5 0
458700 572000 3 0 5 0
458700 687200 3 0 5 0
458700 648800 3 0 5 0
458700 725600 3 0 5 0
458700 764000 3 0 5 0
458700 802400 3 0 5 0
458700 840800 3 0 5 0
458700 891000 6 0 4 0
458700 879200 3 0 5 0
458700 909000 7 0 4 0
458700 945000 8 0 4 0
458700 927000 6 0 4 0
1591300 458000 2 0 1 0
1591300 533600 3 0 5 0
1591300 495200 3 0 5 0
1591300 572000 3 0 5 0
1591300 610400 3 0 5 0
1591300 687200 3 0 5 0
1591300 648800 3 0 5 0
1591300 725600 3 0 5 0
1591300 764000 3 0 5 0
1591300 802400 3 0 5 0
1591300 840800 3 0 5 0
1591300 879200 3 0 5 0
1591300 956000 3 0 5 0
1591300 917600 3 0 5 0
458700 1071200 3 0 5 0
458700 1032800 3 0 5 0
458700 994400 3 0 5 0
458700 1109600 3 0 5 0
458700 1186400 3 0 5 0
458700 1148000 3 0 5 0
458700 1224800 3 0 5 0
458700 1301600 3 0 5 0
458700 1263200 3 0 5 0
458700 1340000 3 0 5 0
458700 1378400 3 0 5 0
458700 1455200 3 0 5 0
458700 1416800 3 0 5 0
458700 1480400 2 0 1 0
1019000 1480400 9 0 4 0
1001000 1480400 9 0 4 0
1019000 1525000 10 0 4 0
1001000 1525000 10 0 4 0
1591300 1019000 5 0 4 0
1591300 994400 4 0 4 0
1591300 1055000 6 0 4 0
1591300 1071200 3 0 5 0
1591300 1109600 3 0 5 0
1591300 1148000 3 0 5 0
1591300 1186400 3 0 5 0
1591300 1224800 3 0 5 0
1591300 1301600 3 0 5 0
1591300 1263200 3 0 5 0
1591300 1340000 3 0 5 0
1591300 1378400 3 0 5 0
1591300 1455200 3 0 5 0
1591300 1416800 3 0 5 0
1055000 1480400 9 0 4 0
1037000 1480400 9 0 4 0
1037000 1525000 10 0 4 0
1055000 1525000 10 0 4 0
1591300 1480400 2 0 1 0
0 0 1 dummy_clampc
0 0 1 dummy_vdd
107 74 1 gnd!
1019000 434400 14000 47600 M2 010 4 0
1001000 434400 14000 47600 M2 010 4 0
1019000 428400 14000 6000 M1 010 4 0
1019000 433000 14000 2800 M1 100 4 0
1001000 428400 14000 6000 M1 010 4 0
1001000 433000 14000 2800 M1 100 4 0
462100 507200 30100 8000 M1 100 5 0
462100 545600 30100 8000 M1 100 5 0
462100 584000 30100 8000 M1 100 5 0
462100 622400 30100 8000 M1 100 5 0
462100 660800 30100 8000 M1 100 5 0
462100 699200 30100 8000 M1 100 5 0
462100 737600 30100 8000 M1 100 5 0
462100 776000 30100 8000 M1 100 5 0
462100 814400 30100 8000 M1 100 5 0
462100 852800 30100 8000 M1 100 5 0
462100 891200 30100 8000 M1 100 5 0
462100 929600 30100 8000 M1 100 5 0
462100 968000 30100 8000 M1 100 5 0
462100 462000 1145800 20000 M1 100 1 0
492200 545600 1085600 8000 M1 100 3 0
492200 507200 1085600 8000 M1 100 3 0
492200 660800 1085600 8000 M1 100 3 0
492200 622400 1085600 8000 M1 100 3 0
492200 584000 1085600 8000 M1 100 3 0
492200 699200 1085600 8000 M1 100 3 0
492200 814400 1085600 8000 M1 100 3 0
492200 776000 1085600 8000 M1 100 3 0
492200 737600 1085600 8000 M1 100 3 0
492200 929600 1085600 8000 M1 100 3 0
492200 891200 1085600 8000 M1 100 3 0
492200 852800 1085600 8000 M1 100 3 0
492200 968000 1085600 8000 M1 100 3 0
1055000 434400 14000 47600 M2 010 4 0
1055000 428400 14000 6000 M1 010 4 0
1055000 433000 14000 2800 M1 100 4 0
1037000 434400 14000 47600 M2 010 4 0
1037000 428400 14000 6000 M1 010 4 0
1037000 433000 14000 2800 M1 100 4 0
1577800 507200 30100 8000 M1 100 5 0
1577800 545600 30100 8000 M1 100 5 0
1577800 584000 30100 8000 M1 100 5 0
1577800 622400 30100 8000 M1 100 5 0
1577800 660800 30100 8000 M1 100 5 0
1577800 699200 30100 8000 M1 100 5 0
1577800 737600 30100 8000 M1 100 5 0
1577800 776000 30100 8000 M1 100 5 0
1577800 814400 30100 8000 M1 100 5 0
1577800 852800 30100 8000 M1 100 5 0
1577800 891200 30100 8000 M1 100 5 0
1577800 929600 30100 8000 M1 100 5 0
1577800 968000 30100 8000 M1 100 5 0
462100 462000 20000 1028000 M2 010 1 0
1587900 462000 20000 1028000 M2 010 1 0
428400 1019000 53700 14000 M1 100 4 0
462100 1006400 30100 8000 M1 100 5 0
428400 1001000 53700 14000 M1 100 4 0
428400 1037000 53700 14000 M1 100 4 0
462100 1044800 30100 8000 M1 100 5 0
462100 1083200 30100 8000 M1 100 5 0
428400 1055000 53700 14000 M1 100 4 0
462100 1121600 30100 8000 M1 100 5 0
462100 1198400 30100 8000 M1 100 5 0
462100 1160000 30100 8000 M1 100 5 0
462100 1236800 30100 8000 M1 100 5 0
462100 1275200 30100 8000 M1 100 5 0
462100 1313600 30100 8000 M1 100 5 0
462100 1352000 30100 8000 M1 100 5 0
462100 1390400 30100 8000 M1 100 5 0
462100 1428800 30100 8000 M1 100 5 0
1001000 1470000 14000 54900 M2 010 4 0
1019000 1470000 14000 54900 M2 010 4 0
1001000 1524900 14000 6700 M1 010 4 0
1019000 1524900 14000 6700 M1 010 4 0
492200 1006400 1085600 8000 M1 100 3 0
492200 1083200 1085600 8000 M1 100 3 0
492200 1044800 1085600 8000 M1 100 3 0
492200 1121600 1085600 8000 M1 100 3 0
492200 1198400 1085600 8000 M1 100 3 0
492200 1160000 1085600 8000 M1 100 3 0
492200 1236800 1085600 8000 M1 100 3 0
492200 1428800 1085600 8000 M1 100 3 0
492200 1390400 1085600 8000 M1 100 3 0
492200 1313600 1085600 8000 M1 100 3 0
492200 1275200 1085600 8000 M1 100 3 0
492200 1352000 1085600 8000 M1 100 3 0
462100 1470000 1145800 20000 M1 100 1 0
1587900 1019000 53700 14000 M1 100 4 0
1587900 1001000 53700 14000 M1 100 4 0
1577800 1006400 30100 8000 M1 100 5 0
1587900 1037000 53700 14000 M1 100 4 0
1577800 1044800 30100 8000 M1 100 5 0
1577800 1083200 30100 8000 M1 100 5 0
1587900 1055000 53700 14000 M1 100 4 0
1577800 1121600 30100 8000 M1 100 5 0
1577800 1160000 30100 8000 M1 100 5 0
1577800 1198400 30100 8000 M1 100 5 0
1577800 1236800 30100 8000 M1 100 5 0
1577800 1275200 30100 8000 M1 100 5 0
1577800 1313600 30100 8000 M1 100 5 0
1577800 1352000 30100 8000 M1 100 5 0
1577800 1390400 30100 8000 M1 100 5 0
1577800 1428800 30100 8000 M1 100 5 0
1055000 1470000 14000 54900 M2 010 4 0
1037000 1470000 14000 54900 M2 010 4 0
1055000 1524900 14000 6700 M1 010 4 0
1037000 1524900 14000 6700 M1 010 4 0
462100 462000 2 0 1 0
1001000 462000 4 0 4 0
1019000 462000 4 0 4 0
1001000 433000 11 0 4 0
1019000 433000 11 0 4 0
462100 507200 3 0 5 0
462100 545600 3 0 5 0
462100 584000 3 0 5 0
462100 622400 3 0 5 0
462100 660800 3 0 5 0
462100 699200 3 0 5 0
462100 737600 3 0 5 0
462100 776000 3 0 5 0
462100 814400 3 0 5 0
462100 852800 3 0 5 0
462100 891200 3 0 5 0
462100 929600 3 0 5 0
462100 968000 3 0 5 0
1055000 462000 4 0 4 0
1055000 433000 11 0 4 0
1037000 462000 4 0 4 0
1037000 433000 11 0 4 0
1587900 462000 2 0 1 0
1587900 507200 3 0 5 0
1587900 545600 3 0 5 0
1587900 584000 3 0 5 0
1587900 622400 3 0 5 0
1587900 660800 3 0 5 0
1587900 699200 3 0 5 0
1587900 737600 3 0 5 0
1587900 776000 3 0 5 0
1587900 814400 3 0 5 0
1587900 852800 3 0 5 0
1587900 891200 3 0 5 0
1587900 929600 3 0 5 0
1587900 968000 3 0 5 0
462100 1019000 6 0 4 0
462100 1001000 6 0 4 0
462100 1037000 10 0 4 0
462100 1083200 3 0 5 0
462100 1055000 6 0 4 0
462100 1121600 3 0 5 0
462100 1198400 3 0 5 0
462100 1160000 3 0 5 0
462100 1236800 3 0 5 0
462100 1275200 3 0 5 0
462100 1313600 3 0 5 0
462100 1352000 3 0 5 0
462100 1390400 3 0 5 0
462100 1428800 3 0 5 0
462100 1470000 2 0 1 0
1001000 1470000 4 0 4 0
1019000 1470000 4 0 4 0
1019500 1517900 5 0 4 0
1001500 1517900 5 0 4 0
1587900 1019000 6 0 4 0
1587900 1001000 6 0 4 0
1587900 1037000 10 0 4 0
1587900 1083200 3 0 5 0
1587900 1055000 6 0 4 0
1587900 1121600 3 0 5 0
1587900 1160000 3 0 5 0
1587900 1198400 3 0 5 0
1587900 1236800 3 0 5 0
1587900 1275200 3 0 5 0
1587900 1313600 3 0 5 0
1587900 1352000 3 0 5 0
1587900 1390400 3 0 5 0
1587900 1428800 3 0 5 0
1055000 1470000 4 0 4 0
1037000 1470000 4 0 4 0
1587900 1470000 2 0 1 0
1055500 1517900 5 0 4 0
1037500 1517900 5 0 4 0
106 68 1 vdd!
891000 428400 14000 31600 M1 010 4 0
945000 428400 14000 31600 M1 010 4 0
927000 428400 14000 31600 M1 010 4 0
909000 428400 14000 31600 M1 010 4 0
440100 492000 52100 4000 M1 100 5 0
440100 526400 52100 8000 M1 100 5 0
440100 564800 52100 8000 M1 100 5 0
440100 603200 52100 8000 M1 100 5 0
440100 641600 52100 8000 M1 100 5 0
440100 680000 52100 8000 M1 100 5 0
440100 718400 52100 8000 M1 100 5 0
440100 756800 52100 8000 M1 100 5 0
440100 833600 52100 8000 M1 100 5 0
440100 795200 52100 8000 M1 100 5 0
428400 891000 31700 14000 M1 100 4 0
440100 872000 52100 8000 M1 100 5 0
428400 909000 31700 14000 M1 100 4 0
440100 910400 52100 8000 M1 100 5 0
440100 948800 52100 8000 M1 100 5 0
428400 945000 31700 14000 M1 100 4 0
428400 927000 31700 14000 M1 100 4 0
440100 440000 1189800 20000 M1 100 1 0
492200 564800 1085600 8000 M1 100 3 0
492200 526400 1085600 8000 M1 100 3 0
492200 492000 1085600 4000 M1 100 3 0
492200 680000 1085600 8000 M1 100 3 0
492200 641600 1085600 8000 M1 100 3 0
492200 603200 1085600 8000 M1 100 3 0
492200 718400 1085600 8000 M1 100 3 0
492200 833600 1085600 8000 M1 100 3 0
492200 795200 1085600 8000 M1 100 3 0
492200 756800 1085600 8000 M1 100 3 0
492200 948800 1085600 8000 M1 100 3 0
492200 910400 1085600 8000 M1 100 3 0
492200 872000 1085600 8000 M1 100 3 0
1577800 492000 52100 4000 M1 100 5 0
1577800 526400 52100 8000 M1 100 5 0
1577800 564800 52100 8000 M1 100 5 0
1577800 603200 52100 8000 M1 100 5 0
1577800 641600 52100 8000 M1 100 5 0
1577800 680000 52100 8000 M1 100 5 0
1577800 718400 52100 8000 M1 100 5 0
1577800 756800 52100 8000 M1 100 5 0
1577800 833600 52100 8000 M1 100 5 0
1577800 795200 52100 8000 M1 100 5 0
1609900 891000 31700 14000 M1 100 4 0
1577800 872000 52100 8000 M1 100 5 0
1609900 909000 31700 14000 M1 100 4 0
1577800 910400 52100 8000 M1 100 5 0
1609900 945000 31700 14000 M1 100 4 0
1609900 927000 31700 14000 M1 100 4 0
1577800 948800 52100 8000 M1 100 5 0
440100 440000 20000 1072000 M2 010 1 0
1609900 440000 20000 1072000 M2 010 1 0
484750 1025600 8000 8000 M2 100 5 0
488750 1025600 7450 8000 M1 100 5 0
440100 1025600 48650 8000 M3 100 5 0
440100 987200 52100 8000 M1 100 5 0
484750 1064000 8000 8000 M2 100 5 0
488750 1064000 7450 8000 M1 100 5 0
440100 1064000 48650 8000 M3 100 5 0
440100 1102400 52100 8000 M1 100 5 0
440100 1140800 52100 8000 M1 100 5 0
440100 1179200 52100 8000 M1 100 5 0
440100 1217600 52100 8000 M1 100 5 0
440100 1256000 52100 8000 M1 100 5 0
440100 1294400 52100 8000 M1 100 5 0
440100 1332800 52100 8000 M1 100 5 0
440100 1371200 52100 8000 M1 100 5 0
440100 1409600 52100 8000 M1 100 5 0
440100 1448000 52100 4000 M1 100 5 0
891000 1492000 14000 39600 M1 010 4 0
909000 1492000 14000 39600 M1 010 4 0
945000 1492000 14000 39600 M1 010 4 0
927000 1492000 14000 39600 M1 010 4 0
492200 1025600 1085600 8000 M1 100 3 0
492200 987200 1085600 8000 M1 100 3 0
492200 1102400 1085600 8000 M1 100 3 0
492200 1064000 1085600 8000 M1 100 3 0
492200 1179200 1085600 8000 M1 100 3 0
492200 1140800 1085600 8000 M1 100 3 0
492200 1217600 1085600 8000 M1 100 3 0
492200 1448000 1085600 4000 M1 100 3 0
492200 1409600 1085600 8000 M1 100 3 0
492200 1371200 1085600 8000 M1 100 3 0
492200 1294400 1085600 8000 M1 100 3 0
492200 1332800 1085600 8000 M1 100 3 0
492200 1256000 1085600 8000 M1 100 3 0
440100 1492000 1189800 20000 M1 100 1 0
1581250 1025600 48650 8000 M3 100 5 0
1577800 987200 52100 8000 M1 100 5 0
1577250 1025600 8000 8000 M2 100 5 0
1573800 1025600 7450 8000 M1 100 5 0
1581250 1064000 48650 8000 M3 100 5 0
1577250 1064000 8000 8000 M2 100 5 0
1573800 1064000 7450 8000 M1 100 5 0
1577800 1102400 52100 8000 M1 100 5 0
1577800 1140800 52100 8000 M1 100 5 0
1577800 1179200 52100 8000 M1 100 5 0
1577800 1217600 52100 8000 M1 100 5 0
1577800 1256000 52100 8000 M1 100 5 0
1577800 1294400 52100 8000 M1 100 5 0
1577800 1332800 52100 8000 M1 100 5 0
1577800 1371200 52100 8000 M1 100 5 0
1577800 1448000 52100 4000 M1 100 5 0
1577800 1409600 52100 8000 M1 100 5 0
440100 440000 2 0 1 0
440100 492000 12 0 5 0
440100 526400 3 0 5 0
440100 564800 3 0 5 0
440100 603200 3 0 5 0
440100 641600 3 0 5 0
440100 680000 3 0 5 0
440100 718400 3 0 5 0
440100 756800 3 0 5 0
440100 833600 3 0 5 0
440100 795200 3 0 5 0
440100 891000 6 0 4 0
440100 872000 3 0 5 0
440100 909000 6 0 4 0
440100 927000 6 0 4 0
440100 945000 6 0 4 0
1609900 440000 2 0 1 0
1609900 492000 12 0 5 0
1609900 526400 3 0 5 0
1609900 564800 3 0 5 0
1609900 603200 3 0 5 0
1609900 641600 3 0 5 0
1609900 680000 3 0 5 0
1609900 718400 3 0 5 0
1609900 756800 3 0 5 0
1609900 795200 3 0 5 0
1609900 833600 3 0 5 0
1609900 872000 3 0 5 0
1609900 891000 6 0 4 0
1609900 909000 6 0 4 0
1609900 927000 6 0 4 0
1609900 945000 6 0 4 0
484750 1025600 8 0 5 0
484750 1025600 9 0 5 0
440100 1025600 7 0 5 0
440100 987200 3 0 5 0
484750 1064000 8 0 5 0
484750 1064000 9 0 5 0
440100 1064000 7 0 5 0
440100 1102400 3 0 5 0
440100 1140800 3 0 5 0
440100 1179200 3 0 5 0
440100 1217600 3 0 5 0
440100 1256000 3 0 5 0
440100 1294400 3 0 5 0
440100 1332800 3 0 5 0
440100 1371200 3 0 5 0
440100 1409600 3 0 5 0
440100 1448000 12 0 5 0
440100 1492000 2 0 1 0
1609900 1025600 7 0 5 0
1609900 987200 3 0 5 0
1577250 1025600 8 0 5 0
1577250 1025600 9 0 5 0
1609900 1064000 7 0 5 0
1577250 1064000 8 0 5 0
1577250 1064000 9 0 5 0
1609900 1102400 3 0 5 0
1609900 1140800 3 0 5 0
1609900 1179200 3 0 5 0
1609900 1217600 3 0 5 0
1609900 1256000 3 0 5 0
1609900 1294400 3 0 5 0
1609900 1332800 3 0 5 0
1609900 1371200 3 0 5 0
1609900 1448000 12 0 5 0
1609900 1409600 3 0 5 0
1609900 1492000 2 0 1 0
107 70 1 vdd!
436700 480000 44000 4000 M1 100 5 0
909000 428400 14000 27600 M1 010 4 0
927000 428400 14000 27600 M1 010 4 0
945000 428400 14000 27600 M1 010 4 0
891000 428400 14000 27600 M1 010 4 0
436700 514400 44000 8000 M1 100 5 0
436700 552800 44000 8000 M1 100 5 0
436700 591200 44000 8000 M1 100 5 0
436700 629600 44000 8000 M1 100 5 0
436700 668000 44000 8000 M1 100 5 0
436700 744800 44000 8000 M1 100 5 0
436700 706400 44000 8000 M1 100 5 0
428400 781000 28300 14000 M1 100 4 0
428400 799000 28300 14000 M1 100 4 0
428400 817000 28300 14000 M1 100 4 0
436700 783200 44000 8000 M1 100 5 0
436700 821600 44000 8000 M1 100 5 0
428400 835000 28300 14000 M1 100 4 0
436700 860000 44000 8000 M1 100 5 0
436700 898400 47450 8000 M3 100 5 0
480150 898400 8000 8000 M2 100 5 0
436700 936800 47450 8000 M3 100 5 0
480150 936800 8000 8000 M2 100 5 0
436700 436000 1196600 20000 M1 100 1 0
480700 480000 1108600 4000 M1 100 3 0
480700 591200 1108600 8000 M1 100 3 0
480700 629600 1108600 8000 M1 100 3 0
480700 668000 1108600 8000 M1 100 3 0
480700 514400 1108600 8000 M1 100 3 0
480700 552800 1108600 8000 M1 100 3 0
480700 860000 1108600 8000 M1 100 3 0
480700 898400 1108600 8000 M1 100 3 0
480700 936800 1108600 8000 M1 100 3 0
480700 706400 1108600 8000 M1 100 3 0
480700 744800 1108600 8000 M1 100 3 0
480700 783200 1108600 8000 M1 100 3 0
480700 821600 1108600 8000 M1 100 3 0
1589300 480000 44000 4000 M1 100 5 0
1589300 552800 44000 8000 M1 100 5 0
1589300 514400 44000 8000 M1 100 5 0
1589300 591200 44000 8000 M1 100 5 0
1589300 668000 44000 8000 M1 100 5 0
1589300 629600 44000 8000 M1 100 5 0
1589300 706400 44000 8000 M1 100 5 0
1589300 744800 44000 8000 M1 100 5 0
1589300 783200 44000 8000 M1 100 5 0
1589300 821600 44000 8000 M1 100 5 0
1589300 860000 44000 8000 M1 100 5 0
1589300 898400 44000 8000 M1 100 5 0
1613300 891000 28300 14000 M1 100 4 0
1613300 909000 28300 14000 M1 100 4 0
1585300 936800 25250 8000 M1 100 5 0
1602550 934400 8000 10400 M1 010 5 0
1602550 934400 30750 8000 M1 100 5 0
1613300 945000 28300 14000 M1 100 4 0
1613300 927000 28300 14000 M1 100 4 0
436700 436000 20000 1086400 M2 010 1 0
436700 975200 44000 8000 M1 100 5 0
480700 975200 1108600 8000 M1 100 3 0
1613300 436000 20000 1086400 M2 010 1 0
1589300 975200 44000 8000 M1 100 5 0
436700 1090400 44000 8000 M1 100 5 0
436700 1052000 44000 8000 M1 100 5 0
436700 1013600 44000 8000 M1 100 5 0
436700 1205600 44000 8000 M1 100 5 0
436700 1128800 44000 8000 M1 100 5 0
436700 1167200 44000 8000 M1 100 5 0
436700 1244000 44000 8000 M1 100 5 0
436700 1282400 44000 8000 M1 100 5 0
436700 1320800 44000 8000 M1 100 5 0
436700 1359200 44000 8000 M1 100 5 0
436700 1436000 44000 8000 M1 100 5 0
436700 1397600 44000 8000 M1 100 5 0
436700 1474400 44000 4000 M1 100 5 0
927000 1502400 14000 29200 M1 010 4 0
909000 1502400 14000 29200 M1 010 4 0
945000 1502400 14000 29200 M1 010 4 0
891000 1502400 14000 29200 M1 010 4 0
480700 1128800 1108600 8000 M1 100 3 0
480700 1167200 1108600 8000 M1 100 3 0
480700 1205600 1108600 8000 M1 100 3 0
480700 1013600 1108600 8000 M1 100 3 0
480700 1052000 1108600 8000 M1 100 3 0
480700 1090400 1108600 8000 M1 100 3 0
480700 1244000 1108600 8000 M1 100 3 0
480700 1397600 1108600 8000 M1 100 3 0
480700 1436000 1108600 8000 M1 100 3 0
480700 1282400 1108600 8000 M1 100 3 0
480700 1320800 1108600 8000 M1 100 3 0
480700 1359200 1108600 8000 M1 100 3 0
480700 1474400 1108600 4000 M1 100 3 0
436700 1502400 1196600 20000 M1 100 1 0
1581850 1013600 8000 8000 M2 100 5 0
1585850 1013600 47450 8000 M3 100 5 0
1581850 1052000 8000 8000 M2 100 5 0
1585850 1052000 47450 8000 M3 100 5 0
1589300 1090400 44000 8000 M1 100 5 0
1589300 1167200 44000 8000 M1 100 5 0
1589300 1128800 44000 8000 M1 100 5 0
1589300 1205600 44000 8000 M1 100 5 0
1589300 1244000 44000 8000 M1 100 5 0
1589300 1282400 44000 8000 M1 100 5 0
1589300 1320800 44000 8000 M1 100 5 0
1589300 1359200 44000 8000 M1 100 5 0
1589300 1397600 44000 8000 M1 100 5 0
1589300 1436000 44000 8000 M1 100 5 0
1589300 1474400 44000 4000 M1 100 5 0
436700 436000 2 0 1 0
436700 480000 11 0 5 0
436700 552800 3 0 5 0
436700 514400 3 0 5 0
436700 591200 3 0 5 0
436700 668000 3 0 5 0
436700 629600 3 0 5 0
436700 744800 3 0 5 0
436700 706400 3 0 5 0
436700 817000 6 0 4 0
436700 799000 6 0 4 0
436700 781000 6 0 4 0
436700 835000 6 0 4 0
436700 860000 3 0 5 0
436700 898400 12 0 5 0
480150 898400 15 0 5 0
480150 898400 14 0 5 0
436700 936800 12 0 5 0
480150 936800 15 0 5 0
480150 936800 14 0 5 0
1613300 436000 2 0 1 0
1613300 480000 11 0 5 0
1613300 552800 3 0 5 0
1613300 514400 3 0 5 0
1613300 591200 3 0 5 0
1613300 668000 3 0 5 0
1613300 629600 3 0 5 0
1613300 706400 3 0 5 0
1613300 744800 3 0 5 0
1613300 821600 3 0 5 0
1613300 783200 3 0 5 0
1613300 860000 3 0 5 0
1613300 891000 13 0 4 0
1613300 909000 6 0 4 0
1613300 945000 6 0 4 0
1613300 927000 13 0 4 0
436700 975200 3 0 5 0
1613300 975200 3 0 5 0
436700 1090400 3 0 5 0
436700 1052000 3 0 5 0
436700 1013600 3 0 5 0
436700 1205600 3 0 5 0
436700 1167200 3 0 5 0
436700 1128800 3 0 5 0
436700 1244000 3 0 5 0
436700 1282400 3 0 5 0
436700 1320800 3 0 5 0
436700 1359200 3 0 5 0
436700 1436000 3 0 5 0
436700 1397600 3 0 5 0
436700 1474400 11 0 5 0
436700 1502400 2 0 1 0
1581850 1013600 15 0 5 0
1581850 1013600 14 0 5 0
1613300 1013600 12 0 5 0
1581850 1052000 15 0 5 0
1581850 1052000 14 0 5 0
1613300 1052000 12 0 5 0
1613300 1090400 3 0 5 0
1613300 1167200 3 0 5 0
1613300 1128800 3 0 5 0
1613300 1205600 3 0 5 0
1613300 1244000 3 0 5 0
1613300 1282400 3 0 5 0
1613300 1320800 3 0 5 0
1613300 1359200 3 0 5 0
1613300 1436000 3 0 5 0
1613300 1397600 3 0 5 0
1613300 1474400 11 0 5 0
1613300 1502400 2 0 1 0
/trunk/syn/cadence/results/floorplan/t6507lp_io.fp
4,13 → 4,13
# FirstEncounter Floor Plan Information #
# #
######################################################
# Created by First Encounter v07.10-p011_1 on Thu Aug 6 06:27:23 2009
# Created by First Encounter v07.10-p011_1 on Fri Aug 7 15:47:14 2009
 
Version: 8
 
Head Box: 0.0000 0.0000 2070.0000 1960.0000
IO Box: 430.0000 430.0000 1640.0000 1530.0000
Core Box: 492.2000 492.0000 1580.0000 1452.0000
Core Box: 480.7000 480.0000 1590.0000 1478.4000
UseStdUtil: false
 
######################################################
28,56 → 28,58
##############################################################################
# DefRow: <name> <site> <x> <y> <orient> <num_x> <num_y> <step_x> <step_y> #
##############################################################################
DefRow: ROW_0 core_l 492.2000 492.0000 FS 472 1 2.3000 0.0000
DefRow: ROW_1 core_l 492.2000 511.2000 N 472 1 2.3000 0.0000
DefRow: ROW_2 core_l 492.2000 530.4000 FS 472 1 2.3000 0.0000
DefRow: ROW_3 core_l 492.2000 549.6000 N 472 1 2.3000 0.0000
DefRow: ROW_4 core_l 492.2000 568.8000 FS 472 1 2.3000 0.0000
DefRow: ROW_5 core_l 492.2000 588.0000 N 472 1 2.3000 0.0000
DefRow: ROW_6 core_l 492.2000 607.2000 FS 472 1 2.3000 0.0000
DefRow: ROW_7 core_l 492.2000 626.4000 N 472 1 2.3000 0.0000
DefRow: ROW_8 core_l 492.2000 645.6000 FS 472 1 2.3000 0.0000
DefRow: ROW_9 core_l 492.2000 664.8000 N 472 1 2.3000 0.0000
DefRow: ROW_10 core_l 492.2000 684.0000 FS 472 1 2.3000 0.0000
DefRow: ROW_11 core_l 492.2000 703.2000 N 472 1 2.3000 0.0000
DefRow: ROW_12 core_l 492.2000 722.4000 FS 472 1 2.3000 0.0000
DefRow: ROW_13 core_l 492.2000 741.6000 N 472 1 2.3000 0.0000
DefRow: ROW_14 core_l 492.2000 760.8000 FS 472 1 2.3000 0.0000
DefRow: ROW_15 core_l 492.2000 780.0000 N 472 1 2.3000 0.0000
DefRow: ROW_16 core_l 492.2000 799.2000 FS 472 1 2.3000 0.0000
DefRow: ROW_17 core_l 492.2000 818.4000 N 472 1 2.3000 0.0000
DefRow: ROW_18 core_l 492.2000 837.6000 FS 472 1 2.3000 0.0000
DefRow: ROW_19 core_l 492.2000 856.8000 N 472 1 2.3000 0.0000
DefRow: ROW_20 core_l 492.2000 876.0000 FS 472 1 2.3000 0.0000
DefRow: ROW_21 core_l 492.2000 895.2000 N 472 1 2.3000 0.0000
DefRow: ROW_22 core_l 492.2000 914.4000 FS 472 1 2.3000 0.0000
DefRow: ROW_23 core_l 492.2000 933.6000 N 472 1 2.3000 0.0000
DefRow: ROW_24 core_l 492.2000 952.8000 FS 472 1 2.3000 0.0000
DefRow: ROW_25 core_l 492.2000 972.0000 N 472 1 2.3000 0.0000
DefRow: ROW_26 core_l 492.2000 991.2000 FS 472 1 2.3000 0.0000
DefRow: ROW_27 core_l 492.2000 1010.4000 N 472 1 2.3000 0.0000
DefRow: ROW_28 core_l 492.2000 1029.6000 FS 472 1 2.3000 0.0000
DefRow: ROW_29 core_l 492.2000 1048.8000 N 472 1 2.3000 0.0000
DefRow: ROW_30 core_l 492.2000 1068.0000 FS 472 1 2.3000 0.0000
DefRow: ROW_31 core_l 492.2000 1087.2000 N 472 1 2.3000 0.0000
DefRow: ROW_32 core_l 492.2000 1106.4000 FS 472 1 2.3000 0.0000
DefRow: ROW_33 core_l 492.2000 1125.6000 N 472 1 2.3000 0.0000
DefRow: ROW_34 core_l 492.2000 1144.8000 FS 472 1 2.3000 0.0000
DefRow: ROW_35 core_l 492.2000 1164.0000 N 472 1 2.3000 0.0000
DefRow: ROW_36 core_l 492.2000 1183.2000 FS 472 1 2.3000 0.0000
DefRow: ROW_37 core_l 492.2000 1202.4000 N 472 1 2.3000 0.0000
DefRow: ROW_38 core_l 492.2000 1221.6000 FS 472 1 2.3000 0.0000
DefRow: ROW_39 core_l 492.2000 1240.8000 N 472 1 2.3000 0.0000
DefRow: ROW_40 core_l 492.2000 1260.0000 FS 472 1 2.3000 0.0000
DefRow: ROW_41 core_l 492.2000 1279.2000 N 472 1 2.3000 0.0000
DefRow: ROW_42 core_l 492.2000 1298.4000 FS 472 1 2.3000 0.0000
DefRow: ROW_43 core_l 492.2000 1317.6000 N 472 1 2.3000 0.0000
DefRow: ROW_44 core_l 492.2000 1336.8000 FS 472 1 2.3000 0.0000
DefRow: ROW_45 core_l 492.2000 1356.0000 N 472 1 2.3000 0.0000
DefRow: ROW_46 core_l 492.2000 1375.2000 FS 472 1 2.3000 0.0000
DefRow: ROW_47 core_l 492.2000 1394.4000 N 472 1 2.3000 0.0000
DefRow: ROW_48 core_l 492.2000 1413.6000 FS 472 1 2.3000 0.0000
DefRow: ROW_49 core_l 492.2000 1432.8000 N 472 1 2.3000 0.0000
DefRow: ROW_0 core_l 480.7000 480.0000 FS 482 1 2.3000 0.0000
DefRow: ROW_1 core_l 480.7000 499.2000 N 482 1 2.3000 0.0000
DefRow: ROW_2 core_l 480.7000 518.4000 FS 482 1 2.3000 0.0000
DefRow: ROW_3 core_l 480.7000 537.6000 N 482 1 2.3000 0.0000
DefRow: ROW_4 core_l 480.7000 556.8000 FS 482 1 2.3000 0.0000
DefRow: ROW_5 core_l 480.7000 576.0000 N 482 1 2.3000 0.0000
DefRow: ROW_6 core_l 480.7000 595.2000 FS 482 1 2.3000 0.0000
DefRow: ROW_7 core_l 480.7000 614.4000 N 482 1 2.3000 0.0000
DefRow: ROW_8 core_l 480.7000 633.6000 FS 482 1 2.3000 0.0000
DefRow: ROW_9 core_l 480.7000 652.8000 N 482 1 2.3000 0.0000
DefRow: ROW_10 core_l 480.7000 672.0000 FS 482 1 2.3000 0.0000
DefRow: ROW_11 core_l 480.7000 691.2000 N 482 1 2.3000 0.0000
DefRow: ROW_12 core_l 480.7000 710.4000 FS 482 1 2.3000 0.0000
DefRow: ROW_13 core_l 480.7000 729.6000 N 482 1 2.3000 0.0000
DefRow: ROW_14 core_l 480.7000 748.8000 FS 482 1 2.3000 0.0000
DefRow: ROW_15 core_l 480.7000 768.0000 N 482 1 2.3000 0.0000
DefRow: ROW_16 core_l 480.7000 787.2000 FS 482 1 2.3000 0.0000
DefRow: ROW_17 core_l 480.7000 806.4000 N 482 1 2.3000 0.0000
DefRow: ROW_18 core_l 480.7000 825.6000 FS 482 1 2.3000 0.0000
DefRow: ROW_19 core_l 480.7000 844.8000 N 482 1 2.3000 0.0000
DefRow: ROW_20 core_l 480.7000 864.0000 FS 482 1 2.3000 0.0000
DefRow: ROW_21 core_l 480.7000 883.2000 N 482 1 2.3000 0.0000
DefRow: ROW_22 core_l 480.7000 902.4000 FS 482 1 2.3000 0.0000
DefRow: ROW_23 core_l 480.7000 921.6000 N 482 1 2.3000 0.0000
DefRow: ROW_24 core_l 480.7000 940.8000 FS 482 1 2.3000 0.0000
DefRow: ROW_25 core_l 480.7000 960.0000 N 482 1 2.3000 0.0000
DefRow: ROW_26 core_l 480.7000 979.2000 FS 482 1 2.3000 0.0000
DefRow: ROW_27 core_l 480.7000 998.4000 N 482 1 2.3000 0.0000
DefRow: ROW_28 core_l 480.7000 1017.6000 FS 482 1 2.3000 0.0000
DefRow: ROW_29 core_l 480.7000 1036.8000 N 482 1 2.3000 0.0000
DefRow: ROW_30 core_l 480.7000 1056.0000 FS 482 1 2.3000 0.0000
DefRow: ROW_31 core_l 480.7000 1075.2000 N 482 1 2.3000 0.0000
DefRow: ROW_32 core_l 480.7000 1094.4000 FS 482 1 2.3000 0.0000
DefRow: ROW_33 core_l 480.7000 1113.6000 N 482 1 2.3000 0.0000
DefRow: ROW_34 core_l 480.7000 1132.8000 FS 482 1 2.3000 0.0000
DefRow: ROW_35 core_l 480.7000 1152.0000 N 482 1 2.3000 0.0000
DefRow: ROW_36 core_l 480.7000 1171.2000 FS 482 1 2.3000 0.0000
DefRow: ROW_37 core_l 480.7000 1190.4000 N 482 1 2.3000 0.0000
DefRow: ROW_38 core_l 480.7000 1209.6000 FS 482 1 2.3000 0.0000
DefRow: ROW_39 core_l 480.7000 1228.8000 N 482 1 2.3000 0.0000
DefRow: ROW_40 core_l 480.7000 1248.0000 FS 482 1 2.3000 0.0000
DefRow: ROW_41 core_l 480.7000 1267.2000 N 482 1 2.3000 0.0000
DefRow: ROW_42 core_l 480.7000 1286.4000 FS 482 1 2.3000 0.0000
DefRow: ROW_43 core_l 480.7000 1305.6000 N 482 1 2.3000 0.0000
DefRow: ROW_44 core_l 480.7000 1324.8000 FS 482 1 2.3000 0.0000
DefRow: ROW_45 core_l 480.7000 1344.0000 N 482 1 2.3000 0.0000
DefRow: ROW_46 core_l 480.7000 1363.2000 FS 482 1 2.3000 0.0000
DefRow: ROW_47 core_l 480.7000 1382.4000 N 482 1 2.3000 0.0000
DefRow: ROW_48 core_l 480.7000 1401.6000 FS 482 1 2.3000 0.0000
DefRow: ROW_49 core_l 480.7000 1420.8000 N 482 1 2.3000 0.0000
DefRow: ROW_50 core_l 480.7000 1440.0000 FS 482 1 2.3000 0.0000
DefRow: ROW_51 core_l 480.7000 1459.2000 N 482 1 2.3000 0.0000
 
######################################################
# Track: dir start number space layer_num layer1 ...#
249,7 → 251,7
# PinBox: <llx> <lly> <urx> <ury> #
# PinPoly: <nrPt> <x1> <y1> <x2> <y2> ...<xn> <yn> #
#######################################################################################
IO: filler1 FILLERP_110 1530.0000 1530.0000 N R180 - 01
IO: test_pad ICP 1530.0000 1530.0000 N R180 - 01
IO: data_in_pad7 ICP 1420.0000 1530.0000 N R180 - 01
IO: data_in_pad6 ICP 1310.0000 1530.0000 N R180 - 01
IO: data_in_pad5 ICP 1200.0000 1530.0000 N R180 - 01
264,11 → 266,11
IO: left_up_pad CORNERCLMP 0.0000 1530.0000 NW R270 - 01
IO: reset_n_pad ICP 0.0000 1420.0000 W R270 - 01
IO: clk_pad ICP 0.0000 1310.0000 W R270 - 01
IO: rw_mem_pad BT4P 0.0000 1200.0000 W R270 - 01
IO: address_pad12 BT4P 0.0000 1090.0000 W R270 - 01
IO: gnd_pad_left GND5ALLPADP 0.0000 980.0000 W R270 - 01
IO: vdd_pad_left VDD5ALLPADP 0.0000 870.0000 W R270 - 01
IO: filler0 FILLERP_110 0.0000 760.0000 W R270 - 01
IO: scan_pad ICP 0.0000 1200.0000 W R270 - 01
IO: rw_mem_pad BT4P 0.0000 1090.0000 W R270 - 01
IO: address_pad12 BT4P 0.0000 980.0000 W R270 - 01
IO: gnd_pad_left GND5ALLPADP 0.0000 870.0000 W R270 - 01
IO: vdd_pad_left VDD5ALLPADP 0.0000 760.0000 W R270 - 01
IO: address_pad11 BT4P 0.0000 650.0000 W R270 - 01
IO: address_pad10 BT4P 0.0000 540.0000 W R270 - 01
IO: address_pad9 BT4P 0.0000 430.0000 W R270 - 01
/trunk/syn/cadence/extras/iofile/t6507lp_io.geom.rpt.old
0,0 → 1,1157
Verify Geometry report created on Tue Jul 28 14:21:11 2009
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1643.400 ) ( 848.700, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1678.300 ) ( 845.400, 1744.300 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 765.500, 1643.200 ) ( 843.600, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 808.750, 1640.400 ) ( 831.850, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.700, 1679.100 ) ( 845.200, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.700, 1640.500 ) ( 844.450, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.700, 1640.500 ) ( 843.600, 2070.000 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 804.500, 1640.400 ) ( 869.600, 1977.200 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 788.700, 1643.200 ) ( 864.500, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 805.250, 1640.400 ) ( 866.300, 2069.600 )
 
 
OVERLAP: Cell filler1 & Cell address_pad12
Bounds : ( 784.800, 1640.000 ) ( 849.100, 2070.000 )
 
 
OVERLAP: Cell reset_n_pad & Cell address_pad12
Bounds : ( 760.000, 1640.000 ) ( 849.100, 2070.000 )
 
 
OVERLAP: Cell reset_n_pad & Cell filler1
Bounds : ( 784.800, 1640.000 ) ( 870.000, 2070.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1679.100 ) ( 763.100, 1743.500 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1679.100 ) ( 764.700, 1743.500 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1679.100 ) ( 743.800, 1743.500 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1679.100 ) ( 742.200, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1679.100 ) ( 787.900, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1679.100 ) ( 787.900, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 785.200, 1643.200 ) ( 804.250, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1643.150 ) ( 783.550, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 785.200, 1640.400 ) ( 803.800, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1640.400 ) ( 783.300, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 739.500, 1640.400 ) ( 759.600, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 748.300, 1640.400 ) ( 750.800, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 743.000, 1640.400 ) ( 756.300, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 788.250, 1640.400 ) ( 794.950, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 788.700, 1640.400 ) ( 803.050, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 765.500, 1640.400 ) ( 782.550, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1640.400 ) ( 782.550, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 744.600, 1640.400 ) ( 754.500, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.800, 1679.100 ) ( 756.100, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.800, 1640.500 ) ( 754.500, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.800, 1640.500 ) ( 755.350, 2069.500 )
 
 
OVERLAP: Cell clk_pad & Cell address_pad12
Bounds : ( 739.100, 1640.000 ) ( 760.000, 2070.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1679.100 ) ( 849.100, 1743.500 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1679.100 ) ( 849.100, 1743.500 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1679.100 ) ( 873.100, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1679.100 ) ( 894.800, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1679.100 ) ( 894.800, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 837.400, 1640.400 ) ( 848.700, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 837.550, 1640.400 ) ( 843.600, 2070.000 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M1 )
Bounds : ( 870.400, 1640.400 ) ( 894.400, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 858.300, 1640.400 ) ( 869.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 873.900, 1640.400 ) ( 891.100, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1679.100 ) ( 890.900, 1743.500 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.850, 1640.500 ) ( 890.150, 2069.500 )
 
 
OVERLAP: Cell filler0 & Cell filler1
Bounds : ( 870.000, 1640.000 ) ( 894.800, 2070.000 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1679.100 ) ( 1200.000, 1743.500 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.650, 1679.100 ) ( 1200.000, 1743.500 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1679.100 ) ( 1196.100, 1743.500 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1679.100 ) ( 1195.050, 1743.500 )
 
 
SPACING: Pin of Cell address_pad11 & Pin of Cell address_pad10 ( M3 )
Bounds : ( 1196.650, 1679.100 ) ( 1197.100, 1743.500 )
Actual: 0.45 Min: 1 SameNetGap
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M1 )
Bounds : ( 1192.350, 1640.400 ) ( 1199.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1195.850, 1640.400 ) ( 1196.300, 2069.600 )
 
 
OVERLAP: Cell address_pad10 & Cell address_pad11
Bounds : ( 1191.950, 1640.000 ) ( 1200.000, 2070.000 )
 
 
SPACING: Blockage of Cell vdd_pad_left & Pin of Cell left_down_pad ( M1 )
Bounds : ( 427.400, 430.000 ) ( 429.600, 430.400 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell left_down_pad & Blockage of Cell data_in_pad0 ( M1 )
Bounds : ( 430.000, 427.400 ) ( 430.400, 429.600 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell left_down_pad & Blockage of Cell data_in_pad0 ( M1 )
Bounds : ( 430.000, 426.900 ) ( 430.400, 427.400 )
Actual: 0.64 Min: 0.8
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1643.200 ) ( 845.400, 1677.900 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1677.900 ) ( 848.700, 1678.300 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 760.500, 1640.500 ) ( 848.600, 1641.450 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1643.200 ) ( 845.200, 1677.100 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.850, 1640.500 ) ( 844.450, 1678.100 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 805.250, 1640.400 ) ( 869.600, 1642.400 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M1 )
Bounds : ( 784.100, 1640.400 ) ( 786.700, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1643.200 ) ( 763.100, 1677.100 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1643.200 ) ( 763.100, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1643.200 ) ( 742.200, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1643.200 ) ( 742.200, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 804.600, 1640.400 ) ( 807.200, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M1 )
Bounds : ( 801.100, 1640.400 ) ( 803.700, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M1 )
Bounds : ( 796.500, 1640.400 ) ( 799.100, 1642.600 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1643.200 ) ( 787.900, 1677.100 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1643.200 ) ( 787.900, 1677.100 )
 
 
SPACING: Blockage of Cell rw_mem_pad & Pin of Cell left_up_pad ( M1 )
Bounds : ( 426.850, 1639.600 ) ( 427.400, 1640.000 )
Actual: 0.68 Min: 0.8
 
SPACING: Blockage of Cell rw_mem_pad & Pin of Cell left_up_pad ( M1 )
Bounds : ( 427.400, 1639.600 ) ( 429.600, 1640.000 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell left_up_pad & Blockage of Cell gnd_pad_up ( M1 )
Bounds : ( 430.000, 1640.400 ) ( 430.400, 1642.600 )
Actual: 0.4 Min: 0.8
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1677.900 ) ( 759.600, 1678.300 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1640.400 ) ( 759.600, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 785.200, 1640.400 ) ( 803.050, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1640.400 ) ( 782.550, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.600, 1640.500 ) ( 759.500, 1641.450 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1643.200 ) ( 756.100, 1677.100 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.950, 1640.500 ) ( 755.350, 1678.100 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1643.200 ) ( 1200.000, 1677.100 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1643.200 ) ( 1200.000, 1677.100 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1643.200 ) ( 1195.050, 1677.100 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1643.200 ) ( 1195.050, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1643.200 ) ( 849.100, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1643.200 ) ( 849.100, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 833.400, 1640.400 ) ( 836.000, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1643.200 ) ( 873.100, 1677.100 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1643.200 ) ( 894.800, 1677.100 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1643.200 ) ( 894.800, 1677.100 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1677.900 ) ( 1199.600, 1678.300 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1640.400 ) ( 1199.600, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1192.450, 1640.500 ) ( 1199.500, 1641.450 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1643.200 ) ( 1196.100, 1677.100 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1677.900 ) ( 894.400, 1678.300 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1640.400 ) ( 894.400, 1642.400 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 870.500, 1640.500 ) ( 894.300, 1641.450 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1643.200 ) ( 890.900, 1677.100 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1374.450 ) ( 1550.750, 1388.450 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1971.350, 1353.850 ) ( 1975.550, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1551.550, 1353.850 ) ( 1884.750, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1688.150, 1357.150 ) ( 1868.350, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1652.250, 1357.150 ) ( 1687.750, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1585.850, 1357.150 ) ( 1651.850, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1357.150 ) ( 1585.450, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1868.350, 1353.850 ) ( 1977.150, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1687.750, 1353.850 ) ( 1688.150, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1651.850, 1353.850 ) ( 1652.250, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1585.450, 1353.850 ) ( 1585.850, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1358.950 ) ( 1977.550, 1414.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1358.950 ) ( 1977.150, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1869.300, 1353.950 ) ( 1977.050, 1419.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1353.950 ) ( 1549.000, 1419.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1783.850, 1357.350 ) ( 1867.550, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1779.750, 1357.350 ) ( 1782.350, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1688.950, 1357.350 ) ( 1778.250, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1653.050, 1357.350 ) ( 1686.950, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1586.650, 1357.350 ) ( 1651.050, 1414.300 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1550.750, 1357.350 ) ( 1584.650, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1652.050, 1358.100 ) ( 1977.050, 1415.150 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1358.100 ) ( 1977.050, 1414.300 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1358.100 ) ( 1585.650, 1415.150 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1652.050, 1358.950 ) ( 1977.550, 1414.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1358.950 ) ( 1977.550, 1414.300 )
 
 
SHORT: Pin of Cell gnd_pad_right & Pin of Cell address_pad8 ( M1 )
Bounds : ( 1885.550, 1365.950 ) ( 1970.550, 1407.500 )
 
 
OVERLAP: Cell address_pad8 & Cell gnd_pad_right
Bounds : ( 1547.550, 1353.450 ) ( 1977.550, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M1 )
Bounds : ( 1885.550, 1353.850 ) ( 1970.550, 1365.150 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M1 )
Bounds : ( 1547.950, 1353.850 ) ( 1550.150, 1354.500 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1653.050, 1353.450 ) ( 1686.950, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1353.450 ) ( 1584.650, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1653.050, 1353.450 ) ( 1686.950, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1550.750, 1353.450 ) ( 1584.650, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1688.950, 1353.450 ) ( 1778.250, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1688.950, 1353.450 ) ( 1778.250, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1783.850, 1353.450 ) ( 1867.550, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1586.650, 1353.450 ) ( 1651.050, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1783.850, 1353.450 ) ( 1867.550, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1586.650, 1353.450 ) ( 1651.050, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1779.750, 1353.450 ) ( 1782.350, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1779.750, 1353.450 ) ( 1782.350, 1356.350 )
 
 
SPACING: Pin of Cell right_down_pad & Blockage of Cell address_pad0 ( M1 )
Bounds : ( 1547.950, 430.000 ) ( 1550.150, 430.400 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell right_down_pad & Blockage of Cell address_pad0 ( M1 )
Bounds : ( 1550.150, 430.000 ) ( 1550.700, 430.400 )
Actual: 0.68 Min: 0.8
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1355.300 ) ( 1884.750, 1373.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1550.750, 1354.850 ) ( 1884.750, 1373.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1550.950, 1353.850 ) ( 1884.750, 1373.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1356.050 ) ( 1549.950, 1372.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1357.150 ) ( 1977.150, 1372.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1358.950 ) ( 1977.550, 1372.900 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1688.950, 1416.900 ) ( 1778.250, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1688.950, 1416.900 ) ( 1778.250, 1420.000 )
 
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M2 )
Bounds : ( 1688.950, 1639.300 ) ( 1778.250, 1640.000 )
Actual: 0.7 Min: 0.8 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M3 )
Bounds : ( 1688.950, 1639.300 ) ( 1778.250, 1640.000 )
Actual: 0.7 Min: 1 SameNetGap
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1407.250 ) ( 1884.750, 1409.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1389.250 ) ( 1884.750, 1391.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1408.000 ) ( 1977.550, 1408.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1390.000 ) ( 1977.550, 1390.900 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1653.050, 1416.900 ) ( 1686.950, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1586.650, 1416.900 ) ( 1651.050, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1550.750, 1416.900 ) ( 1584.650, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1653.050, 1416.900 ) ( 1686.950, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1586.650, 1415.300 ) ( 1651.050, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1550.750, 1416.900 ) ( 1584.650, 1420.000 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1410.450 ) ( 1550.750, 1419.600 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1392.450 ) ( 1550.750, 1406.450 )
 
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M2 )
Bounds : ( 1653.050, 1639.300 ) ( 1686.950, 1640.000 )
Actual: 0.7 Min: 0.8 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M2 )
Bounds : ( 1550.750, 1639.300 ) ( 1584.650, 1640.000 )
Actual: 0.7 Min: 0.8 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M3 )
Bounds : ( 1653.050, 1639.300 ) ( 1686.950, 1640.000 )
Actual: 0.7 Min: 1 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M3 )
Bounds : ( 1550.750, 1639.300 ) ( 1584.650, 1640.000 )
Actual: 0.7 Min: 1 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M2 )
Bounds : ( 1586.650, 1639.300 ) ( 1651.050, 1640.000 )
Actual: 0.7 Min: 0.8 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M3 )
Bounds : ( 1586.650, 1639.300 ) ( 1651.050, 1640.000 )
Actual: 0.7 Min: 1 SameNetGap
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1783.850, 1416.900 ) ( 1867.550, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1783.850, 1416.900 ) ( 1867.550, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1779.750, 1416.900 ) ( 1782.350, 1420.000 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1885.550, 1408.300 ) ( 1970.550, 1419.600 )
 
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M2 )
Bounds : ( 1783.850, 1639.300 ) ( 1867.550, 1640.000 )
Actual: 0.7 Min: 0.8 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M3 )
Bounds : ( 1783.850, 1639.300 ) ( 1867.550, 1640.000 )
Actual: 0.7 Min: 1 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M2 )
Bounds : ( 1779.750, 1639.300 ) ( 1782.350, 1640.000 )
Actual: 0.7 Min: 0.8 SameNetGap
 
SPACING: Pin of Cell vdd_pad_right & Pin of Cell right_up_pad ( M3 )
Bounds : ( 1779.750, 1639.300 ) ( 1782.350, 1640.000 )
Actual: 0.7 Min: 1 SameNetGap
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M1 )
Bounds : ( 772.500, 1978.000 ) ( 857.500, 2063.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 2063.800 ) ( 848.700, 2068.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1780.600 ) ( 845.400, 1960.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1744.700 ) ( 845.400, 1780.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1960.800 ) ( 848.700, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1780.200 ) ( 848.700, 1780.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1744.300 ) ( 848.700, 1744.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 760.500, 1961.750 ) ( 848.600, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1876.300 ) ( 845.200, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1872.200 ) ( 845.200, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1781.400 ) ( 845.200, 1870.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1745.500 ) ( 845.200, 1779.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.850, 1744.500 ) ( 844.450, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.500, 1744.500 ) ( 843.600, 2070.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1876.300 ) ( 763.100, 1960.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1876.300 ) ( 763.100, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1876.300 ) ( 742.200, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1876.300 ) ( 742.200, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1876.300 ) ( 787.900, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1876.300 ) ( 787.900, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1876.300 ) ( 756.100, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.950, 1744.500 ) ( 755.350, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.600, 1744.500 ) ( 754.500, 2070.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1781.400 ) ( 763.100, 1870.700 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1745.500 ) ( 763.100, 1779.400 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1872.200 ) ( 763.100, 1874.800 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1781.400 ) ( 763.100, 1870.700 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1745.500 ) ( 763.100, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1745.500 ) ( 742.200, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1745.500 ) ( 742.200, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1781.400 ) ( 742.200, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1781.400 ) ( 742.200, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1872.200 ) ( 742.200, 1874.800 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1872.200 ) ( 742.200, 1874.800 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1745.500 ) ( 787.900, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1745.500 ) ( 787.900, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1781.400 ) ( 787.900, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1781.400 ) ( 787.900, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1872.200 ) ( 787.900, 1874.800 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1872.200 ) ( 787.900, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1780.200 ) ( 759.600, 1780.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1744.300 ) ( 759.600, 1744.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1872.200 ) ( 756.100, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1781.400 ) ( 756.100, 1870.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1745.500 ) ( 756.100, 1779.400 )
 
 
SHORT: Pin of Cell clk_pad & Blockage of Cell address_pad12 ( M1 )
Bounds : ( 739.500, 1978.000 ) ( 747.500, 2063.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1978.000 ) ( 771.700, 2063.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 751.600, 1978.000 ) ( 759.600, 2063.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 739.500, 2063.800 ) ( 759.600, 2068.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1960.800 ) ( 759.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.600, 1961.750 ) ( 759.500, 2069.500 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1876.300 ) ( 1200.000, 1960.000 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1876.300 ) ( 1200.000, 1960.000 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1876.300 ) ( 1195.050, 1960.000 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1876.300 ) ( 1195.050, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1876.300 ) ( 849.100, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1876.300 ) ( 849.100, 1960.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1876.300 ) ( 873.100, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1876.300 ) ( 894.800, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1876.300 ) ( 894.800, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1876.300 ) ( 1196.100, 1960.000 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1876.300 ) ( 890.900, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1745.500 ) ( 849.100, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1745.500 ) ( 849.100, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1781.400 ) ( 849.100, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1781.400 ) ( 849.100, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1872.200 ) ( 849.100, 1874.800 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1872.200 ) ( 849.100, 1874.800 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1872.200 ) ( 873.100, 1874.800 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1781.400 ) ( 873.100, 1870.700 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1745.500 ) ( 873.100, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1745.500 ) ( 894.800, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1745.500 ) ( 894.800, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1781.400 ) ( 894.800, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1781.400 ) ( 894.800, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1872.200 ) ( 894.800, 1874.800 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1872.200 ) ( 894.800, 1874.800 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1780.200 ) ( 894.400, 1780.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1744.300 ) ( 894.400, 1744.700 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1872.200 ) ( 890.900, 1874.800 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1781.400 ) ( 890.900, 1870.700 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1745.500 ) ( 890.900, 1779.400 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1872.200 ) ( 1200.000, 1874.800 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1781.400 ) ( 1200.000, 1870.700 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1745.500 ) ( 1200.000, 1779.400 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1872.200 ) ( 1200.000, 1874.800 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1781.400 ) ( 1200.000, 1870.700 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1745.500 ) ( 1200.000, 1779.400 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1745.500 ) ( 1195.050, 1779.400 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1745.500 ) ( 1195.050, 1779.400 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1781.400 ) ( 1195.050, 1870.700 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1781.400 ) ( 1195.050, 1870.700 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1872.200 ) ( 1195.050, 1874.800 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1872.200 ) ( 1195.050, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1780.200 ) ( 1199.600, 1780.600 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1744.300 ) ( 1199.600, 1744.700 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1872.200 ) ( 1196.100, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1781.400 ) ( 1196.100, 1870.700 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1745.500 ) ( 1196.100, 1779.400 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1960.800 ) ( 1199.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1192.450, 1961.750 ) ( 1199.500, 2069.500 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1960.800 ) ( 894.400, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 870.500, 1961.750 ) ( 894.300, 2069.500 )
 
 
 
Begin Summary ...
Cells : 0
SameNet : 21
Wiring : 0
Antenna : 0
Short : 128
Overlap : 137
End Summary
 
Total Violations : 286 Viols.
/trunk/syn/cadence/extras/iofile/encounter.log
0,0 → 1,1064
This version requires license using cdslmd daemon.
Checking out Encounter license ...
SOC_Encounter_GPS 7.1 license checkout succeeded.
INFO: Current OA version selected: OA22
INFO: This Encounter release has been compiled with OA data Model 4 and OA version p006.
Starting console server on port samuel.nscad.org.br:8888 ..
sourcing /cds/SOC71/tools/fe/etc/rdaDSL.tcl
*******************************************************************
* Copyright (c) Cadence Design Systems, Inc. 1996 - 2007. *
* All rights reserved. *
* *
* *
* *
* This program contains confidential and trade secret information *
* of Cadence Design Systems, Inc. and is protected by copyright *
* law and international treaties. Any reproduction, use, *
* distribution or disclosure of this program or any portion of it,*
* or any attempt to obtain a human-readable version of this *
* program, without the express, prior written consent of *
* Cadence Design Systems, Inc., is strictly prohibited. *
* *
* Cadence Design Systems, Inc. *
* 2655 Seely Avenue *
* San Jose, CA 95134, USA *
* *
* *
*******************************************************************
 
@(#)CDS: First Encounter v07.10-p011_1 (32bit) 10/29/2007 17:15 (Linux 2.4)
@(#)CDS: NanoRoute v07.10-p014 NR071019-1931/USR51-UB (database version 2.30, 53.1.0) {superthreading v1.9}
@(#)CDS: CeltIC v07.10-p003_1 (32bit) 10/11/2007 00:48:27 (Linux 2.4.21-32.ELsmp)
@(#)CDS: CTE v07.10-p003_1 (32bit) Oct 17 2007 14:48:07 (Linux 2.4.21-37.ELsmp)
--- Starting "First Encounter v07.10-p011_1" on Wed Jul 15 15:54:34 (mem=72.2M) ---
--- Running on samuel (x86_64 w/Linux 2.6.9-67.ELsmp) ---
This version was compiled on Mon Oct 29 17:15:25 PDT 2007.
Set DBUPerIGU to 1000.
Set Default Mode Capacitance Scale Factor to 1.00
Set Detail Mode Capacitance Scale Factor to 1.00
Set Coupling Capacitance Scale Factor to 1.00
Set Resistance Scale Factor to 1.00
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
<CMD> loadConfig /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.conf 0
Reading config file - /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.conf
<CMD> setUIVar rda_Input ui_gndnet gnd
<CMD> setUIVar rda_Input ui_pwrnet vdd
<CMD> commitConfig
Loading Lef file /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/libs/xc06_m3_FE.lef...
Loading Lef file /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/libs/D_CELLS.lef...
**WARN: (SOCLF-108): There is no overlap layer defined in any lef file
so you are unable to create rectilinear partition in a hierarchical flow.
Set DBUPerIGU to M2 pitch 2300.
Initializing default via types and wire widths ...
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
**ERROR: (SOCLF-53): The layer 'VIAL' is not found in the database.
A layer must be defined before it can be referenced.
Loading Lef file /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/libs/D_CELLSL.lef...
Loading Lef file /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/libs/IO_CELLS.lef...
**WARN: (SOCLF-200): Pin 'PAD' in macro 'APR00P' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'APR00P' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'APR01P' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'APR04P' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'APR15P' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC16P' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC16P' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC16SMP' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC16SMP' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC16SP' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC16SP' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC1P' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC1P' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC1SP' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC1SP' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC20P' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC20P' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC20SMP' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC20SMP' has no ANTENNAGATEAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
**WARN: (SOCLF-200): Pin 'PAD' in macro 'BBC20SP' has no ANTENNADIFFAREA attribute defined.
For any non-power/ground input or inout pin, The attribute should be
defined if any area ratio antenna attribute is defined on any layer.
 
Power Planner/ViaGen version 7.1.21 promoted on 09/14/2007.
viaInitial starts at Wed Jul 15 15:54:54 2009
viaInitial ends at Wed Jul 15 15:54:54 2009
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist '/home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.v'
 
*** Memory Usage v0.134.2.1 (Current mem = 195.113M, initial mem = 72.199M) ***
*** End netlist parsing (cpu=0:00:00.0, real=0:00:00.0, mem=195.1M) ***
Set top cell to t6507lp_io.
Reading common timing library '/home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/libs/D_CELLS_3_3V.lib' ...
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'SIG' of cell 'SIGNALHOLD' is not defined in the library
read 568 cells in library 'D_CELLS_3_3V'
ignored 1 cells in library 'D_CELLS_3_3V' because they are not defined in the LEF file, and they are not used in the verilog netlist.
Reading common timing library '/home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/libs/D_CELLSL_3_3V.lib' ...
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'SIG' of cell 'SIGNALHOLDL' is not defined in the library
read 306 cells in library 'D_CELLSL_3_3V'
ignored 1 cells in library 'D_CELLSL_3_3V' because they are not defined in the LEF file, and they are not used in the verilog netlist.
Reading common timing library '/home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/libs/IO_CELLS_33.lib' ...
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'PAD' of cell 'APR00P' is not defined in the library
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'Y' of cell 'APR01P' is not defined in the library
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'Y' of cell 'APR04P' is not defined in the library
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'Y' of cell 'APR15P' is not defined in the library
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'CLAMPC' of cell 'CLAMP' is not defined in the library
**WARN: (TECHLIB-436): Attribute 'max_capacitance' on output/inout pin 'CLAMPC' of cell 'CORNERCLMP' is not defined in the library
read 217 cells in library 'IO_CELLS_33'
*** End library_loading (cpu=0.23min, mem=39.7M, fe_cpu=0.31min, fe_mem=234.8M) ***
Starting recursive module instantiation check.
No recursion found.
*****NEW dbFlattenCell is used.
Flattening Cell t6507lp_io ...
*** Netlist is unique.
** info: there are 1207 modules.
** info: there are 1592 stdCell insts.
** info: there are 46 Pad insts.
** info: there are 3 multi-height stdCell insts (3 stdCells)
 
*** Memory Usage v0.134.2.1 (Current mem = 236.465M, initial mem = 72.199M) ***
CTE reading timing constraint file '/home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.sdc' ...
**ERROR: (TCLCMD-917): Cannot find 'library cells' that match 'D_CELLS_3_3V/CLKVBUF' (File /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.sdc, Line 29).
 
**ERROR: (TCLCMD-917): Cannot find 'modules, or cells' that match '' (File /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.sdc, Line 29).
 
**ERROR: (TCLCMD-917): Cannot find 'library cells' that match 'D_CELLSL_3_3V/CLKVBUFL' (File /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.sdc, Line 54).
 
**ERROR: (TCLCMD-917): Cannot find 'modules, or cells' that match '' (File /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.sdc, Line 54).
 
INFO (CTE): read_dc_script finished with 0 WARNING and 4 ERROR
WARNING (CTE-25): Line: 9, 10 of File /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.sdc : Skipped unsupported command: set_units
 
 
*** Read timing constraints (cpu=0:00:00.1 mem=237.8M) ***
Total number of combinational cells: 588
Total number of sequential cells: 236
Total number of tristate cells: 48
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
List of usable buffers: BULX1 BULX2 BULX3 BULX8 BULX4 BUCX3 BUCX4 BUCX8 BUX1 BUX2 BUX4 BUX3 BUX8
Total number of usable buffers: 13
List of unusable buffers: BUCLX16 BULX16
Total number of unusable buffers: 2
List of usable inverters: INCLX3 INCLX4 INCLX8 INLX1 INLX3 INLX2 INX1 INLX4 INLX8 INX3 INX2 INX4 INX8
Total number of usable inverters: 13
List of unusable inverters: INCLX16 INLX16
Total number of unusable inverters: 2
List of identified usable delay cells: BUCLX3 BUCLX4 BUCLX8 DLY2X1 DLY4X1 DLY8X1
Total number of identified usable delay cells: 6
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
*info: set bottom ioPad orient R0
Initializing I/O assignment ...
Adjusting Core to Left to: 0.1000. Core to Bottom to: 2.0000.
WARNING (SOCFP-0903): The height of site 'core' is not a multiple of single height row. Rows for this site are not created.
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
**WARN: (SOCDC-1159): Invalid input transition time. The default 0.1ps input transition time will be used.
Set Input Pin Transition Delay as 0.1 ps.
Reading Capacitance Table File /home/nscad/samuel/Desktop/svn_atari/trunk//syn/cadence/libs//xc06m3_typ.CapTbl ...
Cap Table was created using First Encounter 06.10-s054_1.
Process name: xc06m3_typ.
**WARN: (SOCEXT-2773): Unable to find a via resistance from LEF technology file;
**WARN: (SOCEXT-2774): Via resistance between layer POLY and M1 is assigned 4. Ohms.
**WARN: (SOCOPT-3465): The buffer cells were automatically identified. The command setBufFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0.
**WARN: (SOCOPT-3466): The inverter cells were automatically identified. The command setInvFootPrint is ignored. If you want to use this manual setting, rerun encounter with dbgGPSAutoCellFunction set to 0.
Set CTS cells: BUX1 BUX2 BUCX8 BUX3 BUX4 INCLX3 INCLX4 INLX8 INCLX8 INX1
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad0 is connected to non-p/g net n_30. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad1 is connected to non-p/g net n_29. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad10 is connected to non-p/g net n_18. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad11 is connected to non-p/g net n_17. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad12 is connected to non-p/g net n_16. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad2 is connected to non-p/g net n_28. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad3 is connected to non-p/g net n_27. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad4 is connected to non-p/g net n_25. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad5 is connected to non-p/g net n_24. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad6 is connected to non-p/g net n_23. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad7 is connected to non-p/g net n_22. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad8 is connected to non-p/g net n_21. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad9 is connected to non-p/g net n_19. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance clk_pad is connected to non-p/g net n_54. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad0 is connected to non-p/g net n_89. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad1 is connected to non-p/g net n_72. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad2 is connected to non-p/g net n_69. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad3 is connected to non-p/g net n_66. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad4 is connected to non-p/g net n_62. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad5 is connected to non-p/g net n_59. Mark the net as power net and create associated snet.
<CMD> fit
<CMD> setDrawView fplan
<CMD> loadIoFile /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/extras/iofile/t6507lp_absolute.io
<CMD> setDrawView place
<CMD> setDrawView fplan
<CMD> floorPlan -site core_l -r 2.14232581205 1 0.1 2.0 0.0 6.0
WARNING (SOCFP-0903): The height of site 'core' is not a multiple of single height row. Rows for this site are not created.
<CMD> setRoutingStyle -top -style m
<CMD> uiSetTool select
<CMD> fit
<CMD> floorPlan -site core_l -r 1.08982791242 0.330995 0.1 2.0 0.0 9.8
WARNING (SOCFP-0903): The height of site 'core' is not a multiple of single height row. Rows for this site are not created.
<CMD> setRoutingStyle -top -style m
<CMD> uiSetTool select
<CMD> fit
<CMD> loadIoFile /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/extras/iofile/t6507lp_absolute.io
<CMD> setDrawView place
<CMD> setDrawView fplan
<CMD> setDrawView ameba
<CMD> setDrawView place
<CMD> uiSetTool addPoly
<CMD> editAddPoly 755.789 1371.149
<CMD> editAddPoly 1109.842 1291.487
<CMD> editAddPoly 1092.139 1099.709
<CMD> editAddPoly 844.302 1146.916
<CMD> editAddPoly 879.708 1412.455
<CMD> uiSetTool addWire
**ERROR: **ERROR: (SOCSPR-55): <e> to open Edit Route form to input net name(s).
**ERROR: (SOCSPR-55): <e> to open Edit Route form to input net name(s).**ERROR: **ERROR: (SOCSPR-55): <e> to open Edit Route form to input net name(s).
**ERROR: (SOCSPR-55): <e> to open Edit Route form to input net name(s).<CMD> uiSetTool select
<CMD> verifyGeometry
*** Starting Verify Geometry (MEM: 241.4) ***
 
VERIFY GEOMETRY ...... Starting Verification
VERIFY GEOMETRY ...... Initializing
VERIFY GEOMETRY ...... Deleting Existing Violations
VERIFY GEOMETRY ...... Creating Sub-Areas
...... bin size: 10800
VERIFY GEOMETRY ...... SubArea : 1 of 1
VERIFY GEOMETRY ...... Cells : 4 Viols.
VERIFY GEOMETRY ...... SameNet : 10 Viols.
VERIFY GEOMETRY ...... Wiring : 0 Viols.
VERIFY GEOMETRY ...... Antenna : 0 Viols.
VERIFY GEOMETRY ...... Sub-Area : 1 complete 14 Viols. 0 Wrngs.
VG: elapsed time: 0.00
Begin Summary ...
Cells : 2
SameNet : 10
Wiring : 0
Antenna : 0
Short : 2
Overlap : 0
End Summary
 
Verification Complete : 14 Viols. 0 Wrngs.
 
**********End: VERIFY GEOMETRY**********
*** verify geometry (CPU: 0:00:00.1 MEM: 1.2M)
 
<CMD> setDrawView fplan
<CMD> setDrawView ameba
<CMD> setDrawView place
<CMD> resizeFP -ySize +1 -proportional
WARNING (SOCFP-0903): The height of site 'core' is not a multiple of single height row. Rows for this site are not created.
<CMD> fit
<CMD> verifyGeometry
*** Starting Verify Geometry (MEM: 242.5) ***
 
VERIFY GEOMETRY ...... Starting Verification
VERIFY GEOMETRY ...... Initializing
VERIFY GEOMETRY ...... Deleting Existing Violations
VERIFY GEOMETRY ...... Creating Sub-Areas
...... bin size: 10800
VERIFY GEOMETRY ...... SubArea : 1 of 1
VERIFY GEOMETRY ...... Cells : 0 Viols.
VERIFY GEOMETRY ...... SameNet : 0 Viols.
VERIFY GEOMETRY ...... Wiring : 0 Viols.
VERIFY GEOMETRY ...... Antenna : 0 Viols.
VERIFY GEOMETRY ...... Sub-Area : 1 complete 0 Viols. 0 Wrngs.
VG: elapsed time: 0.00
Begin Summary ...
Cells : 0
SameNet : 0
Wiring : 0
Antenna : 0
Short : 0
Overlap : 0
End Summary
 
Verification Complete : 0 Viols. 0 Wrngs.
 
**********End: VERIFY GEOMETRY**********
*** verify geometry (CPU: 0:00:00.1 MEM: 0.2M)
 
<CMD> saveFPlan /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/floorplan/t6507lp_io.fp
<CMD> setDrawView fplan
<CMD> addRing -spacing_bottom 1 -width_left 1.2 -width_bottom 1.2 -width_top 1.2 -spacing_top 1 -layer_bottom MET1 -stacked_via_top_layer MET3 -width_right 1.2 -around core -jog_distance 1.15 -offset_bottom 1.15 -layer_top MET1 -threshold 1.15 -offset_left 1.15 -spacing_right 1 -spacing_left 1 -offset_right 1.15 -offset_top 1.15 -layer_right MET2 -nets VDD5R -stacked_via_bottom_layer MET1 -layer_left MET2
 
**ERROR: (SOCPP-190): The Net 'VDD5R' does not exist in design.
**ERROR: Error: Invalid net names specified. <CMD> checkFPlan -outFile t6507lp_io.checkFPlan
Checking routing tracks.....
Checking other grids.....
Checking AreaIO row.....
Checking routing blockage.....
Checking components.....
Checking IO Pins.....
Unplaced Io Pins = 34
Floating/Unconnected IO Pins = 1
Checking constraints (guide/region/fence).....
Checking groups.....
 
Checking Ptn Pins .....
Checking Ptn Core Box.....
 
Checking Preroutes.....
No. of regular pre-routes not on tracks : 0
<CMD> setDrawView fplan
<CMD> checkFPlan -reportUtil -outFile t6507lp_io.checkFPlan
Checking routing tracks.....
Checking other grids.....
Checking AreaIO row.....
Checking routing blockage.....
Checking components.....
Checking IO Pins.....
Unplaced Io Pins = 34
Floating/Unconnected IO Pins = 1
Checking constraints (guide/region/fence).....
Checking groups.....
 
Checking Ptn Pins .....
Checking Ptn Core Box.....
 
Checking Preroutes.....
No. of regular pre-routes not on tracks : 0
Reporting Utilizations.....
 
Core utilization = 32.625702
Effective Utilizations
**WARN: (SOCSP-365): Design has inst(s) with SITE 'core', but no rows for the site.
Average module density = 0.326.
Density for the design = 0.326.
= stdcell_area 10039 (443328 um^2) / alloc_area 30807 (1360437 um^2).
Pin Density = 0.646.
= total # of pins 6489 / total Instant area 10039.
<CMD> setDrawView fplan
<CMD> verifyConnectivity -type all -error 1000 -warning 50
 
******** Start: VERIFY CONNECTIVITY ********
Start Time: Wed Jul 15 16:04:53 2009
 
Design Name: t6507lp_io
Database Units: 1000
Design Boundary: (0.0000, 0.0000) (1986.6000, 2082.4000)
Error Limit = 1000; Warning Limit = 50
Check all nets
Net vdd: no routing.
Net gnd: no routing.
 
Begin Summary
2 Problem(s) [ 98]: Net has no global routing and no special routing.
2 total info(s) created.
End Summary
 
End Time: Wed Jul 15 16:04:53 2009
******** End: VERIFY CONNECTIVITY ********
Verification Complete : 2 Viols. 0 Wrngs.
(CPU Time: 0:00:00.0 MEM: 0.000M)
 
<CMD> zoomOut
<CMD> zoomBox 364.554 2227.846 848.658 1808.682
<CMD> selectMarker 554.5000 1990.4000 639.5000 2075.4000 -1 3 18
<CMD> deselectAll
<CMD> selectInst vdd_pad_up
<CMD> clearDrc
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> deselectAll
<CMD> selectInst reset_n_pad
<CMD> deselectAll
<CMD> selectInst clk_pad
<CMD> deselectAll
<CMD> selectInst vdd_pad_up
<CMD> deselectAll
<CMD> addRing -spacing_bottom 1 -width_left 1.2 -width_bottom 1.2 -width_top 1.2 -spacing_top 1 -layer_bottom MET1 -stacked_via_top_layer MET3 -width_right 1.2 -around core -jog_distance 1.15 -offset_bottom 1.15 -layer_top MET1 -threshold 1.15 -offset_left 1.15 -spacing_right 1 -spacing_left 1 -offset_right 1.15 -offset_top 1.15 -layer_right MET2 -nets vdd -stacked_via_bottom_layer MET1 -layer_left MET2
 
 
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1557.00, 429.60) (1557.15, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1195.30, 429.60) (1205.30, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1195.30, 429.60) (1206.60, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1183.70, 429.60) (1205.20, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1183.70, 429.60) (1206.60, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1171.30, 429.60) (1178.40, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1171.30, 429.60) (1179.50, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1166.70, 429.60) (1167.10, 429.65)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1180.30, 429.65) (1182.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1167.90, 429.65) (1170.50, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1163.30, 429.65) (1165.90, 430.00)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1097.40, 429.60) (1161.40, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1097.40, 429.60) (1162.50, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1097.40, 429.60) (1108.70, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1097.40, 429.60) (1107.40, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1306.30, 429.60) (1316.30, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1306.30, 429.60) (1317.60, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1294.70, 429.60) (1316.20, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1294.70, 429.60) (1317.60, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1282.30, 429.60) (1289.40, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1282.30, 429.60) (1290.50, 429.65)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1277.70, 429.60) (1278.10, 429.65)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1291.30, 429.65) (1293.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1278.90, 429.65) (1281.50, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1274.30, 429.65) (1276.90, 430.00)
**WARN: (SOCPP-573): The power planner detects a potential spacing violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1208.40, 429.60) (1272.40, 429.65)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1394.00, 429.65) (1408.00, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1376.00, 429.65) (1390.00, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1358.00, 429.65) (1372.00, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (1340.00, 429.65) (1354.00, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (514.30, 429.65) (516.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (501.90, 429.65) (504.50, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (497.30, 429.65) (499.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (625.30, 429.65) (627.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (612.90, 429.65) (615.50, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (608.30, 429.65) (610.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (736.30, 429.65) (738.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (723.90, 429.65) (726.50, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (719.30, 429.65) (721.90, 430.00)
**WARN: (SOCPP-572): The power planner detects a potential short violation. Run verifyGeometry to ensure DRC clean.
layer MET1, area (847.30, 429.65) (849.90, 430.00)
 
The power planner created 56 wires.
**WARN: (SOCPP-582): 155 wires violate design rules.
 
<CMD> setDrawView place
<CMD> zoomBox 149.697 1718.492 1962.823 345.352
<CMD> zoomBox 339.838 561.097 575.250 361.903
<CMD> zoomBox 417.721 438.576 455.928 422.999
<CMD> selectWire 427.7500 429.6500 1557.1500 430.8500 1 vdd
<CMD> zoomOut
<CMD> deselectAll
<CMD> selectWire 427.7500 451.7500 428.9500 466.2500 2 vdd
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> deselectAll
<CMD> fit
<CMD> verifyGeometry
*** Starting Verify Geometry (MEM: 245.5) ***
 
VERIFY GEOMETRY ...... Starting Verification
VERIFY GEOMETRY ...... Initializing
VERIFY GEOMETRY ...... Deleting Existing Violations
VERIFY GEOMETRY ...... Creating Sub-Areas
...... bin size: 10800
VERIFY GEOMETRY ...... SubArea : 1 of 1
VERIFY GEOMETRY ...... Cells : 0 Viols.
VERIFY GEOMETRY ...... SameNet : 48 Viols.
VERIFY GEOMETRY ...... Wiring : 30 Viols.
VERIFY GEOMETRY ...... Antenna : 0 Viols.
VERIFY GEOMETRY ...... Sub-Area : 1 complete 78 Viols. 0 Wrngs.
VG: elapsed time: 0.00
Begin Summary ...
Cells : 0
SameNet : 48
Wiring : 2
Antenna : 0
Short : 28
Overlap : 0
End Summary
 
Verification Complete : 78 Viols. 0 Wrngs.
 
**********End: VERIFY GEOMETRY**********
*** verify geometry (CPU: 0:00:00.1 MEM: 2.4M)
 
<CMD> selectInst data_in_pad0
<CMD> zoomBox 377.838 542.336 584.468 338.658
<CMD> deselectAll
<CMD> zoomBox 455.037 440.235 526.167 421.862
<CMD> zoomBox 496.863 431.670 506.275 424.832
<CMD> selectInst data_in_pad0
<CMD> deselectAll
<CMD> selectMarker 497.3000 429.6500 499.9000 430.0000 1 1 6
<CMD> zoomOut
<CMD> zoomOut
<CMD> deselectAll
<CMD> zoomBox 425.970 432.716 430.247 429.238
<CMD> selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1
<CMD> deselectAll
<CMD> selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1
<CMD> deselectAll
<CMD> selectWire 427.7500 429.6500 1557.1500 430.8500 1 vdd
<CMD> deselectAll
<CMD> selectMarker 427.7500 430.8500 429.6000 431.4000 1 1 2
<CMD> deselectAll
<CMD> selectMarker 427.7500 429.6000 428.9500 429.6500 2 1 2
<CMD> deselectAll
<CMD> selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1
<CMD> deselectAll
<CMD> selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1
<CMD> deselectAll
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomBox 86.331 1781.665 2104.163 152.088
<CMD> zoomBox 411.300 1679.793 1612.930 1591.623
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomBox -338.031 1335.676 1942.216 279.561
<CMD> zoomBox 453.366 443.234 1606.299 372.065
<CMD> zoomBox 785.860 465.224 876.540 381.741
<CMD> zoomBox 831.936 430.161 839.634 424.388
<CMD> selectMarker 833.7000 429.6000 834.1000 429.6500 1 1 2
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> deselectAll
<CMD> undo
<CMD> setDrawView ameba
<CMD> setDrawView fplan
<CMD> setDrawView place
<CMD> zoomBox 474.096 1750.997 646.327 1573.844
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> zoomOut
<CMD> verifyGeometry
*** Starting Verify Geometry (MEM: 251.2) ***
 
VERIFY GEOMETRY ...... Starting Verification
VERIFY GEOMETRY ...... Initializing
VERIFY GEOMETRY ...... Deleting Existing Violations
VERIFY GEOMETRY ...... Creating Sub-Areas
...... bin size: 10800
VERIFY GEOMETRY ...... SubArea : 1 of 1
VERIFY GEOMETRY ...... Cells : 0 Viols.
VERIFY GEOMETRY ...... SameNet : 0 Viols.
VERIFY GEOMETRY ...... Wiring : 0 Viols.
VERIFY GEOMETRY ...... Antenna : 0 Viols.
VERIFY GEOMETRY ...... Sub-Area : 1 complete 0 Viols. 0 Wrngs.
VG: elapsed time: 0.00
Begin Summary ...
Cells : 0
SameNet : 0
Wiring : 0
Antenna : 0
Short : 0
Overlap : 0
End Summary
 
Verification Complete : 0 Viols. 0 Wrngs.
 
**********End: VERIFY GEOMETRY**********
*** verify geometry (CPU: 0:00:00.1 MEM: 0.0M)
 
<CMD> zoomOut
<CMD> mp::checkFence -clear
<CMD> setPlanDesignMode -powerAware -createFence -useExistingPowerRail
**WARN: (SOCTCM-70): Option "-powerAware" for command setPlanDesignMode is obsolete and has been replaced by "-powerAware true". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use -powerAware true.
**WARN: (SOCTCM-70): Option "-useExistingPowerRail" for command setPlanDesignMode is obsolete and has been replaced by "-useExistingPowerRail true". The obsolete option still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your script to use -useExistingPowerRail true.
<CMD> planDesign
Check pre-placed instances....
Design Statistics :
Fixed StdCells: 0, Fixed HMs: 0, IO Cells: 46
*** Starting automatic seed selection ...
*** Done seed selection (HIER), (cpu = 0:00:00.0, mem = 251.3M, mem_delta = 0.0M) ***
*** Starting netlist partitioning ...
==== USING NEW MAKESEED ====
Detect 0 HInst fences.
Total 46 preplaced instances.
Total 0 non-fix I/O instances.
Total 1592 non-placed instances.
Total 834 seed instances (1 seeds).
Total 758 instances sorted into 1 bins.
bin[0]: 758 instances (area=5332.0).
==== Seed Area ====
Seed: 4719
Medium seed area: 0
Total Seed Area 4719, Non-seed Area 5332, Total 10051
Target Area = 280.63
Partition Bin 0 (758 inst) (area 5332.0) ...
Group 0: 18 instances 165.
Group 1: 26 instances 164.
Group 2: 14 instances 153.
Group 3: 18 instances 170.
Group 4: 18 instances 177.
Group 5: 37 instances 153.
Group 6: 45 instances 168.
Group 7: 35 instances 182.
Group 8: 28 instances 174.
Group 9: 32 instances 151.
Group 10: 31 instances 159.
Group 11: 35 instances 176.
Group 12: 32 instances 177.
Group 13: 35 instances 161.
Group 14: 34 instances 158.
Group 15: 29 instances 179.
Group 16: 20 instances 164.
Group 17: 14 instances 169.
Group 18: 15 instances 162.
Group 19: 18 instances 171.
Group 20: 14 instances 166.
Group 21: 19 instances 167.
Group 22: 21 instances 177.
Group 23: 16 instances 159.
Group 24: 19 instances 161.
Group 25: 23 instances 175.
Group 26: 27 instances 150.
Group 27: 17 instances 175.
Group 28: 18 instances 175.
Group 29: 13 instances 145.
Group 30: 19 instances 173.
Group 31: 18 instances 176.
*** Done Clustering, (cpu = 0:00:00.0, mem = 251.5M, mem_delta = 0.0M) ***
Make seed create 32 instance group seeds
*** End netlist partitioning (cpu=0:00:00.0) ***
*** Done seed selection (PART), (cpu = 0:00:00.0, mem = 251.5M, mem_delta = 0.3M) ***
*** Done automatic seed selection, (cpu = 0:00:00.0, mem = 251.5M, mem_delta = 0.3M) ***
****** Masterplan Data Statistics for Design Cell Instances ******
Hardmacros : 0 (Fixed : 0)
Considered Standard Cell Instances : 1638 (Fixed IO : 46 and Fixed non-IO : 0)
Free HM and Free non-IO Standard Cell Intances : 1592
Standard Cell Instances Ignored by MP : 0 (Physical Instances : 0)
 
MP Seeds Statistics:
HM Seeds : 0
Instance Seeds : 46
HInst Seeds : 1
Group Seeds : 32
*** Done Seed Creation, (cpu = 0:00:00.0, mem = 251.5M, mem_delta = 0.0M) ***
Total free seeds = 33
*** Done initial seed placement, (cpu = 0:00:00.0, mem = 251.5M, mem_delta = 0.0M) ***
refineSeed command options :
minAspectRatio= 0.20, maxAspectRatio= 5.00, seedUtilMargin= 0.15
*** Start guide refinement (mem=251.5M)
Set top-level seed density to 8.000000
 
..............................................................
..............................................................
..............................................................
..............................................................
..............................................................
......
Set top-level seed density to 4.000000
 
..............................................................
..............................................................
..............................................................
.....................
.........................................
..............................................................
..............................................................
.........................................................................................
Set top-level seed density to 2.000000
 
..............................................................
..............................................................
..............................................................
..............................................................
............................
Set top-level seed density to 1.330000
 
..............................................................
..............................................................
..............................................................
..............................................................
..............................................................
..............................................................
..........................................................................
Set top-level seed density to 1.000000
 
..............................................................
..............................................................
..............................................................
..............................................................
..................
Set top-level seed density to 0.830000
 
..............................................................
..............................................................
...........................................................
...
..............................................................
..............................................................
..............................................................
.................................................................
Set top-level seed density to 0.660000
 
..............................................................
..............................................................
..............................................................
..............................................................
..............................................................
...........
Set top-level seed density to 0.475082
 
..............................................................
..............................................................
..............................................................
.............................................
.................
..............................................................
..............................................................
................................................................................................................................
Create guide for HInst t6507lp/t6507lp_alu at (839174, 549415, 1458813, 1256658)
Create guide for Group PartInstGrp_0 at (815730, 1261651, 995878, 1346787)
Create guide for Group PartInstGrp_1 at (591323, 1123845, 831317, 1187364)
Create guide for Group PartInstGrp_2 at (587857, 1188389, 834783, 1245984)
Create guide for Group PartInstGrp_3 at (611348, 1042733, 811293, 1121764)
Create guide for Group PartInstGrp_4 at (610262, 756567, 691918, 958053)
Create guide for Group PartInstGrp_5 at (1394594, 1325086, 1451689, 1574173)
Create guide for Group PartInstGrp_6 at (1126530, 1419203, 1378909, 1481078)
Create guide for Group PartInstGrp_7 at (1139010, 1512947, 1330388, 1601344)
Create guide for Group PartInstGrp_8 at (685254, 1541963, 883857, 1623400)
Create guide for Group PartInstGrp_9 at (652097, 1493704, 917013, 1546686)
Create guide for Group PartInstGrp_10 at (530622, 1377038, 799439, 1431153)
Create guide for Group PartInstGrp_11 at (551105, 1432080, 797681, 1498427)
Create guide for Group PartInstGrp_12 at (1234299, 1285789, 1375049, 1399379)
Create guide for Group PartInstGrp_13 at (1001016, 1349580, 1224943, 1416411)
Create guide for Group PartInstGrp_14 at (810881, 1349500, 994769, 1429366)
Create guide for Group PartInstGrp_15 at (833931, 1433301, 1094293, 1497206)
Create guide for Group PartInstGrp_16 at (594266, 1247008, 804931, 1319370)
Create guide for Group PartInstGrp_17 at (1006444, 1266333, 1209025, 1343877)
Create guide for Group PartInstGrp_18 at (530275, 1321225, 804635, 1376110)
Create guide for Group PartInstGrp_19 at (523504, 1019761, 583466, 1284843)
Create guide for Group PartInstGrp_20 at (613522, 963617, 823306, 1037169)
Create guide for Group PartInstGrp_21 at (434425, 868915, 519180, 1052066)
Create guide for Group PartInstGrp_22 at (534539, 720850, 597654, 981525)
Create guide for Group PartInstGrp_23 at (695200, 757526, 770057, 954960)
Create guide for Group PartInstGrp_24 at (773339, 647022, 832870, 898407)
Create guide for Group PartInstGrp_25 at (1063867, 451200, 1230073, 549070)
Create guide for Group PartInstGrp_26 at (604610, 666672, 766382, 752860)
Create guide for Group PartInstGrp_27 at (546708, 451200, 807320, 513617)
Create guide for Group PartInstGrp_28 at (1467374, 1023246, 1548038, 1224905)
Create guide for Group PartInstGrp_29 at (1468876, 640848, 1546537, 814398)
Create guide for Group PartInstGrp_30 at (537793, 589508, 756706, 662965)
Create guide for Group PartInstGrp_31 at (563620, 509675, 790408, 581811)
 
*** Successfully refining guides (cpu = 0:00:03.4, mem = 251.5M, mem_delta = 0.0M) ***
*** Generate new data for Block Placer. ***
*** Done Block Placer data generation, (cpu = 0:00:00.0, mem = 251.5M, mem_delta = 0.0M) ***
MacroPlacer: Reading Data for Block Placer
MacroPlacer: total number of seeds contain macros: 0
MacroPlacer: total number of macros: 0
MacroPlacer: total number of clusters: 0
MacroPlacer: total number of ios: 46
MacroPlacer: total number of nets: 0
MacroPlacer: total number of keepouts: 0
MacroPlacer: total number of fences: 0
MacroPlacer: total number of fixed macros: 0
MacroPlacer: 0 2-pins nets
MacroPlacer: 0 3-pins nets
MacroPlacer: 0 4-pins nets
MacroPlacer: 0 5-pins nets
MacroPlacer: Merging nets.
MacroPlacer: total number of merged nets: 0
MacroPlacer: Finished data reading for Block Placer
MacroPlacer: Start Packing Blocks
MacroPlacer: Finished Placing Block Packs
MacroPlacer: Start Refine Block Placement.
MacroPlacer: Finished Refine Block Placement.
MacroPlacer: Start final alignment.
MacroPlacer: End final alignment.
MacroPlacer: Start final net length optimize.
MacroPlacer: Finished final net length optimize.
MacroPlacer: weightedSeedWireLength: 0
MacroPlacer: Design has no overlapping PLACED macro.
MacroPlacer: Macro Placer completes.
*** Done Block Placer, (cpu = 0:00:00.1, mem = 277.0M, mem_delta = 25.4M) ***
-ird mode
The toggle probability ( 0.2 ) is used for power estimation.
Estimated totalPower: 0.240082 mW
Estimated Switching Power: 0.103937 mW
Estimated Internal Power : 0.136144 mW
Estimated Leakage Power : 1.17636e-07 mW
*** Done Power Estimation, (cpu = 0:00:00.0, mem = 277.1M, mem_delta = 0.1M) ***
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_4' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_5' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_6' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_3' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_49' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_14' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_11' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_20' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_15' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_12' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_8' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_9' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_10' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_7' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_0' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_1' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_31' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_34' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_36' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
**ERROR: (SOCDB-1221): A global net connection rule for connecting P/G pins of the pattern 'n_38' was specified. But the connections cannot be made because there is no such pin in any cell. Check the pin name pattern and make sure it is correct.
License check succeded.
 
**WARN: (SOCAPP-999): Command synthesizePowerPlan is obsolete. Use addRing command and/or addStripe command to create power structures. The obsolete command still works in this release, but to avoid this warning and to ensure compatibility with future releases, update your scripts to use addRing command and/or addStripe command.
Maximum total current that can be supplied by power pads is 2.4800e+01 mA.
*** Done Synthesizing Power Plan, (cpu = 0:00:00.0, mem = 277.4M, mem_delta = 0.3M) ***
Master Plan fast floor plan placer ...
fastPlace clustering ...
Creating directory mp_data/soce_clu.
*** Starting netlist clustering ...
cluRatio = 30
Minimum Cluster Cell Area = 4, Maximum Cluster Cell Area = 454, # Cluster Cell = 90.
 
Generating clustered netlist (#insts = 126, #nets = 1004, #terms = 2695)
Average cluster size = 12.63
spCheckDesign
Checking IO
Checking Inst
Checking Net
Checking SNet
Checking BNet
Checking Tree Inst
Checking Tree HInst
Checking Tree Net
*** End netlistClustering (cpu=0:00:00.1, mem=277.4M, mem_delta=0.1M) ***
ModulePlan placer activated
**WARN: (SOCDB-2082): Scan chains were not defined, -ignoreScan option will be ignored.
Please first define the scan chains before using this option.
**WARN: (SOCSP-365): Design has inst(s) with SITE 'core', but no rows for the site.
Iteration 1: Total net bbox = 4.311e+04 (2.11e+04 2.20e+04)
Est. stn bbox = 4.311e+04 (2.11e+04 2.20e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 278.1M
Iteration 2: Total net bbox = 4.311e+04 (2.11e+04 2.20e+04)
Est. stn bbox = 4.311e+04 (2.11e+04 2.20e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 278.1M
Iteration 3: Total net bbox = 5.918e+04 (3.11e+04 2.80e+04)
Est. stn bbox = 5.918e+04 (3.11e+04 2.80e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 278.1M
Iteration 4: Total net bbox = 1.588e+05 (9.88e+04 6.00e+04)
Est. stn bbox = 1.588e+05 (9.88e+04 6.00e+04)
cpu = 0:00:00.1 real = 0:00:00.0 mem = 278.1M
Iteration 5: Total net bbox = 2.415e+05 (1.39e+05 1.02e+05)
Est. stn bbox = 2.415e+05 (1.39e+05 1.02e+05)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 278.1M
*** cluster place finished (cpu=0:00:00.4, mem=278.1M, mem_delta=0.7M) ***
*** Done fastPlace, (cpu = 0:00:00.5, mem = 278.1M, mem_delta = 0.7M) ***
*** Starting netlist unclustering ...
Starting recursive module instantiation check.
No recursion found.
*****NEW dbFlattenCell is used.
Flattening Cell t6507lp_io ...
*** Netlist is unique.
** info: there are 1207 modules.
** info: there are 1592 stdCell insts.
** info: there are 46 Pad insts.
** info: there are 3 multi-height stdCell insts (3 stdCells)
 
*** Memory Usage v0.134.2.1 (Current mem = 277.773M, initial mem = 72.199M) ***
Reading floorplan file - mp_data/soce_clu/t6507lp_io.clu.fp (mem = 277.8M).
**WARN: (SOCDB-1256): Power pin VDD5O of instance address_pad0 is connected to non-p/g net vdd. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad0 is connected to non-p/g net n_30. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1257): Ground pin GND5O of instance address_pad0 is connected to non-p/g net gnd. Mark the net as ground net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad1 is connected to non-p/g net n_29. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad10 is connected to non-p/g net n_18. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad11 is connected to non-p/g net n_17. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad12 is connected to non-p/g net n_16. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad2 is connected to non-p/g net n_28. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad3 is connected to non-p/g net n_27. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad4 is connected to non-p/g net n_25. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad5 is connected to non-p/g net n_24. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad6 is connected to non-p/g net n_23. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad7 is connected to non-p/g net n_22. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad8 is connected to non-p/g net n_21. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance address_pad9 is connected to non-p/g net n_19. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance clk_pad is connected to non-p/g net n_54. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad0 is connected to non-p/g net n_89. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad1 is connected to non-p/g net n_72. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad2 is connected to non-p/g net n_69. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad3 is connected to non-p/g net n_66. Mark the net as power net and create associated snet.
**WARN: (SOCDB-1256): Power pin CLAMPC of instance data_in_pad4 is connected to non-p/g net n_62. Mark the net as power net and create associated snet.
Set FPlanBox to (0 0 1986600 2082400)
WARNING (SOCFP-0903): The height of site 'core' is not a multiple of single height row. Rows for this site are not created.
Set (t6507lp/t6507lp_alu) in guide (837200 547200 1460500 1257600)
There are 46 io inst loaded
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
*** End loading floorplan (cpu = 0:00:00.1, mem = 278.2M) ***
**WARN: (SOCSP-365): Design has inst(s) with SITE 'core', but no rows for the site.
*** End netlist unclustering ***
spCheckDesign
Checking IO
Checking Inst
Checking Net
Checking SNet
Checking BNet
Checking Tree Inst
Checking Tree HInst
Checking Tree Net
*** End netlistUnclustering (cpu=0:00:00.1, mem=278.2M, mem_delta=0.0M) ***
congEst:Reload congestion map.
cannot open display in mp_data/
*** BoxPlacer ***
BoxPlacer: optimizing wire length...........
BoxPlacer: spread placement ...
*** End Box Place (cpu=0:00:00.0, mem=278.2M, mem_delta=0.1M) ***
*** BoxPlacer ***
BoxPlacer: optimizing wire length...........
BoxPlacer: spread placement .....
*** End Box Place (cpu=0:00:00.0, mem=278.2M, mem_delta=0.0M) ***
*** BoxPlacer ***
BoxPlacer: optimizing wire length...........
BoxPlacer: spread placement ....
*** End Box Place (cpu=0:00:00.0, mem=278.2M, mem_delta=0.0M) ***
*** Done snapFPlan, (cpu = 0:00:00.0, mem = 278.2M, mem_delta = 0.0M) ***
*** fastPlace finished, so far total mp::runCongAware cpu=0:00:00.6 ***
CTE reading timing constraint file '/home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.sdc' ...
*** Read timing constraints (cpu=0:00:00.0 mem=278.7M) ***
**ERROR: (SOCPARA-267): Invalid expected power.
Usage: updatePower {-vcd <vcdFileName> ]-vcdTop <VCDTopName>]
[-start <time>] [-end <time>]
[-timeUnit <unit>] [-noTop] | -preCTS
-toggleFile <toggleFileName>
[-expectedPower <power>] | -postCTS
-toggleFile <toggleFileName>
[-expectedPower <power>] | -toggleProb
<probability> -clockRate <clockrate>
[-expectedPower <power>]
| -estimate <filename>} | -totalPower
<value> ]-readInstancePower <fileName>]{-noRailAnalysis
| -pad <padFileList>}[-temperature
<degreesCelsius>] [-mode {floorplan
| layout}] [-irDropAnalysis {average
| peak}] [-report <fileName>] [-reportInstanceVoltage
<fileName>] [-reportInstancePower
<fileName>] [-reportRailAnalysis
<fileName>] [-reportNetPower <fileName>]
[-biasVoltage <volts>] [-isSignal]
[-reportDCSourceCurrent <fileName>]
[-reportUnclockedInstances <fileName>]
[-readBlockPinCurrent <fileName>]
[-readCellPower <cellPowerFileName>]
[-readPackageModel <packageModelFile>]
[-readPackageTerminalMapping <packageTerminalMappingFile>]
[-readPadResistance <padResistanceFile>]
[-readPwrGatingCell <powerGatingFile>]
[-group <netsList>] [-tcf <tcfFileName>]
[-preCTS | -postCTS | -clockRate
<clockrate> | -toggleProb <prob>]
<powerNetNames> ]-extend]
 
**ERROR: (SOCSYC-194): Incorrect usage for command 'updatePower'.
**ERROR: (SOCPARA-116): Net vdd has not been analyzed.
/trunk/syn/cadence/extras/iofile/t6507lp_io.geom.rpt
0,0 → 1,1109
Verify Geometry report created on Tue Jul 28 14:22:49 2009
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1643.400 ) ( 848.700, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1678.300 ) ( 845.400, 1744.300 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 765.500, 1643.200 ) ( 843.600, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 808.750, 1640.400 ) ( 831.850, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.700, 1679.100 ) ( 845.200, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.700, 1640.500 ) ( 844.450, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.700, 1640.500 ) ( 843.600, 2070.000 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 804.500, 1640.400 ) ( 869.600, 1977.200 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 788.700, 1643.200 ) ( 864.500, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 805.250, 1640.400 ) ( 866.300, 2069.600 )
 
 
OVERLAP: Cell filler1 & Cell address_pad12
Bounds : ( 784.800, 1640.000 ) ( 849.100, 2070.000 )
 
 
OVERLAP: Cell reset_n_pad & Cell address_pad12
Bounds : ( 760.000, 1640.000 ) ( 849.100, 2070.000 )
 
 
OVERLAP: Cell reset_n_pad & Cell filler1
Bounds : ( 784.800, 1640.000 ) ( 870.000, 2070.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1679.100 ) ( 763.100, 1743.500 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1679.100 ) ( 764.700, 1743.500 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1679.100 ) ( 743.800, 1743.500 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1679.100 ) ( 742.200, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1679.100 ) ( 787.900, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1679.100 ) ( 787.900, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 785.200, 1643.200 ) ( 804.250, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1643.150 ) ( 783.550, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 785.200, 1640.400 ) ( 803.800, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1640.400 ) ( 783.300, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 739.500, 1640.400 ) ( 759.600, 1977.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 748.300, 1640.400 ) ( 750.800, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 743.000, 1640.400 ) ( 756.300, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 788.250, 1640.400 ) ( 794.950, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 788.700, 1640.400 ) ( 803.050, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 765.500, 1640.400 ) ( 782.550, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1640.400 ) ( 782.550, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 744.600, 1640.400 ) ( 754.500, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.800, 1679.100 ) ( 756.100, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.800, 1640.500 ) ( 754.500, 2070.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.800, 1640.500 ) ( 755.350, 2069.500 )
 
 
OVERLAP: Cell clk_pad & Cell address_pad12
Bounds : ( 739.100, 1640.000 ) ( 760.000, 2070.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1679.100 ) ( 849.100, 1743.500 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1679.100 ) ( 849.100, 1743.500 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1679.100 ) ( 873.100, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1679.100 ) ( 894.800, 1743.500 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1679.100 ) ( 894.800, 1743.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 837.400, 1640.400 ) ( 848.700, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 837.550, 1640.400 ) ( 843.600, 2070.000 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M1 )
Bounds : ( 870.400, 1640.400 ) ( 894.400, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 858.300, 1640.400 ) ( 869.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 873.900, 1640.400 ) ( 891.100, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1679.100 ) ( 890.900, 1743.500 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.850, 1640.500 ) ( 890.150, 2069.500 )
 
 
OVERLAP: Cell filler0 & Cell filler1
Bounds : ( 870.000, 1640.000 ) ( 894.800, 2070.000 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1679.100 ) ( 1200.000, 1743.500 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.650, 1679.100 ) ( 1200.000, 1743.500 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1679.100 ) ( 1196.100, 1743.500 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1679.100 ) ( 1195.050, 1743.500 )
 
 
SPACING: Pin of Cell address_pad11 & Pin of Cell address_pad10 ( M3 )
Bounds : ( 1196.650, 1679.100 ) ( 1197.100, 1743.500 )
Actual: 0.45 Min: 1 SameNetGap
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M1 )
Bounds : ( 1192.350, 1640.400 ) ( 1199.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1195.850, 1640.400 ) ( 1196.300, 2069.600 )
 
 
OVERLAP: Cell address_pad10 & Cell address_pad11
Bounds : ( 1191.950, 1640.000 ) ( 1200.000, 2070.000 )
 
 
SPACING: Blockage of Cell vdd_pad_left & Pin of Cell left_down_pad ( M1 )
Bounds : ( 427.400, 430.000 ) ( 429.600, 430.400 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell left_down_pad & Blockage of Cell data_in_pad0 ( M1 )
Bounds : ( 430.000, 427.400 ) ( 430.400, 429.600 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell left_down_pad & Blockage of Cell data_in_pad0 ( M1 )
Bounds : ( 430.000, 426.900 ) ( 430.400, 427.400 )
Actual: 0.64 Min: 0.8
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1643.200 ) ( 845.400, 1677.900 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1677.900 ) ( 848.700, 1678.300 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 760.500, 1640.500 ) ( 848.600, 1641.450 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1643.200 ) ( 845.200, 1677.100 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.850, 1640.500 ) ( 844.450, 1678.100 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 805.250, 1640.400 ) ( 869.600, 1642.400 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M1 )
Bounds : ( 784.100, 1640.400 ) ( 786.700, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1643.200 ) ( 763.100, 1677.100 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1643.200 ) ( 763.100, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1643.200 ) ( 742.200, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1643.200 ) ( 742.200, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 804.600, 1640.400 ) ( 807.200, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M1 )
Bounds : ( 801.100, 1640.400 ) ( 803.700, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M1 )
Bounds : ( 796.500, 1640.400 ) ( 799.100, 1642.600 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1643.200 ) ( 787.900, 1677.100 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1643.200 ) ( 787.900, 1677.100 )
 
 
SPACING: Blockage of Cell rw_mem_pad & Pin of Cell left_up_pad ( M1 )
Bounds : ( 426.850, 1639.600 ) ( 427.400, 1640.000 )
Actual: 0.68 Min: 0.8
 
SPACING: Blockage of Cell rw_mem_pad & Pin of Cell left_up_pad ( M1 )
Bounds : ( 427.400, 1639.600 ) ( 429.600, 1640.000 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell left_up_pad & Blockage of Cell gnd_pad_up ( M1 )
Bounds : ( 430.000, 1640.400 ) ( 430.400, 1642.600 )
Actual: 0.4 Min: 0.8
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1677.900 ) ( 759.600, 1678.300 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1640.400 ) ( 759.600, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 785.200, 1640.400 ) ( 803.050, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1640.400 ) ( 782.550, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.600, 1640.500 ) ( 759.500, 1641.450 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1643.200 ) ( 756.100, 1677.100 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.950, 1640.500 ) ( 755.350, 1678.100 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1643.200 ) ( 1200.000, 1677.100 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1643.200 ) ( 1200.000, 1677.100 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1643.200 ) ( 1195.050, 1677.100 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1643.200 ) ( 1195.050, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1643.200 ) ( 849.100, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1643.200 ) ( 849.100, 1677.100 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M1 )
Bounds : ( 833.400, 1640.400 ) ( 836.000, 1642.600 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1643.200 ) ( 873.100, 1677.100 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1643.200 ) ( 894.800, 1677.100 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1643.200 ) ( 894.800, 1677.100 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1677.900 ) ( 1199.600, 1678.300 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1640.400 ) ( 1199.600, 1642.400 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1192.450, 1640.500 ) ( 1199.500, 1641.450 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1643.200 ) ( 1196.100, 1677.100 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1677.900 ) ( 894.400, 1678.300 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1640.400 ) ( 894.400, 1642.400 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 870.500, 1640.500 ) ( 894.300, 1641.450 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1643.200 ) ( 890.900, 1677.100 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1374.450 ) ( 1550.750, 1388.450 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1971.350, 1353.850 ) ( 1975.550, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1551.550, 1353.850 ) ( 1884.750, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1688.150, 1357.150 ) ( 1868.350, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1652.250, 1357.150 ) ( 1687.750, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1585.850, 1357.150 ) ( 1651.850, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1357.150 ) ( 1585.450, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1868.350, 1353.850 ) ( 1977.150, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1687.750, 1353.850 ) ( 1688.150, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1651.850, 1353.850 ) ( 1652.250, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1585.450, 1353.850 ) ( 1585.850, 1419.600 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1358.950 ) ( 1977.550, 1414.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1358.950 ) ( 1977.150, 1416.100 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1869.300, 1353.950 ) ( 1977.050, 1419.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1353.950 ) ( 1549.000, 1419.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1783.850, 1357.350 ) ( 1867.550, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1779.750, 1357.350 ) ( 1782.350, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1688.950, 1357.350 ) ( 1778.250, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1653.050, 1357.350 ) ( 1686.950, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1586.650, 1357.350 ) ( 1651.050, 1414.300 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1550.750, 1357.350 ) ( 1584.650, 1415.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1652.050, 1358.100 ) ( 1977.050, 1415.150 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1358.100 ) ( 1977.050, 1414.300 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1358.100 ) ( 1585.650, 1415.150 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1652.050, 1358.950 ) ( 1977.550, 1414.500 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1548.050, 1358.950 ) ( 1977.550, 1414.300 )
 
 
SHORT: Pin of Cell gnd_pad_right & Pin of Cell address_pad8 ( M1 )
Bounds : ( 1885.550, 1365.950 ) ( 1970.550, 1407.500 )
 
 
OVERLAP: Cell address_pad8 & Cell gnd_pad_right
Bounds : ( 1547.550, 1353.450 ) ( 1977.550, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M1 )
Bounds : ( 1885.550, 1353.850 ) ( 1970.550, 1365.150 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M1 )
Bounds : ( 1547.950, 1353.850 ) ( 1550.150, 1354.500 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1653.050, 1353.450 ) ( 1686.950, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1550.750, 1353.450 ) ( 1584.650, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1653.050, 1353.450 ) ( 1686.950, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1550.750, 1353.450 ) ( 1584.650, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1688.950, 1353.450 ) ( 1778.250, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1688.950, 1353.450 ) ( 1778.250, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1783.850, 1353.450 ) ( 1867.550, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1586.650, 1353.450 ) ( 1651.050, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1783.850, 1353.450 ) ( 1867.550, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1586.650, 1353.450 ) ( 1651.050, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1779.750, 1353.450 ) ( 1782.350, 1356.350 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M3 )
Bounds : ( 1779.750, 1353.450 ) ( 1782.350, 1356.350 )
 
 
SPACING: Pin of Cell right_down_pad & Blockage of Cell address_pad0 ( M1 )
Bounds : ( 1547.950, 430.000 ) ( 1550.150, 430.400 )
Actual: 0.4 Min: 0.8
 
SPACING: Pin of Cell right_down_pad & Blockage of Cell address_pad0 ( M1 )
Bounds : ( 1550.150, 430.000 ) ( 1550.700, 430.400 )
Actual: 0.68 Min: 0.8
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1355.300 ) ( 1884.750, 1373.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1550.750, 1354.850 ) ( 1884.750, 1373.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1550.950, 1353.850 ) ( 1884.750, 1373.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1356.050 ) ( 1549.950, 1372.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1357.150 ) ( 1977.150, 1372.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1358.950 ) ( 1977.550, 1372.900 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1783.850, 1416.900 ) ( 1867.550, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1688.950, 1416.900 ) ( 1778.250, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1653.050, 1416.900 ) ( 1686.950, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1586.650, 1416.900 ) ( 1651.050, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M2 )
Bounds : ( 1550.750, 1416.900 ) ( 1584.650, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1783.850, 1416.900 ) ( 1867.550, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1779.750, 1416.900 ) ( 1782.350, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1688.950, 1416.900 ) ( 1778.250, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1653.050, 1416.900 ) ( 1686.950, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1586.650, 1415.300 ) ( 1651.050, 1420.000 )
 
 
SHORT: Pin of Cell address_pad8 & Blockage of Cell gnd_pad_right ( M3 )
Bounds : ( 1550.750, 1416.900 ) ( 1584.650, 1420.000 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1885.550, 1408.300 ) ( 1970.550, 1419.600 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1410.450 ) ( 1550.750, 1419.600 )
 
 
SHORT: Pin of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1392.450 ) ( 1550.750, 1406.450 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1407.250 ) ( 1884.750, 1409.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M1 )
Bounds : ( 1547.950, 1389.250 ) ( 1884.750, 1391.650 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1408.000 ) ( 1977.550, 1408.900 )
 
 
OVERLAP: Blockage of Cell gnd_pad_right & Blockage of Cell address_pad8 ( M2 )
Bounds : ( 1547.950, 1390.000 ) ( 1977.550, 1390.900 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M1 )
Bounds : ( 772.500, 1978.000 ) ( 857.500, 2063.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 2063.800 ) ( 848.700, 2068.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1780.600 ) ( 845.400, 1960.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 763.900, 1744.700 ) ( 845.400, 1780.200 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1960.800 ) ( 848.700, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1780.200 ) ( 848.700, 1780.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 760.400, 1744.300 ) ( 848.700, 1744.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 760.500, 1961.750 ) ( 848.600, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1876.300 ) ( 845.200, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1872.200 ) ( 845.200, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1781.400 ) ( 845.200, 1870.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.100, 1745.500 ) ( 845.200, 1779.400 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 764.850, 1744.500 ) ( 844.450, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 765.500, 1744.500 ) ( 843.600, 2070.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1876.300 ) ( 763.100, 1960.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1876.300 ) ( 763.100, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1876.300 ) ( 742.200, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1876.300 ) ( 742.200, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1876.300 ) ( 787.900, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1876.300 ) ( 787.900, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1876.300 ) ( 756.100, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.950, 1744.500 ) ( 755.350, 2069.500 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 744.600, 1744.500 ) ( 754.500, 2070.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1781.400 ) ( 763.100, 1870.700 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M2 )
Bounds : ( 757.100, 1745.500 ) ( 763.100, 1779.400 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1872.200 ) ( 763.100, 1874.800 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1781.400 ) ( 763.100, 1870.700 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell address_pad12 ( M3 )
Bounds : ( 757.100, 1745.500 ) ( 763.100, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1745.500 ) ( 742.200, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1745.500 ) ( 742.200, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1781.400 ) ( 742.200, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1781.400 ) ( 742.200, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.100, 1872.200 ) ( 742.200, 1874.800 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.100, 1872.200 ) ( 742.200, 1874.800 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1745.500 ) ( 787.900, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1745.500 ) ( 787.900, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1781.400 ) ( 787.900, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1781.400 ) ( 787.900, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M3 )
Bounds : ( 784.800, 1872.200 ) ( 787.900, 1874.800 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell reset_n_pad ( M2 )
Bounds : ( 784.800, 1872.200 ) ( 787.900, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1780.200 ) ( 759.600, 1780.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1744.300 ) ( 759.600, 1744.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1872.200 ) ( 756.100, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1781.400 ) ( 756.100, 1870.700 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 743.200, 1745.500 ) ( 756.100, 1779.400 )
 
 
SHORT: Pin of Cell clk_pad & Blockage of Cell address_pad12 ( M1 )
Bounds : ( 739.500, 1978.000 ) ( 747.500, 2063.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell reset_n_pad ( M1 )
Bounds : ( 760.400, 1978.000 ) ( 771.700, 2063.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 751.600, 1978.000 ) ( 759.600, 2063.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M1 )
Bounds : ( 739.500, 2063.800 ) ( 759.600, 2068.000 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M2 )
Bounds : ( 739.500, 1960.800 ) ( 759.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad12 & Blockage of Cell clk_pad ( M3 )
Bounds : ( 739.600, 1961.750 ) ( 759.500, 2069.500 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1876.300 ) ( 1200.000, 1960.000 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1876.300 ) ( 1200.000, 1960.000 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1876.300 ) ( 1195.050, 1960.000 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1876.300 ) ( 1195.050, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1876.300 ) ( 849.100, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1876.300 ) ( 849.100, 1960.000 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1876.300 ) ( 873.100, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1876.300 ) ( 894.800, 1960.000 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1876.300 ) ( 894.800, 1960.000 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1876.300 ) ( 1196.100, 1960.000 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1876.300 ) ( 890.900, 1960.000 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1745.500 ) ( 849.100, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1745.500 ) ( 849.100, 1779.400 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1781.400 ) ( 849.100, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1781.400 ) ( 849.100, 1870.700 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M3 )
Bounds : ( 846.200, 1872.200 ) ( 849.100, 1874.800 )
 
 
SHORT: Pin of Cell address_pad12 & Blockage of Cell filler1 ( M2 )
Bounds : ( 846.200, 1872.200 ) ( 849.100, 1874.800 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1872.200 ) ( 873.100, 1874.800 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1781.400 ) ( 873.100, 1870.700 )
 
 
SHORT: Pin of Cell reset_n_pad & Blockage of Cell filler1 ( M3 )
Bounds : ( 867.100, 1745.500 ) ( 873.100, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1745.500 ) ( 894.800, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1745.500 ) ( 894.800, 1779.400 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1781.400 ) ( 894.800, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1781.400 ) ( 894.800, 1870.700 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 891.900, 1872.200 ) ( 894.800, 1874.800 )
 
 
SHORT: Pin of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 891.900, 1872.200 ) ( 894.800, 1874.800 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1780.200 ) ( 894.400, 1780.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1744.300 ) ( 894.400, 1744.700 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1872.200 ) ( 890.900, 1874.800 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1781.400 ) ( 890.900, 1870.700 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 874.100, 1745.500 ) ( 890.900, 1779.400 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1872.200 ) ( 1200.000, 1874.800 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1781.400 ) ( 1200.000, 1870.700 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M2 )
Bounds : ( 1197.100, 1745.500 ) ( 1200.000, 1779.400 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1872.200 ) ( 1200.000, 1874.800 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1781.400 ) ( 1200.000, 1870.700 )
 
 
SHORT: Pin of Cell address_pad10 & Blockage of Cell address_pad11 ( M3 )
Bounds : ( 1197.100, 1745.500 ) ( 1200.000, 1779.400 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1745.500 ) ( 1195.050, 1779.400 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1745.500 ) ( 1195.050, 1779.400 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1781.400 ) ( 1195.050, 1870.700 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1781.400 ) ( 1195.050, 1870.700 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1191.950, 1872.200 ) ( 1195.050, 1874.800 )
 
 
SHORT: Pin of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1191.950, 1872.200 ) ( 1195.050, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1780.200 ) ( 1199.600, 1780.600 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1744.300 ) ( 1199.600, 1744.700 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1872.200 ) ( 1196.100, 1874.800 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1781.400 ) ( 1196.100, 1870.700 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1196.050, 1745.500 ) ( 1196.100, 1779.400 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M2 )
Bounds : ( 1192.350, 1960.800 ) ( 1199.600, 2069.600 )
 
 
OVERLAP: Blockage of Cell address_pad11 & Blockage of Cell address_pad10 ( M3 )
Bounds : ( 1192.450, 1961.750 ) ( 1199.500, 2069.500 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M2 )
Bounds : ( 870.400, 1960.800 ) ( 894.400, 2069.600 )
 
 
OVERLAP: Blockage of Cell filler1 & Blockage of Cell filler0 ( M3 )
Bounds : ( 870.500, 1961.750 ) ( 894.300, 2069.500 )
 
 
 
Begin Summary ...
Cells : 0
SameNet : 9
Wiring : 0
Antenna : 0
Short : 128
Overlap : 137
End Summary
 
Total Violations : 274 Viols.
/trunk/syn/cadence/extras/iofile/t6507lp_relative.io
0,0 → 1,63
######################################################
# #
# Silicon Perspective, A Cadence Company #
# FirstEncounter IO Assignment #
# #
######################################################
 
Version: 2
 
Pad: clk_pad N
Pad: reset_n_pad N
 
Pad: data_in_pad0 S
Pad: data_in_pad1 S
Pad: data_in_pad2 S
Pad: data_in_pad3 S
Pad: data_in_pad4 S
Pad: data_in_pad5 S
Pad: data_in_pad6 S
Pad: data_in_pad7 S
 
Pad: rw_mem_pad W
 
Pad: data_out_pad0 W
Pad: data_out_pad1 W
Pad: data_out_pad2 W
Pad: data_out_pad3 W
Pad: data_out_pad4 W
Pad: data_out_pad5 W
Pad: data_out_pad6 W
Pad: data_out_pad7 W
 
Pad: adress_pad0 E
Pad: adress_pad1 E
Pad: adress_pad2 E
Pad: adress_pad3 E
Pad: adress_pad4 E
Pad: adress_pad5 E
Pad: adress_pad6 E
Pad: adress_pad7 E
Pad: adress_pad8 E
Pad: adress_pad9 N
Pad: adress_pad10 N
Pad: adress_pad11 N
Pad: adress_pad12 N
 
Pad: left_up_pad NW
Pad: right_up_pad NE
Pad: left_down_pad SW
Pad: right_down_pad SE
 
Pad: gnd_pad_left W
Pad: gnd_pad_right E
Pad: gnd_pad_up N
Pad: gnd_pad_down S
 
Pad: vdd_pad_left W
Pad: vdd_pad_right E
Pad: vdd_pad_up N
Pad: vdd_pad_down S
 
Pad: filler0 N
Pad: filler1 N
trunk/syn/cadence/extras/iofile/t6507lp_relative.io Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/cadence/extras/iofile/encounter.cmd =================================================================== --- trunk/syn/cadence/extras/iofile/encounter.cmd (nonexistent) +++ trunk/syn/cadence/extras/iofile/encounter.cmd (revision 259) @@ -0,0 +1,153 @@ +####################################################### +# # +# Encounter Command Logging File # +# Created on Wed Jul 15 15:54:34 # +# # +####################################################### +loadConfig /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io.conf 0 +setUIVar rda_Input ui_gndnet gnd +setUIVar rda_Input ui_pwrnet vdd +commitConfig +fit +setDrawView fplan +loadIoFile /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/extras/iofile/t6507lp_absolute.io +setDrawView place +setDrawView fplan +floorPlan -site core_l -r 2.14232581205 1 0.1 2.0 0.0 6.0 +setRoutingStyle -top -style m +uiSetTool select +fit +floorPlan -site core_l -r 1.08982791242 0.330995 0.1 2.0 0.0 9.8 +setRoutingStyle -top -style m +uiSetTool select +fit +loadIoFile /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/extras/iofile/t6507lp_absolute.io +setDrawView place +setDrawView fplan +setDrawView ameba +setDrawView place +uiSetTool addPoly +editAddPoly 755.789 1371.149 +editAddPoly 1109.842 1291.487 +editAddPoly 1092.139 1099.709 +editAddPoly 844.302 1146.916 +editAddPoly 879.708 1412.455 +uiSetTool addWire +uiSetTool select +verifyGeometry +setDrawView fplan +setDrawView ameba +setDrawView place +resizeFP -ySize +1 -proportional +fit +verifyGeometry +saveFPlan /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/floorplan/t6507lp_io.fp +setDrawView fplan +addRing -spacing_bottom 1 -width_left 1.2 -width_bottom 1.2 -width_top 1.2 -spacing_top 1 -layer_bottom MET1 -stacked_via_top_layer MET3 -width_right 1.2 -around core -jog_distance 1.15 -offset_bottom 1.15 -layer_top MET1 -threshold 1.15 -offset_left 1.15 -spacing_right 1 -spacing_left 1 -offset_right 1.15 -offset_top 1.15 -layer_right MET2 -nets VDD5R -stacked_via_bottom_layer MET1 -layer_left MET2 +checkFPlan -outFile t6507lp_io.checkFPlan +setDrawView fplan +checkFPlan -reportUtil -outFile t6507lp_io.checkFPlan +setDrawView fplan +verifyConnectivity -type all -error 1000 -warning 50 +zoomOut +zoomBox 364.554 2227.846 848.658 1808.682 +selectMarker 554.5000 1990.4000 639.5000 2075.4000 -1 3 18 +deselectAll +selectInst vdd_pad_up +clearDrc +zoomOut +zoomOut +zoomOut +deselectAll +selectInst reset_n_pad +deselectAll +selectInst clk_pad +deselectAll +selectInst vdd_pad_up +deselectAll +addRing -spacing_bottom 1 -width_left 1.2 -width_bottom 1.2 -width_top 1.2 -spacing_top 1 -layer_bottom MET1 -stacked_via_top_layer MET3 -width_right 1.2 -around core -jog_distance 1.15 -offset_bottom 1.15 -layer_top MET1 -threshold 1.15 -offset_left 1.15 -spacing_right 1 -spacing_left 1 -offset_right 1.15 -offset_top 1.15 -layer_right MET2 -nets vdd -stacked_via_bottom_layer MET1 -layer_left MET2 +setDrawView place +zoomBox 149.697 1718.492 1962.823 345.352 +zoomBox 339.838 561.097 575.250 361.903 +zoomBox 417.721 438.576 455.928 422.999 +selectWire 427.7500 429.6500 1557.1500 430.8500 1 vdd +zoomOut +deselectAll +selectWire 427.7500 451.7500 428.9500 466.2500 2 vdd +zoomOut +zoomOut +zoomOut +zoomOut +deselectAll +fit +verifyGeometry +selectInst data_in_pad0 +zoomBox 377.838 542.336 584.468 338.658 +deselectAll +zoomBox 455.037 440.235 526.167 421.862 +zoomBox 496.863 431.670 506.275 424.832 +selectInst data_in_pad0 +deselectAll +selectMarker 497.3000 429.6500 499.9000 430.0000 1 1 6 +zoomOut +zoomOut +deselectAll +zoomBox 425.970 432.716 430.247 429.238 +selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1 +deselectAll +selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1 +deselectAll +selectWire 427.7500 429.6500 1557.1500 430.8500 1 vdd +deselectAll +selectMarker 427.7500 430.8500 429.6000 431.4000 1 1 2 +deselectAll +selectMarker 427.7500 429.6000 428.9500 429.6500 2 1 2 +deselectAll +selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1 +deselectAll +selectMarker 427.7500 429.6500 428.9500 430.1000 2 1 1 +deselectAll +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomBox 86.331 1781.665 2104.163 152.088 +zoomBox 411.300 1679.793 1612.930 1591.623 +zoomOut +zoomOut +zoomOut +zoomBox -338.031 1335.676 1942.216 279.561 +zoomBox 453.366 443.234 1606.299 372.065 +zoomBox 785.860 465.224 876.540 381.741 +zoomBox 831.936 430.161 839.634 424.388 +selectMarker 833.7000 429.6000 834.1000 429.6500 1 1 2 +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +zoomOut +deselectAll +undo +setDrawView ameba +setDrawView fplan +setDrawView place +zoomBox 474.096 1750.997 646.327 1573.844 +zoomOut +zoomOut +zoomOut +zoomOut +verifyGeometry +zoomOut +mp::checkFence -clear +setPlanDesignMode -powerAware -createFence -useExistingPowerRail +planDesign Index: trunk/syn/cadence/extras/iofile/t6507lp_absolute.io =================================================================== --- trunk/syn/cadence/extras/iofile/t6507lp_absolute.io (nonexistent) +++ trunk/syn/cadence/extras/iofile/t6507lp_absolute.io (revision 259) @@ -0,0 +1,77 @@ +###################################################### +# # +# Cadence Design Systems, Inc. # +# FirstEncounter Data file for I/O Placement +# # +###################################################### +# Created by First Encounter v07.10-p011_1 on Wed Jul 15 09:56:44 2009 + +(globals + version = 3 + io_order = default +) +(iopad + (topright + (inst name="right_up_pad" ) + ) + (left + (inst name="address_pad9" offset=430.0000 ) + (inst name="address_pad10" offset=540.0000 ) + (inst name="address_pad11" offset=650.0000 ) + (inst name="vdd_pad_left" offset=760.0000 ) + (inst name="gnd_pad_left" offset=870.0000 ) + (inst name="address_pad12" offset=980.0000 ) + (inst name="rw_mem_pad" offset=1090.0000 ) + (inst name="scan_pad" offset=1200.0000 ) + (inst name="clk_pad" offset=1310.0000 ) + (inst name="reset_n_pad" offset=1420.0000 ) + ) + (topleft + (inst name="left_up_pad" ) + ) + (right + (inst name="data_out_pad0" offset=430.0000 ) + (inst name="data_out_pad1" offset=540.0000 ) + (inst name="data_out_pad2" offset=650.0000 ) + (inst name="data_out_pad3" offset=760.0000 ) + (inst name="vdd_pad_right" offset=870.0000 ) + (inst name="gnd_pad_right" offset=980.0000 ) + (inst name="data_out_pad4" offset=1090.0000 ) + (inst name="data_out_pad5" offset=1200.0000 ) + (inst name="data_out_pad6" offset=1310.0000 ) + (inst name="data_out_pad7" offset=1420.0000 ) + + ) + (bottomleft + (inst name="left_down_pad" ) + ) + (top + (inst name="data_in_pad0" offset=430.0000 ) + (inst name="data_in_pad1" offset=540.0000 ) + (inst name="data_in_pad2" offset=650.0000 ) + (inst name="data_in_pad3" offset=760.0000 ) + (inst name="vdd_pad_up" offset=870.0000 ) + (inst name="gnd_pad_up" offset=980.0000 ) + (inst name="data_in_pad4" offset=1090.0000 ) + (inst name="data_in_pad5" offset=1200.0000 ) + (inst name="data_in_pad6" offset=1310.0000 ) + (inst name="data_in_pad7" offset=1420.0000 ) + (inst name="test_pad" offset=1530.0000 ) + ) + (bottomright + (inst name="right_down_pad" ) + ) + (bottom + (inst name="address_pad0" offset=430.0000 ) + (inst name="address_pad1" offset=540.0000 ) + (inst name="address_pad2" offset=650.0000 ) + (inst name="address_pad3" offset=760.0000 ) + (inst name="vdd_pad_down" offset=870.0000 ) + (inst name="gnd_pad_down" offset=980.0000 ) + (inst name="address_pad4" offset=1090.0000 ) + (inst name="address_pad5" offset=1200.0000 ) + (inst name="address_pad6" offset=1310.0000 ) + (inst name="address_pad7" offset=1420.0000 ) + (inst name="address_pad8" offset=1530.0000 ) + ) +) Index: trunk/syn/cadence/extras/iofile/t6507lp_io.checkFPlan =================================================================== --- trunk/syn/cadence/extras/iofile/t6507lp_io.checkFPlan (nonexistent) +++ trunk/syn/cadence/extras/iofile/t6507lp_io.checkFPlan (revision 259) @@ -0,0 +1,16 @@ +########################################## +# # +# Cadence Design Systems, Inc. # +# FirstEncounter Floorplan check file # +# # +########################################## +**INFO: Unplaced Io Pins = 34 + +**INFO: Floating/Unconnected IO Pins = 1 + +**INFO: No. of regular pre-routes not on tracks : 0 + + +Reporting Utilizations.... + +Core Utilization = 32.625702 Index: trunk/syn/cadence/extras/iofile/t6507lp_io.conn.rpt =================================================================== --- trunk/syn/cadence/extras/iofile/t6507lp_io.conn.rpt (nonexistent) +++ trunk/syn/cadence/extras/iofile/t6507lp_io.conn.rpt (revision 259) @@ -0,0 +1,10 @@ +Verify Connectivity report created on Wed Jul 15 16:04:53 2009 + + +Net vdd: no routing +Net gnd: no routing + +Begin Summary + 2 Problem(s) [ 98]: Net has no global routing and no special routing. + 2 total info(s) created. +End Summary Index: trunk/syn/cadence/extras/lefdef.layermap =================================================================== --- trunk/syn/cadence/extras/lefdef.layermap (nonexistent) +++ trunk/syn/cadence/extras/lefdef.layermap (revision 259) @@ -0,0 +1,7 @@ +#type layer_ict lefdef layer_lef +poly POLY lefdef POLY +metal MET1 lefdef MET1 +metal MET2 lefdef MET2 +metal MET3 lefdef MET3 +via VIA lefdef VIA +via VIA2 lefdef VIA2 Index: trunk/syn/cadence/scripts/LP_io.cmd =================================================================== --- trunk/syn/cadence/scripts/LP_io.cmd (revision 258) +++ trunk/syn/cadence/scripts/LP_io.cmd (revision 259) @@ -5,12 +5,13 @@ set FILE_LIST {t6507lp_io.v t6507lp.v t6507lp_alu.v t6507lp_fsm.v} set_attr lp_insert_clock_gating true / -set_attribute lp_insert_operand_isolation true / -#set_attr dft_scan_style muxed_scan / +set_attr lp_insert_operand_isolation true / +set_attr dft_scan_style muxed_scan / +#set_attr dft_scan_map_mode tdrc_pass / +# this will force the mapping of all registers that passed dft rules into scannable registers +set_attr hdl_search_path $SVNPATH/rtl/verilog/ +set_attr lib_search_path "$SVNPATH/syn/cadence/libs/ /home" -set_attribute hdl_search_path $SVNPATH/rtl/verilog/ -set_attr lib_search_path $SVNPATH/syn/cadence/libs/ - read_hdl $FILE_LIST -v2001 set_attr library {D_CELLSL_3_3V.lib IO_CELLS_33.lib} @@ -17,8 +18,7 @@ set_attribute avoid false [find / -libcell LGC*] set_attribute avoid false [find / -libcell LSG*] set_attribute avoid false [find / -libcell LSOGC*] - -set_attribute avoid true [find / -libcell EN2LX1] +#set_attribute avoid true [find / -libcell EN2LX1] # the EN2LX1 cell always reports violations. i have also declared the dont use attribute of the cell in the .lib file set_attribute lef_library {xc06_m3_FE.lef D_CELLSL.lef IO_CELLS.lef} @@ -28,20 +28,30 @@ elaborate define_clock -period 1000000 -name 1MHz [find [ find / -design t6507lp_io] -port clk] set_attribute slew {0 0 1 1} [find / -clock 1MHz] - external_delay -clock [find / -clock 1MHz] -output 100 [all_outputs] external_delay -clock [find / -clock 1MHz] -input 100 [all_inputs] #0.1 ns each -read_vcd simvision.vcd -module t6507lp +define_dft shift_enable -active high [find / -port scan_enable] -name SE +set_attribute lp_clock_gating_test_signal SE /des*/* -#check_design +#read_vcd simvision.vcd -module t6507lp -static +#argh +#check_design -all -report timing -lint +#report timing -lint +check_dft_rules + synthesize -to_generic -effort high synthesize -to_mapped -effort high -no_incremental -clock_gating share +#clock_gating share +define_dft scan_chain -name chain1 -sdi [find / -pin data_in[0]] -sdo [find / -pin data_out[0]] -shared_out -shared_select SE -shift_enable SE +connect_scan_chains +check_dft_rules + synthesize -incremental -effort high +#write_hdl t6507lp_io > gates.v + write_encounter design -basename /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io t6507lp_io
/trunk/syn/cadence/scripts/rc.cmd
1,7 → 1,10
# Cadence Encounter(R) RTL Compiler
# version v07.20-s009_1 (32-bit) built Feb 7 2008
# version v07.20-s009_1 (64-bit) built Feb 7 2008
#
# Run with the following arguments:
# -files LP_io.cmd
# -logfile rc.log
# -cmdfile rc.cmd
 
source LP_io.cmd
exit

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