URL
https://opencores.org/ocsvn/tcp_socket/tcp_socket/trunk
Subversion Repositories tcp_socket
Compare Revisions
- This comparison shows the changes necessary to convert path
/tcp_socket/trunk/scripts
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/atlys.py
19,16 → 19,30
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if "compile" in sys.argv or "all" in sys.argv: |
print "Compiling C files using chips ...." |
retval = os.system("../chips2/c2verilog ../source/user_design_atlys.c") |
retval = os.system("../chips2/c2verilog ../source/user_design.c") |
retval = os.system("../chips2/c2verilog ../source/server.c") |
if retval != 0: |
sys.exit(-1) |
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if "synth_estimate" in sys.argv: |
print "Test build to estimate size ...." |
os.mkdir(os.path.join(current_directory, "synth_estimate")) |
os.chdir(os.path.join(current_directory, "synth_estimate")) |
retval = os.system("../chips2/c2verilog ../source/server.c") |
output_file = open("server.prj", "w") |
output_file.write("verilog work server.v") |
output_file.close() |
os.system("%s/xflow -synth xst_mixed.opt -p XC6Slx45-CSG324 -implement balanced.opt -config bitgen.opt server"%xilinx) |
os.chdir(current_directory) |
shutil.rmtree("synth_estimate") |
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if "build" in sys.argv or "all" in sys.argv: |
print "Building Demo using Xilinx ise ...." |
retval = os.system("%s/xflow -synth xst_mixed.opt -p XC6Slx45-CSG324 -implement balanced.opt -config bitgen.opt ATLYS"%xilinx) |
if retval != 0: |
sys.exit(-1) |
shutil.copyfile("server.v", os.path.join(current_directory, "precompiled", "server.v")) |
shutil.copyfile("ATLYS.bit", os.path.join(current_directory, "precompiled", "ATLYS.bit")) |
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if "download" in sys.argv or "all" in sys.argv: |
print "Downloading bit file to development kit ...." |