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URL https://opencores.org/ocsvn/tg68kc/tg68kc/trunk

Subversion Repositories tg68kc

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  • This comparison shows the changes necessary to convert path 
    /tg68kc
    from Rev 10 to Rev 9
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  •

Rev 10 → Rev 9

/trunk/TG68K_ALU.vhd
237,7 → 237,7
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
-- IF exe_opcode(15)='1' THEN
OP1in <= result_div(47 downto 32)&result_div(15 downto 0); --word
OP1in <= result_div(47 downto 32)&result_div(15 downto 0);
ELSE --64bit
IF exec(write_reminder)='1' THEN
OP1in <= result_div(63 downto 32);
316,7 → 316,7
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
c_in(0) <= '1';
END IF;
opaddsub <= exec(addsub);
386,9 → 386,7
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
END IF;
-- IF cpu(1)='1' THEN
Vflag_a <= '0'; --TG 01.11.2019 only for cputest -- but other behaiver in real 68000 Hardware ??? I must check this later
-- END IF;
Vflag_a <= '0'; --TG 01.11.2019 only for cputest -- but other behaiver in real 68000 Hardware ??? I must check this later
bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
END PROCESS;
985,10 → 983,8
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSIF exe_opcode(15)='1' OR DIV_Mode=0 THEN
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
ELSE
Flags(3 downto 0) <= OP1IN(31)&flag_z(2)&"00";
END IF;
ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
Flags(3) <= set_flags(3);
1031,8 → 1027,7
ELSE
Flags(2) <='0';
END IF;
Flags(1) <= '0';
Flags(0) <= NOT set_flags(0);
Flags(1 downto 0) <= "00";
END IF;
END IF;
END IF;
/trunk/TG68K_Pack.vhd
116,8 → 116,9
constant store_ea_packdata : integer := 80; --
constant exec_BS : integer := 81; --
constant hold_OP2 : integer := 82; --
constant opcTRAPV : integer := 83; --
 
constant lastOpcBit : integer := 82;
constant lastOpcBit : integer := 83;
 
component TG68K_ALU
generic(
/trunk/TG68KdotC_Kernel.vhd
19,12 → 19,8
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
 
-- 10.11.2019 TG inset TRAPcc
-- 08.11.2019 TG bugfix movem in 68020 mode
-- 06.11.2019 TG bugfix CHK
-- 06.11.2019 TG bugfix flags and stackframe DIVU
-- 04.11.2019 TG insert RTE from TH
-- 03.11.2019 TG insert TrapV from TH
-- 03.11.2019 TG bugfix MUL 64Bit
69,9 → 65,9
-- CHK2
-- CMP2
-- cpXXX Coprozessor stuff
-- TRAPcc
 
-- done 020:
-- TRAPcc
-- done 020:
-- PACK
-- UNPK
-- Bitfields
89,15 → 85,22
 
entity TG68KdotC_Kernel is
generic(
SR_Read : integer:= 2; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer:= 2; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer:= 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BitField : integer := 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
BarrelShifter : integer := 1; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Hardware : integer := 1 --0=>no, 1=>yes,
SR_Read : integer:= 1; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer:= 1; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer:= 1; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 1; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
MUL_Hardware : integer := 0; --0=>no, 1=>yes,
DIV_Mode : integer := 1; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BarrelShifter : integer := 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
BitField : integer := 1 --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- SR_Read : integer:= 0; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
-- VBR_Stackframe : integer:= 0; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
-- extAddr_Mode : integer:= 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
-- MUL_Hardware : integer := 1; --0=>no, 1=>yes,
-- DIV_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
-- BarrelShifter : integer := 0; --0=>no, 1=>yes, 2=>switchable with CPU(1)
-- BitField : integer := 0 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(clk : in std_logic;
nReset : in std_logic; --low active
127,8 → 130,6
architecture logic of TG68KdotC_Kernel is
 
 
signal use_VBR_Stackframe : std_logic;
 
signal syncReset : std_logic_vector(3 downto 0);
signal Reset : std_logic;
signal clkena_lw : std_logic;
148,8 → 149,8
signal exe_opcode : std_logic_vector(15 downto 0);
signal sndOPC : std_logic_vector(15 downto 0);
 
signal exe_pc : std_logic_vector(31 downto 0);--TH
signal last_opc_pc : std_logic_vector(31 downto 0);--TH
signal exe_pc : std_logic_vector(31 downto 0);--TH
signal last_opc_pc : std_logic_vector(31 downto 0);--TH
signal last_opc_read : std_logic_vector(15 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
256,7 → 257,6
signal trap_1111 : bit;
signal trap_trap : bit;
signal trap_trapv : bit;
signal trap_trapcc : bit;
signal trap_interrupt : bit;
signal trapmake : bit;
signal trapd : bit;
263,7 → 263,6
signal trap_SR : std_logic_vector(7 downto 0);
signal make_trace : std_logic;
signal make_berr : std_logic;
signal useStackframe2 : std_logic;
signal set_stop : bit;
signal stop : bit;
426,14 → 425,7
Reset <= NOT syncReset(3);
END IF;
END IF;
IF rising_edge(clk) THEN
IF VBR_Stackframe=1 or (cpu(0)='1' and VBR_Stackframe=2) THEN
use_VBR_Stackframe<='1';
ELSE
use_VBR_Stackframe<='0';
END IF;
END IF;
END PROCESS;
END PROCESS;
PROCESS (clk, long_done, last_data_in, data_in, addr, long_start, memmaskmux, memread, memmask, data_read)
BEGIN
697,13 → 689,11
use_direct_data <= '0';
Z_error <= '0';
ELSIF clkena_lw='1' THEN
useStackframe2<='0';
direct_data <= '0';
IF state="11" THEN
exec_write_back <= '0';
ELSIF setstate="10" AND write_back='1' THEN
-- ELSIF setstate = "10" AND write_back = '1' AND next_micro_state = idle THEN --this shut be a fix for pinball
-- --but it destory pack -(ax),-(ay) and unpack
-- elsif setstate = "10" and write_back = '1' and next_micro_state = idle then --???
exec_write_back <= '1';
END IF;
 
752,12 → 742,10
-- paste and copy form TH ---------
elsif micro_state=trap00 THEN
data_write_tmp <= exe_pc; --TH
useStackframe2<='1';
elsif micro_state = trap0 then
-- this is only active for 010+ since in 000 writePC is
-- true in state trap0
-- if trap_trace='1' or set_exec(opcTRAPV)='1' or Z_error='1' then
IF useStackframe2='1' THEN
if trap_trace='1' or set_exec(opcTRAPV) = '1' then
-- stack frame format #2
data_write_tmp(15 downto 0) <= "0010" & trap_vector(11 downto 0); --TH
else
818,11 → 806,11
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec,
memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu, use_VBR_Stackframe)
memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu)
BEGIN
IF rising_edge(clk) THEN
IF clkena_lw='1' THEN
IF clkena_lw='1' THEN
trap_vector(31 downto 10) <= (others => '0');
IF trap_berr='1' THEN
trap_vector(9 downto 0) <= "00" & X"08";
833,7 → 821,7
IF trap_illegal='1' THEN
trap_vector(9 downto 0) <= "00" & X"10";
END IF;
IF set_Z_error='1' THEN
IF z_error='1' THEN
trap_vector(9 downto 0) <= "00" & X"14";
END IF;
IF exec(trap_chk)='1' THEN
862,10 → 850,10
END IF;
END IF;
END IF;
IF use_VBR_Stackframe='1' THEN
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
trap_vector_vbr <= trap_vector;
ELSE
trap_vector_vbr <= trap_vector+VBR;
ELSE
trap_vector_vbr <= trap_vector;
END IF;
memaddr_a(4 downto 0) <= "00000";
945,7 → 933,7
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, trap_trapcc, interrupt, tmp_TG68_PC, TG68_PC)
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
BEGIN
PC_dataa <= TG68_PC;
1144,6 → 1132,9
IF decodeOPC='1' OR exec(ld_rot_cnt)='1' OR rot_cnt/="000001" THEN
rot_cnt <= set_rot_cnt;
END IF;
-- IF setstate(1)='1' AND set_datatype="00" THEN
-- byte <= '1';
-- END IF;
IF set_Suppress_Base='1' THEN
Suppress_Base <= '1';
1175,16 → 1166,7
IF setnextpass='1' OR regdirectsource='1' THEN
nextpass <= '1';
END IF;
END IF;
 
-- why do not I need this ??? What are the immediate data for ???
-- IF trap_trapcc='1' THEN
-- IF opcode(2 downto 0)="100" THEN
-- exe_pc <= (others => '0');
-- ELSE
-- exe_pc <= last_data_read;
-- END IF;
-- END IF;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= FlagsSR;
1355,7 → 1337,7
PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, trap_trapcc, last_data_in, use_VBR_Stackframe,
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, last_data_in,
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
BEGIN
TG68_PC_brw <= '0';
1392,7 → 1374,6
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trap_trapcc <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
1429,20 → 1410,16
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF interrupt='1' AND trap_berr='1' THEN
next_micro_state <= trap0;
IF preSVmode='0' THEN
set(changeMode) <= '1';
END IF;
setstate <= "01";
END IF;
IF trapmake='1' AND trapd='0' THEN
IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(opcCHK)='1') THEN
-- paste and copy form TH ---------
if trap_trapv = '1' and (VBR_Stackframe = 1 or (cpu(0) = '1' and VBR_Stackframe = 2)) then
next_micro_state <= trap00;
else
next_micro_state <= trap0;
end if;
IF use_VBR_Stackframe='0' THEN
------------------------------------
-- next_micro_state <= trap0;
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
set(writePC_add) <= '1';
-- set_datatype <= "10";
END IF;
1451,9 → 1428,16
END IF;
setstate <= "01";
END IF;
IF interrupt='1' AND trap_berr='1' THEN
next_micro_state <= trap0;
IF preSVmode='0' THEN
set(changeMode) <= '1';
END IF;
setstate <= "01";
END IF;
IF micro_state=int1 OR (interrupt='1' AND trap_trace='1') THEN
-- paste and copy form TH ---------
if trap_trace='1' AND use_VBR_Stackframe='1' then
if trap_trace='1' AND (VBR_Stackframe=1 or (cpu(0)='1' AND VBR_Stackframe=2)) then
next_micro_state <= trap00; --TH
else
next_micro_state <= trap0;
1469,6 → 1453,14
setstate <= "01";
END IF;
if micro_state = int1 or (interrupt = '1' and trap_trace = '1') then
if trap_trace='1' AND (VBR_Stackframe=1 or (cpu(0)='1' AND VBR_Stackframe=2)) then
next_micro_state <= trap00; --TH
else
next_micro_state <= trap0;
end if;
-- if cpu(0)='0' then
-- set_datatype <= "10";
-- end if;
if preSVmode = '0' then
set(changeMode) <= '1';
end if;
1784,14 → 1776,14
ELSE --chk
IF opcode(7)='1' THEN
datatype <= "01"; --Word
set(trap_chk) <= '1';
set(trap_chk) <= '1';
IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
trapmake <= '1';
END IF;
ELSIF cpu(1)='1' THEN --chk long for 68020
datatype <= "10"; --Long
set(trap_chk) <= '1';
IF (c_out(2)='0' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
set(trap_chk) <= '1';
IF (c_out(2)='1' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
trapmake <= '1';
END IF;
ELSE
2290,6 → 2282,7
END IF;
WHEN "1110110" => --trapv
set_exec(opcTRAPV) <= '1'; --TH
IF decodeOPC='1' THEN
setstate <= "01";
END IF;
2299,7 → 2292,7
END IF;
WHEN "1111010"|"1111011" => --movec
IF cpu="00" THEN
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
trap_illegal <= '1';
trapmake <= '1';
ELSIF SVmode='0' THEN
2335,6 → 2328,7
--
---- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
IF decodeOPC='1' THEN
2341,30 → 2335,7
next_micro_state <= dbcc1;
set(OP2out_one) <= '1';
data_is_source <= '1';
END IF;
ELSIF opcode(5 downto 3)="111" AND (opcode(2 downto 1)="01" OR opcode(2 downto 0)="100") THEN --trapcc
IF cpu(1)='1' THEN -- only 68020+
IF opcode(2 downto 1)="01" THEN
IF decodeOPC='1' THEN
IF opcode(0)='1' THEN --long
set(longaktion) <= '1';
END IF;
next_micro_state <= nop;
END IF;
ELSE
IF decodeOPC='1' THEN
setstate <= "01";
END IF;
END IF;
trap_trapcc<='1';
IF exe_condition='1' AND decodeOPC='0' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
ELSE --Scc
datatype <= "00"; --Byte
ea_build_now <= '1';
3048,10 → 3019,7
IF last_data_read(15 downto 0)/=X"0000" THEN
setstate <="01";
IF opcode(5 downto 3)="100" THEN
set(mem_addsub) <= '1';
IF cpu(1)='1' THEN
set(Regwrena) <= '1'; --tg
END IF;
set(mem_addsub) <= '1';
END IF;
next_micro_state <= movem2;
END IF;
3140,10 → 3108,10
set(postadd) <= '1';
next_micro_state <= unlink2;
WHEN unlink2 => -- unlink
set(ea_data_OP2) <= '1';
set(ea_data_OP2) <= '1';
-- paste and copy form TH ---------
WHEN trap00 => -- TRAP format #2
when trap00 => -- TRAP format #2
next_micro_state <= trap0;
set(presub) <= '1';
setstackaddr <='1';
3154,7 → 3122,7
set(presub) <= '1';
setstackaddr <='1';
setstate <= "11";
IF use_VBR_Stackframe='1' THEN --68010
IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN --68010
set(writePC_add) <= '1';
datatype <= "01";
-- set_datatype <= "10";
3229,7 → 3197,7
set(postadd) <= '1';
setstackaddr <= '1';
set(directPC) <= '1';
IF use_VBR_Stackframe='0' OR opcode(2)='1' THEN --opcode(2)='1' => opcode is RTR
IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) OR opcode(2)='1' THEN --opcode(2)='1' => opcode is RTR
set(update_FC) <= '1';
set(direct_delta) <= '1';
END IF;
3237,7 → 3205,7
WHEN rte2 => -- RTE
datatype <= "01";
set(update_FC) <= '1';
IF use_VBR_Stackframe='1' AND opcode(2)='0' THEN
IF (VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2)) AND opcode(2)='0' THEN
-- 010+ reads another word
setstate <= "10";
set(postadd) <= '1';
3462,7 → 3430,7
case brief(11 downto 0) is
when X"002" => movec_data <= "0000000000000000000000000000" & (CACR AND "0011");
 
when X"801" =>
when X"801" => --if VBR_Stackframe=1 or (cpu(0)='1' and VBR_Stackframe=2) then
movec_data <= VBR;
--end if;
when others => NULL;

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