URL
https://opencores.org/ocsvn/tg68kc/tg68kc/trunk
Subversion Repositories tg68kc
Compare Revisions
- This comparison shows the changes necessary to convert path
/tg68kc
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/TG68K_ALU.vhd
180,13 → 180,10
-- signal i : integer range 0 to 31; |
-- signal i : std_logic_vector(5 downto 0); |
|
-- signal hot_bit : std_logic_vector(33 downto 0); simulation error => |
signal hot_bit : std_logic_vector(63 downto 0); |
signal hot_msb : std_logic_vector(32 downto 0); |
signal hot_msb : std_logic_vector(33 downto 0); |
signal vector : std_logic_vector(32 downto 0); |
signal result_bs : std_logic_vector(65 downto 0); |
signal bit_nr : std_logic_vector(5 downto 0); |
signal bit_nr7 : std_logic_vector(6 downto 0); |
signal bit_msb : std_logic_vector(5 downto 0); |
signal bs_shift : std_logic_vector(5 downto 0); |
signal bs_shift_mod : std_logic_vector(5 downto 0); |
271,7 → 268,6
OP1in <= bf_datareg; --new bitfieldvector for bfins - for others the old bitfieldvector |
ELSIF exec(opcMOVESR)='1' THEN |
OP1in(7 downto 0) <= Flags; |
-- IF exe_datatype="00" THEN |
IF exe_opcode(9)='1' THEN |
OP1in(15 downto 8) <= "00000000"; |
ELSE |
390,7 → 386,7
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4)); |
bcd_a <= bcd_pur(9 downto 1) - bcd_kor; |
END IF; |
Vflag_a <= '0'; --nur zum testen |
Vflag_a <= '0'; --TG 01.11.2019 only for cputest -- but other behaiver in real 68000 Hardware ??? I must check this later |
bcd_a_carry <= bcd_pur(9) OR bcd_a(8); |
END PROCESS; |
|
496,8 → 492,6
ELSE |
bf_datareg <= datareg; |
END IF; |
-- bf_datareg <= shifted_bitmask(31 downto 4)&"0000"; |
-- result(31 downto 0)<=datareg; |
|
-- shift bitmask for operation |
IF bf_loffset(4)='1' THEN |
715,8 → 709,8
----------------------------------------------------------------------------- |
-- Barrel Shifter |
----------------------------------------------------------------------------- |
process (OP1out, OP2out, opcode, bit_nr, bit_nr7, bit_msb, hot_bit, bs_shift, bs_shift_mod, ring, result_bs, exe_opcode, vector, |
rot_bits, Flags, msb, hot_msb, asl_over, asl_over_xor, ALU, asr_sign, exec) |
process (OP1out, OP2out, opcode, bit_nr, bit_msb, bs_shift, bs_shift_mod, ring, result_bs, exe_opcode, vector, |
rot_bits, Flags, bs_C, msb, hot_msb, asl_over, asl_over_xor, ALU, asr_sign, exec) |
begin |
ring <= "100000"; |
IF rot_bits="10" THEN --ROX L/R |
754,33 → 748,11
END IF; |
END IF; |
|
bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring)); |
|
bit_nr <= bs_shift_mod(5 downto 0); |
bit_nr7 <= ('1'&ring)-('0'&bs_shift_mod); |
IF exe_opcode(8)='0' THEN --right shift |
bit_nr <= bit_nr7(5 downto 0); |
END IF; |
IF rot_bits(1)='0' THEN --only shift |
IF unsigned(bs_shift)<33 THEN |
IF exe_opcode(8)='0' THEN --right shift |
bit_nr <= 32-bs_shift; |
ELSE |
bit_nr <= bs_shift; |
END IF; |
ELSE |
bit_nr <= "100001"; |
bit_msb <= "000000"; |
END IF; |
END IF; |
|
|
-- calc V-Flag by ASL |
bit_msb <= "000000"; |
hot_msb <= (OTHERS =>'0'); |
hot_msb(conv_integer(bit_msb)) <= '1'; |
IF bs_shift > ring THEN |
bit_msb <= "000000"; |
ELSE |
IF bs_shift < ring THEN |
bit_msb <= ring-bs_shift; |
END IF; |
asl_over_xor <= (('0'&vector(30 downto 0)) XOR ('0'&vector(31 downto 1)))&msb; |
797,20 → 769,17
bs_V <= not asl_over(32); |
END IF; |
|
bs_X <= bs_C; |
IF exe_opcode(8)='0' THEN --right shift |
bs_C <= result_bs(31); |
bs_X <= result_bs(31); |
ELSE --left shift |
CASE exe_opcode(7 downto 6) IS |
WHEN "00" => --Byte |
bs_C <= result_bs(8); |
bs_X <= result_bs(8); |
WHEN "01"|"11" => --Word |
bs_C <= result_bs(16); |
bs_X <= result_bs(16); |
WHEN "10" => --Long |
bs_C <= result_bs(32); |
bs_X <= result_bs(32); |
WHEN OTHERS => NULL; |
END CASE; |
END IF; |
838,15 → 807,12
WHEN "00" => --Byte |
ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(16 downto 9); |
bs_C <= result_bs(8) OR result_bs(17); |
bs_X <= result_bs(8) OR result_bs(17); |
WHEN "01"|"11" => --Word |
ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(32 downto 17); |
bs_C <= result_bs(16) OR result_bs(33); |
bs_X <= result_bs(16) OR result_bs(33); |
WHEN "10" => --Long |
ALU <= result_bs(31 downto 0) OR result_bs(64 downto 33); |
bs_C <= result_bs(32) OR result_bs(65); |
bs_X <= result_bs(32) OR result_bs(65); |
WHEN OTHERS => NULL; |
END CASE; |
ELSE |
867,6 → 833,33
bs_V <= '0'; |
END IF; |
|
-- calc shift count |
bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring)); |
bit_nr <= bs_shift_mod(5 downto 0); |
IF exe_opcode(8)='0' THEN --right shift |
bit_nr <= ring-bs_shift_mod; |
END IF; |
IF rot_bits(1)='0' THEN --only shift |
IF exe_opcode(8)='0' THEN --right shift |
bit_nr <= 32-bs_shift_mod; |
END IF; |
IF bs_shift = ring THEN |
IF exe_opcode(8)='0' THEN --right shift |
bit_nr <= 32-ring; |
ELSE |
bit_nr <= ring; |
END IF; |
END IF; |
IF bs_shift > ring THEN |
IF exe_opcode(8)='0' THEN --right shift |
bit_nr <= "000000"; |
bs_C <= '0'; |
ELSE |
bit_nr <= ring+1; |
END IF; |
END IF; |
END IF; |
|
-- calc ASR sign |
BSout <= ALU; |
asr_sign <= (OTHERS =>'0'); |
875,7 → 868,6
BSout <= ALU or asr_sign(32 downto 1); |
IF bs_shift > ring THEN |
bs_C <= '1'; |
bs_X <= '1'; |
END IF; |
END IF; |
|
902,12 → 894,7
END IF; |
WHEN OTHERS => NULL; |
END CASE; |
|
hot_bit <= (OTHERS =>'0'); |
hot_bit(conv_integer(bit_nr(5 downto 0))) <= '1'; |
result_bs <= vector * hot_bit(32 downto 0); |
-- if you don't like to use the multiplier -> uncommend next line and commend the lines before |
-- result_bs <= std_logic_vector(unsigned('0'&X"00000000"&vector) sll to_integer(unsigned(bit_nr(5 downto 0)))); |
result_bs <= std_logic_vector(unsigned('0'&X"00000000"&vector) sll to_integer(unsigned(bit_nr(5 downto 0)))); |
|
end process; |
|
/trunk/TG68KdotC_Kernel.vhd
21,6 → 21,8
------------------------------------------------------------------------------ |
------------------------------------------------------------------------------ |
|
-- 03.11.2019 TG rework barrel shifter - some other tweaks |
-- 02.11.2019 TG bugfig N-Flag and Z-Flag for DIV |
-- 30.10.2019 TG bugfix RTR in 68020-mode |
-- 30.10.2019 TG bugfix BFINS again |
-- 19.10.2019 TG insert some bugfixes from apolkosnik |
1257,11 → 1259,10
|
IF rising_edge(clk) THEN |
IF Reset='1' THEN |
FlagsSR(5) <= '1'; |
FC(2) <= '1'; |
SVmode <= '1'; |
preSVmode <= '1'; |
FlagsSR(3 downto 0) <= "0111"; |
FlagsSR <= "00100111"; |
make_trace <= '0'; |
ELSIF clkena_lw = '1' THEN |
IF setopcode='1' THEN |
1297,7 → 1298,10
END IF; |
IF interrupt='1' THEN |
FC(2) <= '1'; |
END IF; |
END IF; |
IF cpu(1)='0' THEN |
FlagsSR(6) <= '0'; |
END IF; |
FlagsSR(3) <= '0'; |
END IF; |
END IF; |
1975,7 → 1979,8
set_exec(opcSWAP) <= '1'; |
set_exec(Regwrena) <= '1'; |
ELSIF opcode(5 downto 3)="001" THEN --bkpt |
|
trap_illegal <= '1'; |
trapmake <= '1'; |
ELSE --pea |
ea_only <= '1'; |
ea_build_now <= '1'; |