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/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/frame_counting.vhd
0,0 → 1,416
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: frame_counting - Behavioral |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: Contains several counters that keep track of the number of packets |
-- received of each protocol type. |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use work.port_block_constants.all; |
|
entity frame_counting is |
Port ( clock : in STD_LOGIC; |
sys_clock : in std_logic; |
reset : in STD_LOGIC; |
-- ICMP_type : in std_logic; |
field_type : in STD_LOGIC_VECTOR (7 downto 0); |
field_data : in std_logic_vector(7 downto 0); |
data_ready : in STD_LOGIC; |
frame_counters : out frame_counters_type); |
-- total_count : out STD_LOGIC_VECTOR (31 downto 0); |
-- ipv4_count : out STD_LOGIC_VECTOR (31 downto 0); |
-- ipv6_count : out STD_LOGIC_VECTOR (31 downto 0); |
-- tcp_count : out STD_LOGIC_VECTOR (31 downto 0); |
-- udp_count : out STD_LOGIC_VECTOR (31 downto 0); |
-- arp_count : out STD_LOGIC_VECTOR (31 downto 0); |
-- unknown_count : out STD_LOGIC_VECTOR (31 downto 0)); |
end frame_counting; |
|
architecture Behavioral of frame_counting is |
|
signal total_frame_count_s : std_logic_vector(31 downto 0); |
signal ipv4_frame_count_s : std_logic_vector(31 downto 0); |
signal ipv6_frame_count_s : std_logic_vector(31 downto 0); |
signal tcp_frame_count_s : std_logic_Vector(31 downto 0); |
signal udp_frame_count_s : std_logic_Vector(31 downto 0); |
signal arp_frame_count_s : std_logic_Vector(31 downto 0); |
signal unknown_packet_count_s : std_logic_vector(31 downto 0); |
signal icmp_frame_count_s : std_logic_vector(31 downto 0); |
begin |
|
process(sys_clock) |
begin |
if rising_edge(sys_clock) then |
frame_counters.count0 <= total_frame_count_s; |
end if; |
end process; |
|
process(sys_clock) |
begin |
if rising_Edge(sys_clock) then |
frame_counters.count1 <= ipv4_frame_count_s; |
end if; |
end process; |
|
process(sys_clock) |
begin |
if rising_edge(sys_clock) then |
frame_counters.count2 <= ipv6_frame_count_s; |
end if; |
end process; |
|
process(sys_clock) |
begin |
if rising_Edge(sys_clock) then |
frame_counters.count3 <= tcp_frame_count_s; |
end if; |
end process; |
|
process(sys_clock) |
begin |
if rising_edge(sys_clock) then |
frame_counters.count4 <= udp_frame_count_s; |
end if; |
end process; |
|
process(sys_clock) |
begin |
if rising_edge(sys_clock) then |
frame_counters.count5 <= arp_frame_count_s; |
end if; |
end process; |
|
process(sys_clock) |
begin |
if rising_edge(sys_clock) then |
frame_counters.count6 <= unknown_packet_count_s; |
end if; |
end process; |
|
process(sys_clock) |
begin |
if rising_edge(sys_clock) then |
frame_counters.count7 <= ICMP_frame_count_s; |
end if; |
end process; |
|
total_frame_count_s <= tcp_frame_count_s + udp_frame_count_s + arp_frame_count_s + unknown_packet_count_s; |
--tot_cnt:process(reset,data_ready,field_type) |
--begin |
---- if rising_edge(clock) then |
-- if reset = '1' then |
-- total_frame_count_s <= (others => '0'); |
-- elsif data_ready'event and data_ready = '1' then |
-- if field_type = X"05" then |
-- total_frame_count_s <= total_frame_count_s + 1; |
-- else |
-- total_frame_count_s <= total_frame_count_s; |
-- end if; |
-- end if; |
---- end if; |
--end process; |
|
ipv4_cnt:process(clock,reset,data_ready,field_type) |
variable ipv4 : std_logic_vector(31 downto 0); |
begin |
-- if rising_edge(clock) then |
if reset = '1' then |
ipv4 := (others => '0'); |
elsif rising_edge(clock) then |
if data_ready = '1' and field_type = X"1C" then |
ipv4 := ipv4 + 1; |
else |
ipv4 := ipv4; |
end if; |
else |
ipv4 := ipv4; |
end if; |
ipv4_frame_count_s <= ipv4; |
-- end if; |
end process; |
|
ipv6_cnt:process(clock,reset,data_ready,field_type) |
variable ipv6 : std_logic_Vector(31 downto 0); |
begin |
-- if rising_edge(clock) then |
if reset = '1' then |
ipv6 := (others => '0'); |
elsif rising_edge(clock) then |
if data_ready = '1' and field_type = X"33" then |
ipv6 := ipv6 + 1; |
else |
ipv6 := ipv6; |
end if; |
else |
ipv6 := ipv6; |
end if; |
ipv6_frame_count_s <= ipv6; |
-- end if; |
end process; |
|
tcp_cnt:process(clock,reset,data_ready,field_type) |
variable tcp : std_logic_Vector(31 downto 0); |
begin |
-- if rising_edge(clock) then |
if reset = '1' then |
tcp := (others => '0'); |
elsif rising_edge(clock) then |
if data_ready = '1' and field_type = X"25" then |
tcp := tcp + 1; |
else |
tcp := tcp; |
end if; |
else |
tcp := tcp; |
end if; |
tcp_frame_count_s <= tcp; |
-- end if; |
end process; |
|
udp_cnt:process(clock,reset,data_ready,field_type) |
variable udp : std_logic_Vector(31 downto 0); |
begin |
-- if rising_edge(clock) then |
if reset = '1' then |
udp := (others => '0'); |
elsif rising_edge(clock) then |
if data_ready = '1' and field_type = X"2F" then |
udp := udp + 1; |
else |
udp := udp; |
end if; |
else |
udp := udp; |
end if; |
udp_frame_count_s <= udp; |
-- end if; |
end process; |
|
arp_cnt:process(clock,reset,data_ready,field_type) |
variable arp : std_logic_Vector(31 downto 0); |
begin |
-- if rising_edge(clock) then |
if reset = '1' then |
arp := (others => '0'); |
elsif rising_edge(clock) then |
if data_ready = '1' and field_type = X"07" then |
arp := arp + 1; |
else |
arp := arp; |
end if; |
else |
arp := arp; |
end if; |
arp_frame_count_s <= arp; |
-- end if; |
end process; |
|
icmp_cnt: process(clock,reset,data_ready,field_type) |
variable icmp : std_logic_vector(31 downto 0); |
begin |
if rising_edge(clock) then |
if reset = '1' then |
icmp := (others => '0'); |
elsif data_ready = '1' and field_type = X"43" then-- AND icmp_type = '1' then |
icmp := icmp + 1; |
else |
icmp := icmp; |
end if; |
end if; |
icmp_frame_count_s <= icmp; |
end process; |
------------Marlon's version that works---------------------------------- |
--icmp_cnt: process(clock,reset,data_ready,field_type,icmp_type) |
--variable icmp : std_logic_vector(31 downto 0); |
--begin |
-- if rising_edge(clock) then |
-- if reset = '1' then |
-- icmp := (others => '0'); |
-- elsif data_ready = '1' and field_type = X"1F" AND icmp_type = '1' then |
-- icmp := icmp + 1; |
-- else |
-- icmp := icmp; |
-- end if; |
-- end if; |
--icmp_frame_count_s <= icmp; |
--end process; |
----------------end Marlon's version-------------------------------------- |
------------Stacie's version that doesn't work---------------------------------- |
--icmp_cnt: process(clock,reset,data_ready,field_type,field_data) |
--variable icmp : std_logic_vector(31 downto 0); |
--begin |
-- if reset = '1' then |
-- icmp := (others => '0'); |
-- elsif rising_edge(clock) then |
-- if data_ready = '1' and field_type = X"1F" then |
-- if field_data = X"01" then |
-- icmp := icmp + 1; |
-- else |
-- icmp := icmp; |
-- end if; |
-- else |
-- icmp := icmp; |
-- end if; |
-- end if; |
--icmp_frame_count_s <= icmp; |
--end process; |
----------------end Stacie's version-------------------------------------- |
unk_cnt:process(clock,reset,field_type,data_ready) |
variable count_once : std_logic := '0'; |
variable unknown : std_Logic_Vector(31 downto 0); |
begin |
-- if rising_edge(clock) then |
if reset = '1' then |
unknown := (others => '0'); |
count_once := '0'; |
elsif rising_edge(clock) then |
if data_ready = '1' and field_type = X"42" and count_once = '0' then |
unknown := unknown + 1; |
count_once := '1'; |
elsif field_type = X"03" then-- and count_once = '1' then |
count_once := '0'; |
unknown := unknown; |
else |
count_once := count_once; |
unknown := unknown; |
end if; |
else |
unknown := unknown; |
count_once := count_once; |
end if; |
-- end if; |
-- end if; |
unknown_packet_count_s <= unknown; |
end process; |
|
|
--ipv4_cnt:process(reset,data_ready,field_type) |
--begin |
---- if rising_edge(clock) then |
-- if reset = '1' then |
-- IPv4_frame_count_s <= (others => '0'); |
-- elsif data_ready'event and data_ready = '1' then |
-- if field_type = X"1C" then |
-- IPv4_frame_count_s <= IPv4_frame_count_s + 1; |
-- else |
-- IPv4_frame_count_s <= IPv4_frame_count_s; |
-- end if; |
-- end if; |
---- end if; |
--end process; |
-- |
--ipv6_cnt:process(reset,data_ready,field_type) |
--begin |
---- if rising_edge(clock) then |
-- if reset = '1' then |
-- IPv6_frame_count_s <= (others => '0'); |
-- elsif data_ready'event and data_ready = '1' then |
-- if field_type = X"33" then |
-- IPv6_frame_count_s <= IPv6_frame_count_s + 1; |
-- else |
-- IPv6_frame_count_s <= IPv6_frame_count_s; |
-- end if; |
-- end if; |
---- end if; |
--end process; |
-- |
--tcp_cnt:process(reset,data_ready,field_type) |
--begin |
---- if rising_edge(clock) then |
-- if reset = '1' then |
-- tcp_frame_count_s <= (others => '0'); |
-- elsif data_ready'event and data_ready = '1' then |
-- if field_type = X"25" then |
-- tcp_frame_count_s <= tcp_frame_count_s + 1; |
-- else |
-- tcp_frame_count_s <= tcp_frame_count_s; |
-- end if; |
-- end if; |
---- end if; |
--end process; |
-- |
--udp_cnt:process(reset,data_ready,field_type) |
--begin |
---- if rising_edge(clock) then |
-- if reset = '1' then |
-- udp_frame_count_s <= (others => '0'); |
-- elsif data_ready'event and data_ready = '1' then |
-- if field_type = X"2F" then |
-- udp_frame_count_s <= udp_frame_count_s + 1; |
-- else |
-- udp_frame_count_s <= udp_frame_count_s; |
-- end if; |
-- end if; |
---- end if; |
--end process; |
-- |
--arp_cnt:process(reset,data_ready,field_type) |
--variable arp : std_logic_Vector(31 downto 0); |
--begin |
---- if rising_edge(clock) then |
-- if reset = '1' then |
-- ARP_frame_count_s <= (others => '0'); |
-- elsif data_ready'event and data_ready = '1' then |
-- if field_type = X"07" then |
-- ARP_frame_count_s <= ARP_frame_count_s + 1; |
-- else |
-- ARP_frame_count_s <= ARP_frame_count_s; |
-- end if; |
-- end if; |
---- end if; |
--end process; |
-- |
--unk_cnt:process(clock,reset,field_type,data_ready) |
--variable count_once : std_logic := '0'; |
--begin |
-- if rising_edge(clock) then |
-- if reset = '1' then |
-- unknown_packet_count_s <= (others => '0'); |
-- count_once := '0'; |
-- elsif data_ready = '1' then |
-- if field_type = X"42" and count_once = '0' then |
-- unknown_packet_count_s <= unknown_packet_count_s + 1; |
-- count_once := '1'; |
-- elsif field_type = X"03" then-- and count_once = '1' then |
-- count_once := '0'; |
-- unknown_packet_count_s <= unknown_packet_count_s; |
-- else |
-- count_once := count_once; |
-- unknown_packet_count_s <= unknown_packet_count_s; |
-- end if; |
-- else |
-- unknown_packet_count_s <= unknown_packet_count_s; |
-- count_once := count_once; |
-- end if; |
---- end if; |
-- end if; |
--end process; |
|
end Behavioral; |
|
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/protocol_saver.vhd
0,0 → 1,138
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: protocol_fsm - Behavioral |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: Contains FSM that classifies the phy data, providing a corresponding |
-- field identifier called "field_type". This is the "brains" of EmPAC. |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use work.EmPAC_constants.all; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity protocol_saver is |
Port ( clock : in std_logic; |
reset : in std_logic; |
Protocol_indicator : in STD_LOGIC; |
-- optional : in std_logic; |
Field_data : in STD_LOGIC_VECTOR (31 downto 0); |
Field_type : in std_logic_vector(7 downto 0); |
TCP_type_out : out std_logic; |
UDP_type_out : out std_logic; |
ICMP_type_out : out std_logic); |
-- eoframe : out std_logic; |
-- Jump_address : out STD_LOGIC_VECTOR (7 downto 0)); |
end protocol_saver; |
|
architecture Behavioral of protocol_saver is |
|
signal TCP_type : std_logic := '0'; |
signal UDP_type : std_logic := '0'; |
signal ICMP_type : std_logic := '0'; |
|
begin |
|
process(protocol_indicator,field_data,clock,reset) |
begin |
--wait until clock'event and clock = '1'; |
if rising_Edge(clock) then |
if reset = '1' then |
TCP_type <= '0'; |
UDP_type <= '0'; |
ICMP_type <= '0'; |
else--if rising_Edge(clock) then |
if protocol_indicator = '1' then |
-- if field_type = X"06" then --Etherenet header protocol length is 2 bytes |
--protocol_type <= field_data(15 downto 0); |
if field_type = X"1F" then |
if field_data(7 downto 0) = X"06" then |
TCP_type <= '1'; |
UDP_type <= '0'; |
ICMP_type <= '0'; |
elsif field_data(7 downto 0) = X"11" then |
TCP_type <= '0'; |
UDP_type <= '1'; |
ICMP_type <= '0'; |
elsif field_data(7 downto 0) = X"01" then |
TCP_type <= '0'; |
UDP_type <= '0'; |
ICMP_type <= '1'; |
else |
TCP_type <= '0'; |
UDP_type <= '0'; |
ICMP_type <= '0'; |
end if; |
else |
TCP_type <= '0'; |
UDP_type <= '0'; |
ICMP_type <= '0'; |
-- elsif field_type = X"2A" then |
-- protocol_type <= X"FFFD"; |
-- elsif eof = '1' then |
-- protocol_type <= X"FFFF"; |
-- elsif field_type = X"1E" or field_type = X"36" then |
-- protocol_type <= X"00" & field_data(7 downto 0); --All other header's protocol length is 1 byte. |
end if; |
else |
-- protocol_type <= protocol_type; --Retain last protocol value. |
TCP_type <= TCP_type; |
UDP_type <= UDP_type; |
ICMP_type <= ICMP_type; |
end if; |
end if; |
end if; |
end process; |
|
TCP_type_out <= TCP_type; |
UDP_type_out <= UDP_type; |
ICMP_type_out <= ICMP_type; |
--opt:process--(optional,field_type) |
--begin |
-- wait until clock'event and clock = '1'; |
-- case optional is--_delay is--optional is |
-- when '0' => |
-- if ( (field_type = X"2C") or (field_type = X"31") or (field_type = X"40") ) then |
-- eof <= '1'; |
-- else eof <= '0'; |
-- end if; |
-- when '1' => |
-- if ( (field_type = X"22") or (field_type = X"2B") ) then |
-- eof <= '1'; |
-- else eof <= '0'; |
-- end if; |
-- when others => eof <= '0'; |
-- end case; |
-- |
--end process; |
|
end Behavioral; |
|
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/lengthsaver.vhd
0,0 → 1,424
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: lengthsaver - Behavioral |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: This component calculates the length of each packet. |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
USE ieee.std_logic_arith.all; |
use IEEE.std_logic_unsigned.all; |
use work.EmPAC_constants.all; |
|
ENTITY lengthsaver IS |
PORT( |
clock : IN std_logic; |
field_data : IN std_logic_vector (31 DOWNTO 0); |
length_indicator : IN std_logic; |
field_type : IN std_logic_vector (7 DOWNTO 0); |
reset : IN std_logic; |
optional : OUT std_logic; |
length1 : OUT std_logic_vector (17 DOWNTO 0) |
); |
END lengthsaver ; |
-- VHDL Architecture ProtocolAnalyzer.length_block.struct |
-- Generated by Mentor Graphics' HDL Designer(TM) 2003.1 (Build 399) |
|
|
|
ARCHITECTURE struct OF lengthsaver IS |
-- Architecture declarations |
-- Internal signal declarations |
-- SIGNAL IP_header_len : std_logic_vector(15 DOWNTO 0); |
-- SIGNAL opt : std_logic := '0'; |
SIGNAL length1_tmp : std_logic_vector(17 DOWNTO 0) := (others => '0'); |
-- signal ip_total_len : std_logic_vector(15 downto 0); |
-- signal tcp_header_len : std_logic_vector(15 downto 0); |
-- signal no_app_layer : std_logic; |
-- signal app_layer_len : std_logic_vector(15 downto 0); |
-- signal tcp_head : std_logic_vector(15 downto 0); |
-- signal ip_packet_len : std_logic_vector(15 downto 0); |
signal IPv4_header_len : std_logic_vector(17 downto 0) := (others => '0'); |
signal app_layer: std_logic := '0'; |
signal tcp_header_len : std_logic_Vector(17 downto 0) := (others => '0'); |
signal transport_layer_len : std_logic_Vector(17 downto 0) := (others => '0'); |
signal padding : std_logic_Vector(17 downto 0) := (others => '0'); |
signal total_length : std_logic_Vector(17 downto 0) := (others => '0'); |
signal IPv6transp_true : std_logic := '1'; |
signal opt : std_logic := '0'; |
signal padded : std_logic := '0'; |
signal pad_data,udp_length : std_logic_vector(17 downto 0) := (others => '0'); |
|
BEGIN |
|
-- Architecture concurrent statements |
|
-- HDL Embedded Text Block 1 len_calc |
|
-- The field_type bus indicates what packet field is currently coming |
|
-- in on field_data. If the field contains information that will be used to |
|
-- calculate a dynamic field length, the information is registered and/or used |
|
-- in calculations accordingly. |
--tcp_head <= "0000000000" & tcp_header_len; |
-- tcp_head <= "0000000000"&(unsigned(field_data(15 downto 12)) - 5)&"00"; |
|
set_len:process(reset,tcp_header_len,field_type,IPv4_header_len,opt,app_layer,clock,transport_layer_len, |
pad_data) |
begin |
--if reset = '1' then |
-- length1_tmp <= "000000000000000000"; |
|
if rising_edge(clock) then |
if reset = '1' then |
length1_tmp <= (others => '0'); |
elsif field_type = X"02" then |
length1_tmp <= (others => '0'); |
elsif opt = '1' then |
if field_type = X"1C" then |
length1_tmp <= IPv4_header_len - "000000000000010100";--x14, dec_20 |
elsif field_type = X"29" then |
length1_tmp <= TCP_header_len - "000000000000010100";--x14, dec_20 |
elsif field_type = X"37" then |
length1_tmp <= transport_layer_len; |
elsif field_type = X"30" then |
length1_tmp <= "00"&(unsigned(field_data(15 downto 0)) - 8); |
else |
length1_tmp <= length1_tmp; |
end if; |
elsif app_layer = '1' then |
if field_type = X"29" then |
length1_tmp <= Transport_layer_len - TCP_header_len; |
elsif field_type = X"31" then |
-- if padded = '1' then--field_data(15 downto 0) < X"001A" then |
-- length1_tmp <= (X"001A" - field_data(15 downto 0)) + ("00"&(unsigned(field_data(15 downto 0)) - 8)); |
-- else |
length1_tmp <= udp_length + pad_data; |
-- length1_tmp <= ("00"&(unsigned(field_data(15 downto 0)) - 8)) + pad_data;--+ padding;--changed 3-26-08 |
-- end if; |
else |
length1_tmp <= length1_tmp; |
end if; |
elsif opt = '0' and app_layer = '0' then |
if field_type = X"29" then |
length1_tmp <= "000000000000000110"; |
elsif field_type = X"31" then |
-- if padded = '1' then --field_data(15 downto 0) < X"001A" then |
-- length1_tmp <= (X"001A" - field_data(15 downto 0)) + ("00"&(unsigned(field_data(15 downto 0)) - 8)); |
-- else |
length1_tmp <= udp_length + pad_data; |
-- length1_tmp <= ("00"&(unsigned(field_data(15 downto 0)) - 8)) + pad_data;--+ padding;--changed 3-26-08 |
-- end if; |
-- length1_tmp <= "0000000000"&(unsigned(field_data(7 downto 0)) - 8);--original_wrong |
else |
length1_tmp <= length1_tmp; |
end if; |
else |
length1_tmp <= length1_tmp; |
end if; |
else |
length1_tmp <= length1_tmp; |
end if; |
end process; |
|
length1 <= length1_tmp;-- when padded = '0' else |
-- (length1_tmp + padding) when padded = '1'; |
|
process(clock,length_indicator,field_data,field_type) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
padded <= '0'; |
pad_data <= (others => '0'); |
udp_length <= (others => '0'); |
else |
if length_indicator = '1' then |
if field_type = X"30" then |
udp_length <= ("00"&(unsigned(field_data(15 downto 0)) - 8)); |
if field_data(15 downto 0) < X"001A" then |
padded <= '1'; |
pad_data <= "00" & (X"001A" - field_data(15 downto 0)); |
else |
-- udp_length <= udp_length; |
padded <= '0'; |
pad_data <= (others => '0'); |
end if; |
elsif field_type = X"17" then |
udp_length <= (others => '0'); |
padded <= '0'; |
pad_data <= (others => '0'); |
else |
udp_length <= udp_length; |
padded <= padded; |
pad_data <= pad_data; |
end if; |
else |
udp_length <= udp_length; |
padded <= padded; |
pad_data <= pad_data; |
end if; |
end if; |
end if; |
|
|
end process; |
|
|
process(clock,reset,length_indicator,field_type) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
TCP_header_len <= (others => '0'); |
else |
if length_indicator = '1' then |
if field_type = X"17" then |
TCP_header_len <= (others => '0'); |
elsif field_type = X"28" then |
TCP_header_len <= "000000000000" & field_data(15 downto 12) & "00"; |
else |
TCP_header_len <= TCP_header_len; |
end if; |
else |
TCP_header_len <= TCP_header_len; |
end if; |
end if; |
end if; |
end process; |
|
|
process(clock,reset,length_indicator,field_type) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
transport_layer_len <= (others => '0'); |
else |
if length_indicator = '1' then |
if field_type = X"17" then |
transport_layer_len <= (others => '0'); |
elsif field_type = X"1B" then |
transport_layer_len <= (("00" & field_data(15 downto 0)) - IPv4_header_len); |
elsif field_type = X"36" then |
transport_layer_len <= field_data(15 downto 0) & "00"; |
else |
transport_layer_len <= transport_layer_len; |
end if; |
else |
transport_layer_len <= transport_layer_len; |
end if; |
end if; |
end if; |
end process; |
|
|
process(clock,reset,length_indicator,field_type) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
IPv4_header_len <= (others => '0'); |
else |
if length_indicator = '1' then |
if field_type = X"17" then |
IPv4_header_len <= (others => '0'); |
elsif field_type = X"19" then |
IPv4_header_len <= "000000000000" & field_data(3 downto 0) & "00"; |
else |
IPv4_header_len <= IPv4_header_len; |
end if; |
else |
IPv4_header_len <= IPv4_header_len; |
end if; |
end if; |
end if; |
end process; |
|
process(clock,reset,field_type,field_data) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
IPv6transp_true <= '1'; |
else |
if field_type = X"37" then |
if ((field_data(7 downto 0) = X"06") or (field_data(7 downto 0) = X"11")) then |
IPv6transp_true <= '1'; |
else |
IPv6transp_true <= '0'; |
end if; |
elsif field_type = X"17" then |
IPv6transp_true <= '1'; |
else |
IPv6transp_true <= IPv6transp_true; |
end if; |
end if; |
end if; |
end process; |
|
process(clock,reset,field_type,field_data,length_indicator) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
total_length <= (others => '0'); |
else |
if field_type = X"1B" then |
Total_length <= (("00" & field_data(15 downto 0)) + X"12"); |
elsif field_type = X"02" then |
total_length <= (others => '0'); |
else |
total_length <= total_length; |
end if; |
end if; |
end if; |
end process; |
|
--process(clock,reset,total_length,field_type) |
--begin |
-- if rising_edge(clock) then |
-- if reset = '1' then |
-- padded <= '0'; |
-- else |
-- if field_type >= X"1C" then |
-- if (total_length < "000000000001000000") then --"X"40") then |
-- padded <= '1'; |
-- else |
-- padded <= '0'; |
-- end if; |
-- else |
-- padded <= '0'; |
-- end if; |
-- end if; |
-- end if; |
--end process; |
|
|
--process(clock,reset,padded) |
--begin |
-- if rising_edge(clock) then |
-- if reset = '1' then |
-- padding <= (others => '0'); |
-- else |
-- if padded = '1' then |
-- padding <= "000000000001000000" - total_length; |
-- else |
-- padding <= (others => '0'); |
-- end if; |
-- end if; |
-- end if; |
--end process; |
--transp_len: process(clock,reset,IPv4_header_len,field_type,length_indicator,field_data) |
--begin |
--if reset = '1' then |
---- TCP_header_len <= "000000000000000000"; |
---- transport_layer_len <= "000000000000000000"; |
---- IPv4_header_len <= "000000000000000000"; |
-- IPv6transp_true <= '1'; |
--elsif rising_edge(clock) then |
-- if length_indicator = '1' then |
-- if field_type = X"17" then |
---- TCP_header_len <= "000000000000000000"; |
---- transport_layer_len <= "000000000000000000"; |
---- IPv4_header_len <= "000000000000000000"; |
-- IPv6transp_true <= '1'; |
---- elsif field_type = X"19" then |
---- IPv4_header_len <= "000000000000" & field_data(3 downto 0) & "00"; |
---- TCP_header_len <= TCP_header_len; |
---- transport_layer_len <= transport_layer_len; |
-- IPv6transp_true <= IPv6transp_true; |
---- elsif field_type = X"1B" then |
---- transport_layer_len <= (("00" & field_data(15 downto 0)) - IPv4_header_len); |
---- IPv4_header_len <= IPv4_header_len; |
---- TCP_header_len <= TCP_header_len; |
-- IPv6transp_true <= IPv6transp_true; |
-- elsif field_type = X"28" then |
---- TCP_header_len <= "000000000000" & field_data(15 downto 12) & "00"; |
---- IPv4_header_len <= IPv4_header_len; |
---- transport_layer_len <= transport_layer_len; |
-- IPv6transp_true <= IPv6transp_true; |
---- elsif field_type = X"36" then |
---- transport_layer_len <= field_data(15 downto 0) & "00"; |
---- IPv4_header_len <= IPv4_header_len; |
---- TCP_header_len <= TCP_header_len; |
-- IPv6transp_true <= IPv6transp_true; |
-- elsif field_type = X"37" then |
-- if ((field_data(7 downto 0) = X"06") or (field_data(7 downto 0) = X"11")) then |
-- IPv6transp_true <= '1'; |
-- else |
-- IPv6transp_true <= '0'; |
-- end if; |
---- transport_layer_len <= transport_layer_len; |
---- IPv4_header_len <= IPv4_header_len; |
---- TCP_header_len <= TCP_header_len; |
-- else |
---- IPv4_header_len <= IPv4_header_len; |
---- transport_layer_len <= transport_layer_len; |
---- TCP_header_len <= TCP_header_len; |
-- IPv6transp_true <= IPv6transp_true; |
-- end if; |
-- else |
---- IPv4_header_len <= IPv4_header_len; |
---- transport_layer_len <= transport_layer_len; |
---- TCP_header_len <= TCP_header_len; |
-- IPv6transp_true <= IPv6transp_true; |
-- end if; |
--else |
---- IPv4_header_len <= IPv4_header_len; |
---- transport_layer_len <= transport_layer_len; |
---- TCP_header_len <= TCP_header_len; |
-- IPv6transp_true <= IPv6transp_true; |
--end if; |
--end process; |
|
app_lay: process(clock,transport_layer_len,TCP_header_len) |
begin |
--if rising_edge(clock) then |
if (transport_layer_len - TCP_header_len) > "000000000000000000" then |
app_layer <= '1'; |
else |
app_layer <= '0'; |
end if; |
--end if; |
end process; |
|
--app_layer <= '1' when |
|
options: process(clock,TCP_header_len,IPv4_header_len,IPv6transp_true) |
begin |
--if rising_edge(clock) then |
-- if field_type = X"16" or field_type = X"17" then --X"2B" or field_type = X"22" or field_type = X"40" then |
-- opt <= '0'; |
-- els |
if (((TCP_header_len > "000000000000010100") or (IPv4_header_len > "000000000000010100")) or (IPv6transp_true = '0')) then |
opt <= '1'; |
-- elsif IPv6transp_true = '1' then |
-- opt <= '1'; |
else |
opt <= '0'; |
end if; |
--end if; |
end process; |
optional <= opt; |
|
END struct; |
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/ppt.vhd
0,0 → 1,199
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: port_block - Structural |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: Keeps track of which ports have been encountered |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use work.port_block_Constants.all; |
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity port_block is |
Port ( sys_clock : in std_logic; |
clock : in STD_LOGIC; |
reset : in STD_LOGIC; |
reset_100 : in std_logic; |
fifo_empty_out : out std_logic; |
fifo_full_out : out std_logic; |
field_data : in std_logic_vector(31 downto 0); |
field_type : in std_logic_vector(7 downto 0); |
data_ready : in std_logic; |
-- config_trig : in std_logic; |
frame_counters : in frame_counters_type; |
ack_i : in STD_LOGIC; |
dat_i : in STD_LOGIC_vector(31 downto 0); |
dat_o : out STD_LOGIC_VECTOR (31 downto 0); |
adr_o : out STD_LOGIC_VECTOR (21 downto 0); |
we_o : out STD_LOGIC; |
cyc_o : out STD_LOGIC; |
stb_o : out STD_LOGIC; |
fifo_push_count : out std_logic_vector(11 downto 0)); |
end port_block; |
|
architecture Behavioral of port_block is |
|
|
signal lut_ptr : integer range 0 to MAX_NUM_PORTS_2_FIND-1 := 0; |
signal lut_info : lut_check; |
signal fifo_push,fifo_pop,fifo_full,fifo_empty : std_logic; |
signal fifo_push_s : std_logic; |
signal fifo_empty_delay_0,fifo_empty_delay_1,fifo_empty_delay_2 : std_logic := '1'; |
signal fifo_data_out,fifo_data_in : std_logic_vector(24 downto 0); |
signal fifo_data_in_s : std_logic_vector(24 downto 0); |
signal ready_check : std_logic; |
signal fifo0 : std_logic := '1'; |
signal load_lut : std_logic; |
signal enable_lut_search : std_logic; |
signal counter_data : std_Logic_Vector(31 downto 0); |
--signal fifo_push_count : std_logic_vector(11 downto 0); |
|
component fifo_ppt is |
Port ( reset : in STD_LOGIC; |
push_clock : in STD_LOGIC; |
push : in STD_LOGIC; |
fifo_data_in : in std_logic_vector(24 downto 0); |
full : out STD_LOGIC; |
pop_clock : in STD_LOGIC; |
pop : in STD_LOGIC; |
fifo_data_out : out std_logic_vector(24 downto 0); |
empty : out STD_LOGIC; |
fifo_push_count : out std_logic_vector(11 downto 0)); |
end component; |
|
component lut_ppt is |
port( |
clock : in std_logic; |
reset : in std_logic; |
enable_lut_search : in std_logic; |
load_lut : in std_logic; |
lut_data : in std_Logic_vector(16 downto 0); |
lut_info : out lut_check; |
lut_ptr : out integer range 0 to MAX_NUM_PORTS_2_FIND-1 |
); |
end component; |
|
component fsm_ppt is |
Port ( clock : in STD_LOGIC; |
reset : in STD_LOGIC; |
frame_counters : in frame_counters_type; |
fifo_empty : in STD_LOGIC; |
lut_info : in lut_check; |
lut_ptr : in integer range 0 to MAX_NUM_PORTS_2_FIND-1; |
fifo_data_out : in STD_LOGIC_VECTOR (16 downto 0); |
ack_i : in STD_LOGIC; |
dat_i : in STD_LOGIC_VECTOR (31 downto 0); |
dat_o : out STD_LOGIC_VECTOR (31 downto 0); |
adr_o : out STD_LOGIC_VECTOR (21 downto 0); |
cyc_o : out STD_LOGIC; |
stb_o : out STD_LOGIC; |
we_o : out STD_LOGIC; |
fifo_pop : out STD_LOGIC; |
load_lut : out STD_LOGIC; |
enable_lut_search : out STD_LOGIC); |
end component; |
|
begin |
fifo_empty_out <= fifo_empty; |
fifo_full_out <= fifo_full; |
|
fifo: fifo_ppt |
Port map( reset => reset, |
push_clock => clock, |
push => fifo_push, |
fifo_data_in => fifo_data_in, |
full => fifo_full, |
pop_clock => sys_clock, |
pop => fifo_pop, |
fifo_data_out => fifo_data_out, |
empty => fifo_empty, |
fifo_push_count => fifo_push_count); |
|
fifo_store:process(clock,reset,field_type,field_data,data_ready,fifo_full) |
begin |
if reset = '1' then |
fifo_push_s <= '0'; |
fifo_data_in_s <= (others => '0'); |
elsif rising_Edge(Clock) then |
if ((data_ready = '1' and fifo_full = '0') and (field_type = TCP_SOURCE OR field_type = UDP_SOURCE)) then |
fifo_push_s <= '1'; |
fifo_data_in_s <= field_type & '0' & field_data(15 downto 0); |
elsif ((data_ready = '1' and fifo_full = '0') and (field_type = TCP_destination OR field_type = UDP_destination)) then |
fifo_push_s <= '1'; |
fifo_data_in_s <= field_type & '1' & field_data(15 downto 0); |
else |
fifo_push_s <= '0'; |
fifo_data_in_s <= fifo_data_in_s; |
end if; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_edge(clock) then |
fifo_push <= fifo_push_s; |
fifo_data_in <= fifo_data_in_s; |
end if; |
end process; |
|
lut_cmp: lut_ppt |
port map( |
clock => sys_clock, |
reset => reset_100, |
enable_lut_search => enable_lut_search, |
load_lut => load_lut, |
lut_data => fifo_data_out(16 downto 0), |
lut_info => lut_info, |
lut_ptr => lut_ptr |
); |
|
fsm_cmp: fsm_ppt |
Port map( clock => sys_clock, |
reset => reset_100, |
frame_counters => frame_counters, |
fifo_empty => fifo_empty, |
lut_info => lut_info, |
lut_ptr => lut_ptr, |
fifo_data_out => fifo_data_out(16 downto 0), |
ack_i => ack_i, |
dat_i => dat_i, |
dat_o => dat_o, |
adr_o => adr_o, |
cyc_o => cyc_o, |
stb_o => stb_o, |
we_o => we_o, |
fifo_pop => fifo_pop, |
load_lut => load_lut, |
enable_lut_search => enable_lut_search); |
|
|
end Behavioral; |
|
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/fifo_ppt.vhd
0,0 → 1,171
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 15:46:53 03/07/2008 |
-- Design Name: |
-- Module Name: fifo_2_clock - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
Library UNISIM; |
use UNISIM.vcomponents.all; |
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity fifo_ppt is |
Port ( reset : in STD_LOGIC; |
push_clock : in STD_LOGIC; |
push : in STD_LOGIC; |
fifo_data_in : in std_logic_vector(24 downto 0); |
full : out STD_LOGIC; |
pop_clock : in STD_LOGIC; |
pop : in STD_LOGIC; |
fifo_data_out : out std_logic_vector(24 downto 0); |
empty : out STD_LOGIC; |
fifo_push_count : out std_logic_vector(11 downto 0)); |
end fifo_ppt; |
|
architecture Behavioral of fifo_ppt is |
|
--constant MAX_FIFO_SIZE : INTEGER := 16; |
-- |
--signal clk_div_s : std_logic := '0'; |
|
signal almostfull,almostempty : std_logic; |
signal unconnected : std_logic_vector(31 downto 0);-- := X"00000000"; |
signal rdcount : std_logic_vector(11 downto 0); |
signal wrcount : std_logic_vector(11 downto 0); |
signal wrerr : std_logic; |
signal rderr : std_logic; |
signal reset_int : std_logic; |
signal dop : std_logic_vector(3 downto 0); |
signal data_in : std_logic_Vector(31 downto 0); |
signal reset_s : std_logic; |
begin |
|
fifo_data_out <= unconnected(24 downto 0); |
data_in <= "0000000" & fifo_data_in; |
--process(phy_clock) |
--begin |
-- if rising_edge(phy_clock) then |
-- clk_div_s <= not clk_div_s; |
-- end if; |
--end process; |
|
process(push_clock,reset) |
begin |
if(reset = '1') then |
reset_s <= '1'; |
elsif(push_clock'event and push_clock= '1') then |
reset_s <= '0'; |
end if; |
end process; |
|
--process(push_clock) |
-- begin |
-- if(push_clock'event and push_clock = '1') then |
-- reset_s <= reset; |
-- end if; |
-- end process; |
|
FIFO16_inst : FIFO16 |
generic map ( |
ALMOST_FULL_OFFSET => X"080", -- Sets almost full threshold |
ALMOST_EMPTY_OFFSET => X"080", -- Sets the almost empty threshold |
DATA_WIDTH => 36, -- Sets data width to 4, 9, 18, or 36 |
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE |
port map ( |
ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit almost empty output flag |
ALMOSTFULL => ALMOSTFULL, -- 1-bit almost full output flag |
DO => unconnected, -- 32-bit data output |
DOP => DOP, -- 4-bit parity data output |
EMPTY => EMPTY, -- 1-bit empty output flag |
FULL => FULL, -- 1-bit full output flag |
RDCOUNT => RDCOUNT, -- 12-bit read count output |
RDERR => RDERR, -- 1-bit read error output |
WRCOUNT => fifo_push_count,--WRCOUNT, -- 12-bit write count output |
WRERR => WRERR, -- 1-bit write error |
DI => data_in, -- 32-bit data input |
DIP => X"0",--DIP, -- 4-bit partity input |
RDCLK => pop_clock, -- 1-bit read clock input |
RDEN => pop, -- 1-bit read enable input |
RST => reset_s, --reset, -- 1-bit reset input |
WRCLK => push_clock, -- 1-bit write clock input |
WREN => push -- 1-bit write enable input |
); |
--process(push_clock,reset) |
--begin |
-- if rising_edge(push_clock) then |
-- if reset = '1' then |
-- reset_int <= '1'; |
-- else |
-- reset_int <= '0'; |
-- end if; |
-- end if; |
--end process; |
|
end Behavioral; |
|
|
|
-- |
--process(clk_div_s,reset) |
--begin |
-- if rising_edge(clk_div_s) then |
-- reset_2 <= reset; |
-- end if; |
--end process; |
-- |
-- |
-- |
--process(push,phy_clock,reset) |
--begin |
-- if rising_edge(phy_clock) then |
-- if reset = '1' then |
-- push_count <= 0; |
-- elsif push = '1' then |
-- push_count <= push_count + 1; |
-- else |
-- push_count <= push_count; |
-- end if; |
-- end if; |
--end process; |
-- |
--process(pop,clk_div_s,reset) |
--begin |
-- if rising_Edge(clk_div_s) then |
-- if reset_2 = '1' then |
-- pop_count <= 0; |
-- elsif pop = '1' then |
-- pop_count <= pop_count + 1; |
-- else |
-- pop_count <= pop_count; |
-- end if; |
-- end if; |
--end process; |
-- |
--full_s <= '1' when (push_count - pop_count) = MAX_FIFO_SIZE else '0'; |
--empty_s <= '1' when (push_count - pop_count) = 0; |
-- |
--process(clk_div_s) |
--begin |
-- if rising_edge(clk_div_s) then |
-- full <= full_s; |
-- end if; |
--end process; |
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/new_assembler.vhd
0,0 → 1,134
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: new_assembler - Behavioral |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: The assembler combines 8-bit phy data to 32-bit phy data for other |
-- components to further process. |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
entity new_assembler is |
Port ( clock : in STD_LOGIC; |
-- reset : in STD_LOGIC; |
phy_data : in STD_LOGIC_VECTOR (7 downto 0); |
phy_data_valid : in STD_LOGIC; |
field_data_early : out STD_LOGIC_VECTOR (31 downto 0); |
valid : out std_logic |
); |
end new_assembler; |
|
architecture Behavioral of new_assembler is |
|
signal q3 : std_logic_vector(7 downto 0) := X"00"; |
signal q2 : std_logic_vector(7 downto 0) := X"00"; |
signal q1 : std_logic_vector(7 downto 0) := X"00"; |
signal q0 : std_logic_vector(7 downto 0) := X"00"; |
--signal q4 : std_logic_vector(7 downto 0); |
signal valid3 : std_logic := '0'; |
signal valid2 : std_logic := '0'; |
signal valid1 : std_logic := '0'; |
signal valid0 : std_logic := '0'; |
--signal valid4 : std_logic; |
signal field_data_early_s : STD_LOGIC_VECTOR (31 downto 0) := X"00000000"; |
|
begin |
field_data_early <= field_data_early_s; |
process(clock) |
begin |
if rising_Edge(clock) then |
field_data_early_s <= field_data_early_s(23 downto 0) & q0; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_Edge(clock) then |
valid <= valid0; |
end if; |
end process; |
|
|
process(clock) |
begin |
if rising_edge(clock) then |
q3 <= phy_data; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_edge(clock) then |
valid3 <= phy_data_valid; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_edge(clock) then |
q2 <= q3; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_Edge(clock) then |
valid2 <= valid3; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_edge(clock) then |
q1 <= q2; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_Edge(clock) then |
valid1 <= valid2; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_edge(clock) then |
q0 <= q1; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_Edge(clock) then |
valid0 <= valid1; |
end if; |
end process; |
|
end Behavioral; |
|
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/protocol_fsm.vhd
0,0 → 1,1587
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: protocol_fsm - Behavioral |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: Contains FSM that classifies the phy data, providing a corresponding |
-- field identifier called "field_type". This is the "brains" of EmPAC. |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use work.empac_constants.all; |
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity protocol_fsm is |
port(clock : in std_logic; |
reset : in std_logic; |
EmPAC_leds : out std_logic_vector(8 downto 0); |
phy_data_valid : in std_logic; |
field_data_early : in std_logic_vector(31 downto 0); |
opt : in std_logic; |
length1 : in std_logic_vector(17 downto 0);--teger; |
TCP_type : in std_logic; |
UDP_type : in std_logic; |
icmp_type : in std_logic; |
protocol_ind : out std_logic; |
length_ind : out std_logic; |
port_ind : out std_logic; |
field_type_out : out std_logic_vector(7 downto 0); |
field_type_early : out std_logic_vector(7 downto 0); |
data_ready : out std_logic; |
field_data : out std_logic_vector(31 downto 0); |
end_of_frame : out std_logic); |
end protocol_fsm; |
|
architecture Behavioral of protocol_fsm is |
|
signal CurrentState,NextState : StateType; |
--signal data_tmp : std_logic_vector(31 downto 0); |
signal field_width : std_logic_vector(1 downto 0); |
signal length_s : integer; |
signal fw : integer; |
signal count : integer; |
signal vlf : std_logic; |
signal field_data_s : std_logic_Vector(31 downto 0); |
signal data_ready_off : std_logic; |
signal rst : std_logic; |
signal data_ready_s : std_logic; |
signal phy_data_valid_reg : std_logic; |
signal field_type : std_logic_vector(7 downto 0); |
|
begin |
field_type_early <= field_type; |
fw <= conv_integer(field_width); |
length_s <= conv_integer(length1-1); |
----data_tmp <= field_data_early; |
--data_ready <= data_ready_s or vlf; |
process(clock) |
begin |
if rising_edge(clock) then |
field_type_out <= field_type; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_edge(clock) then |
field_data <= field_data_s; |
end if; |
end process; |
|
process(clock) |
begin |
if rising_edge(clock) then |
phy_data_valid_reg <= phy_data_valid; |
end if; |
end process; |
|
--cnt : process(reset,clock,fw,length_s,rst) |
--begin |
----if reset = '1' then |
---- count <= 0; |
--if rising_edge(clock) then |
-- if reset = '1' then |
-- count <= 0; |
-- else |
-- if rst = '1' then |
-- count <= 0; |
-- elsif vlf = '1' then |
-- if (count = length_s)then-- - 1) then-- or (count = fw)) then |
-- count <= 0; |
-- else |
-- count <= count + 1; |
-- end if; |
-- else |
-- if (count = fw) then |
-- count <= 0; |
-- -- data_ready <= '1'; |
-- else |
-- count <= count + 1; |
-- -- data_ready <= '0'; |
-- end if; |
-- end if; |
-- end if; |
--end if; |
--end process; |
cnt : process(reset,clock,fw,length_s,phy_data_valid,vlf,count) |
begin |
--if reset = '1' then |
-- count <= 0; |
if rising_edge(clock) then |
if reset = '1' then |
count <= 0; |
else |
if phy_data_valid = '1' then |
if vlf = '1' then |
if (count = length_s) then |
count <= 0; |
else |
count <= count + 1; |
end if; |
elsif (count = fw) then |
count <= 0; |
else |
count <= count + 1; |
end if; |
else |
count <= 0; |
end if; |
end if; |
end if; |
end process; |
|
process(clock,reset,vlf,data_ready_off,fw,count) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
data_ready <= '0'; |
else |
if data_ready_off = '1' then |
data_ready <= '0'; |
elsif vlf = '1' then |
data_ready <= '1'; |
elsif count = fw then |
data_ready <= '1'; |
else |
data_ready <= '0'; |
end if; |
end if; |
end if; |
end process; |
|
--process(count,clock,vlf,reset,fw,data_ready_off,length_s) |
--variable cnt_v : integer := 0; |
--begin |
-- if rising_edge(clock) then |
-- if reset = '1' then |
-- data_ready_s <= '0'; |
-- cnt_v := 0; |
-- else--if rising_edge(clock) then |
-- if data_ready_off = '1' then |
-- data_ready_s <= '0'; |
-- cnt_v := 0; |
-- elsif vlf = '1' then |
-- if cnt_v = 3 then |
-- cnt_v := 0; |
-- data_ready_s <= '1'; |
-- elsif count = length_s then--conv_integer(length1_s) then--cnt_v = conv_integer(length1) then -- -1) then |
-- data_ready_s <= '1'; |
-- else |
-- data_ready_s <= '0'; |
-- cnt_v := cnt_v + 1; |
-- end if; |
-- else |
-- if count = fw then -- -1 then |
-- data_ready_s <= '1'; |
-- else |
-- data_ready_s <= '0'; |
-- end if; |
-- end if; |
-- end if; |
-- end if; |
--end process; |
|
--process(clock) |
--begin |
----wait until clock'event and clock = '1'; |
-- if rising_edge(clock) then |
-- field_data <= field_data_s; |
-- end if; |
--end process; |
|
fsm : process(CurrentState,phy_data_valid,phy_data_valid_reg,count,field_data_early,TCP_type,UDP_type,opt,length_s,icmp_type)--,field_data_early) |
begin |
case CurrentState is |
when ftreset => |
if phy_data_valid = '1' then |
NextState <= ft2; |
else |
NextState <= ftreset; |
end if; |
field_width <= "11"; |
-- |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= "00000000000000000000000000000000";--field_data_early; |
field_type <= X"00"; |
data_ready_off <= '1'; |
rst <= '1'; |
EmPAC_leds <= "110000000"; |
end_of_frame <= '1'; |
|
-- when ft0 => |
-- if count = 3 then |
-- NextState <= ft1; |
-- else |
-- NextState <= ft0; |
-- end if; |
-- field_width <= "11"; |
---- |
-- protocol_ind <= '0'; |
-- length_ind <= '0'; |
-- port_ind <= '0'; |
-- vlf <= '0'; |
-- field_data_s <= field_data_early; |
-- field_type <= X"00"; |
-- data_ready_off <= '0'; |
-- EmPAC_leds <= "000000000"; |
-- when ft1 => |
-- if count = 3 then |
-- NextState <= ft2; |
-- else |
-- NextState <= ft1; |
-- end if; |
-- field_width <= "11"; |
---- |
-- protocol_ind <= '0'; |
-- length_ind <= '0'; |
-- port_ind <= '0'; |
-- vlf <= '0'; |
-- field_data_s <= field_data_early; |
-- field_type <= X"01"; |
-- data_ready_off <= '0'; |
-- EmPAC_leds <= "000000001"; |
|
when ft2 => |
if count = 3 then |
NextState <= ft3; |
else |
NextState <= ft2; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"02"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000000010"; |
end_of_frame <= '0'; |
|
when ft3 => |
if count = 1 then |
NextState <= ft4; |
else |
NextState <= ft3; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"03"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000000011"; |
end_of_frame <= '0'; |
|
when ft4 => |
if count = 3 then |
NextState <= ft5; |
else |
NextState <= ft4; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"04"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000000100"; |
end_of_frame <= '0'; |
|
when ft5 => |
if count = 1 then |
NextState <= ft6; |
else |
NextState <= ft5; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"05"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000000101"; |
end_of_frame <= '0'; |
|
when ft6 => |
-- if count = 1 then |
if count = 1 and field_data_early(15 downto 0) = X"0800" then |
NextState <= ft19; |
elsif count = 1 and field_data_early(15 downto 0) = X"86DD" then |
NextState <= ft33; |
elsif count = 1 and field_data_early(15 downto 0) = X"0806" then |
NextState <= ft7; |
elsif count = 1 then |
NextState <= unknown_protocol; |
elsif count = 0 then |
NextState <= ft6; |
else |
NextState <= ft6; |
end if; |
-- end if; |
field_width <= "01"; |
protocol_ind <= '1'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"06"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000000110"; |
end_of_frame <= '0'; |
|
when ft7 => |
if count = 1 then |
NextState <= ft8; |
else |
NextState <= ft7; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"07"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000000111"; |
end_of_frame <= '0'; |
|
when ft8 => |
if count = 1 then |
NextState <= ft9; |
else |
NextState <= ft8; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"08"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001000"; |
end_of_frame <= '0'; |
|
when ft9 => |
if count = 0 then |
NextState <= ftA; |
else |
NextState <= ft9; |
end if; |
field_width <= "00"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"09"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001001"; |
end_of_frame <= '0'; |
when ftA => |
if count = 0 then |
NextState <= ftB; |
else |
NextState <= ftA; |
end if; |
field_width <= "00"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"0A"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001010"; |
end_of_frame <= '0'; |
|
when ftB => |
if count = 1 then |
NextState <= ft_C; |
else |
NextState <= ftB; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"0B"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001011"; |
end_of_frame <= '0'; |
|
when ft_C => |
if count = 3 then |
NextState <= ftD; |
else |
NextState <= ft_C; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"0C"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001100"; |
end_of_frame <= '0'; |
|
when ftD => |
if count = 1 then |
NextState <= ftE; |
else |
NextState <= ftD; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"0D"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001101"; |
end_of_frame <= '0'; |
|
when ftE => |
if count = 3 then |
NextState <= ftF; |
else |
NextState <= ftE; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"0E"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001110"; |
end_of_frame <= '0'; |
|
when ftF => |
if count = 3 then |
NextState <= ft10; |
else |
NextState <= ftF; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"0F"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000001111"; |
end_of_frame <= '0'; |
|
when ft10 => |
if count = 1 then |
NextState <= ft11; |
else |
NextState <= ft10; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"10"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010000"; |
end_of_frame <= '0'; |
|
when ft11 => |
if count = 3 then |
NextState <= ft12; |
else |
NextState <= ft11; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"11"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010001"; |
end_of_frame <= '0'; |
|
when ft12 => |
if count = 3 then |
NextState <= ft13; |
else |
NextState <= ft12; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"12"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010010"; |
end_of_frame <= '0'; |
|
when ft13 => |
if count = 3 then |
NextState <= ft14; |
else |
NextState <= ft13; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"13"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010011"; |
end_of_frame <= '0'; |
|
when ft14 => |
if count = 3 then |
NextState <= ft15; |
else |
NextState <= ft14; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"14"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010100"; |
end_of_frame <= '0'; |
|
when ft15 => |
if count = 3 then |
NextState <= ft16; |
else |
NextState <= ft15; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"15"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010101"; |
end_of_frame <= '0'; |
|
when ft16 => |
if count = 1 then |
NextState <= ft17; |
else |
NextState <= ft16; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"16"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010110"; |
end_of_frame <= '0'; |
|
when ft17 => |
if count = 3 then |
NextState <= ft18; |
else |
NextState <= ft17; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '1'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"17"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000010111"; |
end_of_frame <= '0'; |
when ft18 => |
-- if phy_data_valid = '0' then |
NextState <= ftreset; |
-- elsif count = 0 then |
-- NextState <= ft2; |
-- else |
-- NextState <= ft18; |
-- end if; |
field_width <= "00"; |
--branch_ind <= '1'; |
protocol_ind <= '1'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"18"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011000"; |
end_of_frame <= '0'; |
|
when ft19 => |
if count = 0 then |
NextState <= ft1A; |
else |
NextState <= ft19; |
end if; |
field_width <= "00"; |
|
protocol_ind <= '0'; |
length_ind <= '1'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"19"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011001"; |
end_of_frame <= '0'; |
|
when ft1A => |
if count = 0 then |
NextState <= ft1B; |
else |
NextState <= ft1A; |
end if; |
field_width <= "00"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"1A"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011010"; |
end_of_frame <= '0'; |
|
when ft1B => |
if count = 1 then |
NextState <= ft1C; |
else |
NextState <= ft1B; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '1'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"1B"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011011"; |
end_of_frame <= '0'; |
|
when ft1C => |
if count = 1 then |
NextState <= ft1D; |
else |
NextState <= ft1C; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"1C"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011100"; |
end_of_frame <= '0'; |
|
when ft1D => |
if count = 1 then |
NextState <= ft1E; |
else |
NextState <= ft1D; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"1D"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011101"; |
end_of_frame <= '0'; |
|
when ft1E => |
if count = 0 then |
NextState <= ft1F; |
else |
NextState <= ft1E; |
end if; |
field_width <= "00"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"1E"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011110"; |
end_of_frame <= '0'; |
|
when ft1F => |
if count = 0 then |
NextState <= ft20; |
else |
NextState <= ft1F; |
end if; |
field_width <= "00"; |
|
protocol_ind <= '1'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"1F"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000011111"; |
end_of_frame <= '0'; |
|
when ft20 => |
if count = 1 then |
NextState <= ft21; |
else |
NextState <= ft20; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"20"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100000"; |
end_of_frame <= '0'; |
|
when ft21 => |
if count = 3 then |
NextState <= ft22; |
else |
NextState <= ft21; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"21"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100001"; |
end_of_frame <= '0'; |
|
when ft22 => |
-- if (count = 3 and opt = '1') then |
---- if opt = '1' then--IPv4_header_len > "000000000000010100" then |
-- NextState <= ft23; |
-- elsif (count = 3 and TCP_type = '1') then--field_data_early(15 downto 0) = X"06" then--protocol_type = X"06" then |
-- NextState <= ft24; |
-- elsif (count = 3 and UDP_type = '1') then--field_data_early(15 downto 0) = X"11" then --protocol_type = X"11" then |
-- NextState <= ft2E; |
-- elsif (count = 3 and opt='0' and TCP_type = '0' and UDP_type = '0') then |
-- NextState <= unknown_protocol; |
---- end if; |
-- else |
-- NextState <= ft22; |
-- end if; |
if (count = 3) then |
if (opt = '1') then |
NextState <= ft23; |
elsif (TCP_type = '1') then |
NextState <= ft24; |
elsif (UDP_type = '1') then |
NextState <= ft2E; |
elsif (ICMP_type = '1') then |
Nextstate <= icmp_protocol; |
else --if ((opt = '0') and (TCP_type = '0') and (UDP_type = '0') ) then |
NextState <= unknown_protocol; |
end if; |
else |
NextState <= ft22; |
end if; |
field_width <= "11"; |
--branch_ind <= '1'; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"22"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100010"; |
end_of_frame <= '0'; |
|
when ft23 => |
if (count = length_s)then---1) then |
NextState <= ft17; |
else |
NextState <= ft23; |
end if; |
field_width <= "XX"; |
--branch_ind <= '1'; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '1'; |
field_data_s <= field_data_early; |
field_type <= X"23"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100011"; |
end_of_frame <= '0'; |
|
when ft24 => |
if count = 1 then |
NextState <= ft25; |
else |
NextState <= ft24; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '1'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"24"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100100"; |
end_of_frame <= '0'; |
|
when ft25 => |
if count = 1 then |
NextState <= ft26; |
else |
NextState <= ft25; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '1'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"25"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100101"; |
end_of_frame <= '0'; |
|
when ft26 => |
if count = 3 then |
NextState <= ft27; |
else |
NextState <= ft26; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"26"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100110"; |
end_of_frame <= '0'; |
|
when ft27 => |
if count = 3 then |
NextState <= ft28; |
else |
NextState <= ft27; |
end if; |
field_width <= "11"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"27"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000100111"; |
end_of_frame <= '0'; |
|
when ft28 => |
if count = 1 then |
NextState <= ft29; |
else |
NextState <= ft28; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '1'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"28"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101000"; |
end_of_frame <= '0'; |
|
when ft29 => |
if count = 1 then |
NextState <= ft2A; |
else |
NextState <= ft29; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"29"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101001"; |
end_of_frame <= '0'; |
|
when ft2A => |
if count = 1 then |
NextState <= ft2B; |
else |
NextState <= ft2A; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"2A"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101010"; |
end_of_frame <= '0'; |
|
when ft2B => |
if count = 1 and opt = '1' then |
--if opt = '1' then |
NextState <= ft2C; |
elsif count = 1 and opt = '0' then |
NextState <= ft2D; |
-- end if; |
else |
NextState <= ft2B; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"2B"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101011"; |
end_of_frame <= '0'; |
|
when ft2C => |
if (count = length_s)then---1 then |
NextState <= ft17; |
else |
NextState <= ft2C; |
end if; |
field_width <= "XX"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '1'; |
field_data_s <= field_data_early; |
field_type <= X"2C"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101100"; |
end_of_frame <= '0'; |
|
when ft2D => |
if (count = length_s)then-- - 1 then |
NextState <= ft17; |
else |
NextState <= ft2D; |
end if; |
field_width <= "XX"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '1'; |
field_data_s <= field_data_early; |
field_type <= X"2D"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101101"; |
end_of_frame <= '0'; |
|
when ft2E => |
if count = 1 then |
NextState <= ft2F; |
else |
NextState <= ft2E; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '1'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"2E"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101110"; |
end_of_frame <= '0'; |
when ft2F => |
if count = 1 then |
NextState <= ft30; |
else |
NextState <= ft2F; |
end if; |
field_width <= "01"; |
|
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '1'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"2F"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000101111"; |
end_of_frame <= '0'; |
|
when ft30 => |
if count = 1 then |
NextState <= ft31; |
else |
NextState <= ft30; |
end if; |
field_width <= "01"; |
-- |
protocol_ind <= '0'; |
length_ind <= '1'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"30"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110000"; |
end_of_frame <= '0'; |
|
when ft31 => |
if count = 1 then |
NextState <= ft32; |
else |
NextState <= ft31; |
end if; |
field_width <= "01"; |
-- |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"31"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110001"; |
end_of_frame <= '0'; |
|
when ft32 => |
if (count = length_s)then-- -1 then |
NextState <= ft17; |
else |
NextState <= ft32; |
end if; |
field_width <= "XX"; |
-- |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '1'; |
field_data_s <= field_data_early; |
field_type <= X"32"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110010"; |
end_of_frame <= '0'; |
|
when ft33 => |
if count = 0 then |
NextState <= ft34; |
else |
NextState <= ft33; |
end if; |
field_width <= "00"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"33"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110011"; |
end_of_frame <= '0'; |
|
when ft34 => |
if count = 0 then |
NextState <= ft35; |
else |
NextState <= ft34; |
end if; |
field_width <= "00"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"34"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110100"; |
end_of_frame <= '0'; |
|
when ft35 => |
if count = 1 then |
NextState <= ft36; |
else |
NextState <= ft35; |
end if; |
field_width <= "01"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"35"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110101"; |
end_of_frame <= '0'; |
|
when ft36 => |
if count = 1 then |
NextState <= ft37; |
else |
NextState <= ft36; |
end if; |
field_width <= "01"; |
protocol_ind <= '0'; |
length_ind <= '1'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"0000" & field_data_early(15 downto 0); |
field_type <= X"36"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110110"; |
end_of_frame <= '0'; |
|
when ft37 => |
if count = 0 then |
NextState <= ft38; |
else |
NextState <= ft37; |
end if; |
field_width <= "00"; |
protocol_ind <= '1'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"000000" & field_data_early(7 downto 0); |
field_type <= X"37"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000110111"; |
end_of_frame <= '0'; |
|
when ft38 => |
if count = 0 then |
NextState <= ft39; |
else |
NextState <= ft38; |
end if; |
field_width <= "00"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"38"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111000"; |
end_of_frame <= '0'; |
|
when ft39 => |
if count = 3 then |
NextState <= ft3A; |
else |
NextState <= ft39; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"39"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111001"; |
end_of_frame <= '0'; |
|
when ft3A => |
if count = 3 then |
NextState <= ft3B; |
else |
NextState <= ft3A; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"3A"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111010"; |
end_of_frame <= '0'; |
|
when ft3B => |
if count = 3 then |
NextState <= ft3C; |
else |
NextState <= ft3B; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"3B"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111011"; |
end_of_frame <= '0'; |
|
when ft3C => |
if count = 3 then |
NextState <= ft3D; |
else |
NextState <= ft3C; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"3C"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111100"; |
end_of_frame <= '0'; |
|
when ft3D => |
if count = 3 then |
NextState <= ft3E; |
else |
NextState <= ft3D; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"3D"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111101"; |
end_of_frame <= '0'; |
|
when ft3E => |
if count = 3 then |
NextState <= ft3F; |
else |
NextState <= ft3E; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"3E"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111110"; |
end_of_frame <= '0'; |
|
when ft3F => |
if count = 3 then |
NextState <= ft40; |
else |
NextState <= ft3F; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"3F"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "000111111"; |
end_of_frame <= '0'; |
|
--------------------------------------------------------------------------------------------------- |
when ft40 => |
if count = 3 and opt = '1' then |
-- if opt = '1' then--IPv4_header_len > "000000000000010100" then |
NextState <= ft41; |
elsif count = 3 and TCP_type = '1' then--field_data_early(15 downto 0) = X"06" then--protocol_type = X"06" then |
NextState <= ft24; |
elsif count = 3 and UDP_type = '1' then--field_data_early(15 downto 0) = X"11" then --protocol_type = X"11" then |
NextState <= ft2E; |
elsif count = 3 and opt='0' and TCP_type = '0' and UDP_type = '0' then |
NextState <= unknown_protocol; |
-- end if; |
else |
NextState <= ft40; |
end if; |
field_width <= "11"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= field_data_early; |
field_type <= X"40"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "001000000"; |
end_of_frame <= '0'; |
|
-------------------------------------------------------------------------------------------------- |
|
when ft41 => |
if (count = length_s) then-- -1 then |
NextState <= ft17; |
else |
NextState <= ft41; |
end if; |
field_width <= "XX"; |
protocol_ind <= '1'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '1'; |
field_data_s <= field_data_early; |
field_type <= X"41"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "001000001"; |
end_of_frame <= '0'; |
|
when unknown_protocol => |
if phy_data_valid = '0' then---was if phy_data_valid_reg = 0 |
NextState <= ftreset; |
else |
NextState <= unknown_protocol; |
end if; |
field_width <= "XX"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '1'; |
field_data_s <= field_data_early; |
field_type <= X"42"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "001000010"; |
end_of_frame <= '0'; |
|
when icmp_protocol => |
-- if phy_data_valid = '0' then---was if phy_data_valid_reg = 0 |
-- NextState <= ftreset; |
-- else |
NextState <= unknown_protocol; |
-- end if; |
field_width <= "XX"; |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '1'; |
field_data_s <= field_data_early; |
field_type <= X"43"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "001000010"; |
end_of_frame <= '0'; |
|
when others => |
NextState <= unknown_protocol; |
field_width <= "XX"; |
-- |
protocol_ind <= '0'; |
length_ind <= '0'; |
port_ind <= '0'; |
vlf <= '0'; |
field_data_s <= X"00000000"; |
field_type <= "XXXXXXXX"; |
data_ready_off <= '0'; |
rst <= '0'; |
EmPAC_leds <= "001000011"; |
end_of_frame <= '0'; |
|
end case; |
end process; |
|
nxt_state_logic:process(clock,reset)--(clock,reset) |
begin |
if rising_Edge(clock) then |
if reset = '1' then |
currentstate <= ftreset; |
else |
currentstate <= nextstate; |
end if; |
end if; |
end process; |
|
end Behavioral; |
|
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/lut_ppt.vhd
0,0 → 1,231
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: lut_ppt - Behavioral |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: Keeps track of which ports have been encountered and |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
----------------------------------------------------------------------------------library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use work.port_block_constants.all; |
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity lut_ppt is |
Port ( clock : in STD_LOGIC; |
reset : in STD_LOGIC; |
enable_lut_search : in STD_LOGIC; |
load_lut : in STD_LOGIC; |
lut_data : in STD_LOGIC_VECTOR (16 downto 0); |
lut_info : out lut_check; |
lut_ptr : out integer range 0 to MAX_NUM_PORTS_2_FIND-1); |
end lut_ppt; |
|
architecture Behavioral of lut_ppt is |
|
signal lut : array_table; |
signal lut_ptr_s : integer range 0 to MAX_NUM_PORTS_2_FIND-1 := 0; |
|
begin |
|
--search_lut:process(clock,reset,enable_lut_search,lut,lut_data) |
--variable lut_find : lut_check; |
--begin |
-- if reset = '1' then |
-- lut_find.in_lut := false; |
-- lut_find.lut_pointer := 0; |
-- else |
-- if rising_edge(clock) then |
-- if enable_lut_search = '1' then |
-- for i in 0 to MAX_NUM_PORTS_2_FIND -1 loop |
-- if(lut(i) = lut_data) then |
-- lut_find.in_lut := true; |
-- lut_find.lut_pointer := i; |
-- exit; |
-- else |
-- lut_find.in_lut := false; |
-- lut_find.lut_pointer := 0; |
-- end if; |
-- end loop; |
-- else |
-- lut_find := lut_find; |
-- end if; |
-- end if; |
-- end if; |
--lut_info <= lut_find; |
--end process; |
|
search_lut:process(clock,reset,enable_lut_search,lut,lut_data) |
variable lut_find : lut_check; |
begin |
if reset = '1' then |
lut_find.in_lut := false; |
lut_find.lut_pointer := 0; |
else |
if rising_edge(clock) then |
if enable_lut_search = '1' then |
lut_find := check_lut(lut,lut_data); |
else |
lut_find := lut_find; |
end if; |
end if; |
end if; |
lut_info <= lut_find; |
end process; |
|
process(clock,reset,load_lut,lut_ptr_s,lut_data) |
begin |
if reset = '1' then |
lut_ptr_s <= 0; |
else |
if rising_edge(clock) then |
if load_lut = '1' then |
if lut_ptr_s = MAX_NUM_PORTS_2_FIND-1 then |
lut_ptr_s <= lut_ptr_s; |
else |
lut_ptr_s <= lut_ptr_s + 1; |
end if; |
else |
lut_ptr_s <= lut_ptr_s; |
end if; |
end if; |
end if; |
end process; |
|
process(clock,reset,load_lut,lut_data,lut_ptr_s) |
begin |
if rising_edge(clock) then |
if reset = '1' then |
for i in 0 to MAX_NUM_PORTS_2_FIND-1 loop |
lut(i) <= (others => '0'); |
end loop; |
elsif load_lut = '1' then |
if lut_ptr_s = MAX_NUM_PORTS_2_FIND-1 then |
lut(lut_ptr_s) <= lut(lut_ptr_s); |
else |
lut(lut_ptr_s) <= lut_data; |
end if; |
else |
lut(lut_ptr_s) <= lut(lut_ptr_s); |
end if; |
end if; |
end process; |
|
lut_ptr <= lut_ptr_s; |
end Behavioral; |
|
------------------------------------------------------------------------------------ |
---- Company: |
---- Engineer: |
---- |
---- Create Date: 16:02:26 03/18/2008 |
---- Design Name: |
---- Module Name: lut_ppt - Behavioral |
---- Project Name: |
---- Target Devices: |
---- Tool versions: |
---- Description: |
---- |
---- Dependencies: |
---- |
---- Revision: |
---- Revision 0.01 - File Created |
---- Additional Comments: |
---- |
------------------------------------------------------------------------------------ |
--library IEEE; |
--use IEEE.STD_LOGIC_1164.ALL; |
--use IEEE.STD_LOGIC_ARITH.ALL; |
--use IEEE.STD_LOGIC_UNSIGNED.ALL; |
--use work.port_block_constants.all; |
------ Uncomment the following library declaration if instantiating |
------ any Xilinx primitives in this code. |
----library UNISIM; |
----use UNISIM.VComponents.all; |
-- |
--entity lut_ppt is |
-- Port ( clock : in STD_LOGIC; |
-- reset : in STD_LOGIC; |
-- enable_lut_search : in STD_LOGIC; |
-- load_lut : in STD_LOGIC; |
-- lut_data : in STD_LOGIC_VECTOR (16 downto 0); |
-- lut_info : out lut_check; |
-- lut_ptr : out integer range 0 to MAX_NUM_PORTS_2_FIND-1); |
--end lut_ppt; |
-- |
--architecture Behavioral of lut_ppt is |
-- |
--signal lut : array_table; |
--signal lut_ptr_s : integer range 0 to MAX_NUM_PORTS_2_FIND-1 := 0; |
-- |
--begin |
-- |
--search_lut:process(clock,reset,load_lut,enable_lut_search,lut_ptr_s) |
--variable lut_find : lut_check; |
--variable lut_ptr_v : integer; |
--begin |
-- if reset = '1' then |
-- lut_ptr_s <= 0; |
-- lut_find.in_lut := false; |
-- lut_find.lut_pointer := 0; |
-- for i in 0 to MAX_NUM_PORTS_2_FIND-1 loop |
-- lut(i) <= (others => '0'); |
-- end loop; |
-- |
-- elsif rising_Edge(clock) then |
-- if enable_lut_search = '1' then--search lut--_empty_delay_0 = '0' then |
-- lut_find := check_lut(lut,lut_data); |
-- else |
-- lut_find := lut_find; |
-- end if; |
-- |
-- if (load_lut = '1') then --store value into lut |
-- if lut_ptr_s = MAX_NUM_PORTS_2_FIND-1 then |
-- lut(lut_ptr_s) <= lut(lut_ptr_s); |
-- lut_ptr_s <= lut_ptr_s; |
-- else |
-- lut(lut_ptr_s) <= lut_data; |
-- lut_ptr_s <= lut_ptr_s + 1; |
-- end if; |
-- else |
-- lut(lut_ptr_s) <= lut(lut_ptr_s); |
-- lut_ptr_s <= lut_ptr_s; |
-- end if; |
---- else --everything remains the same |
---- lut_find.in_lut := lut_find.in_lut; |
---- lut_find.lut_pointer := lut_find.lut_pointer; |
---- lut(lut_ptr) <= lut(lut_ptr); |
---- lut_ptr <= lut_ptr; |
---- end if; |
-- end if; |
---- end if; |
-- lut_info <= lut_find; |
--end process; |
--lut_ptr <= lut_ptr_s; |
--end Behavioral; |
|
/trunk/Wizardry/VHDL/Wizardry Top Level/Address Generation/NIDS Components/EmPAC/fsm_ppt.vhd
0,0 → 1,870
+signal increment_rd_data : std_logic;
+signal frame_counters_reg : frame_counters_array_type;
+signal update_counters : std_logic;
+signal increment_counter_ptr : std_logic;
+signal counter_address_reg : std_logic_vector(21 downto 0);
+signal new_counter_address_reg : std_logic_Vector(21 downto 0);
+signal lut_port_address_reg : std_logic_vector(21 downto 0);
+signal lut_port_delim_address_Reg : std_logic_Vector(21 downto 0);
+signal dat_o_reg : std_logic_vector(31 downto 0);
+signal register_address : std_logic;
+signal frame_counter_address_reg : std_logic_vector(21 downto 0);
+signal lut_start_address : std_logic_vector(21 downto 0);
+
+begin
+
+
+lut_start_address <= SHARED_MEM_LUT_SRC_START & "0000000000000";
+
+process(clock,reset,counter_snapshot,counter_ptr)
+begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ frame_counter_address_reg <= (others => '0');
+ elsif counter_snapshot = '1' then
+ frame_counter_address_reg <= SHARED_MEM_COUNTER_START & conv_std_logic_vector(counter_ptr,13);
+ else
+ frame_counter_address_reg <= frame_counter_address_reg;
+ end if;
+ end if;
+end process;
+
+process(clock,register_address)
+begin
+ if rising_edge(clock) then
+ if register_address = '1' then
+ dat_o_reg <= conv_std_logic_vector(lut_ptr-1,15) & fifo_data_out(16 downto 0);
+ else
+ dat_o_reg <= dat_o_reg;
+ end if;
+ end if;
+end process;
+
+process(clock,reset,register_address,lut_info)
+begin
+ if rising_Edge(clock) then
+ if reset = '1' then
+ counter_address_reg <= (others => '0');
+ elsif (register_address = '1' and lut_info.in_lut = true )then
+ counter_address_reg <= SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
+ else
+ counter_address_reg <= counter_address_reg;
+ end if;
+ end if;
+end process;
+
+process(clock,reset,register_address,lut_ptr)
+begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ new_counter_address_reg <= (others => '0');
+ elsif register_address = '1' then
+ new_counter_address_reg <= SHARED_MEM_PREFIX_SOURCE & conv_std_logic_Vector(lut_ptr,13);
+ else
+ new_counter_address_reg <= new_counter_address_reg;
+ end if;
+ end if;
+end process;
+
+process(clock,reset,register_address,lut_ptr)
+begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ lut_port_address_reg <= (others => '0');
+ elsif register_address = '1' then
+ lut_port_address_reg <= SHARED_MEM_LUT_SRC_START & conv_std_logic_vector(lut_ptr-1,13);
+ else
+ lut_port_address_reg <= lut_port_address_reg;
+ end if;
+ end if;
+end process;
+
+process(clock,reset,register_address,lut_ptr)
+begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ lut_port_delim_address_reg <= (others => '0');
+ elsif register_address = '1' then
+ lut_port_delim_address_reg <= SHARED_MEM_LUT_SRC_START & conv_std_logic_Vector(lut_ptr, 13);
+ else
+ lut_port_delim_address_reg <= lut_port_delim_address_reg;
+ end if;
+ end if;
+end process;
+
+process(clock,ack_i)
+begin
+ if rising_edge(clock) then
+ if ack_i = '1' then
+ dat_i_reg <= dat_i;
+ else
+ dat_i_reg <= dat_i_reg;
+ end if;
+ end if;
+end process;
+
+process(clock,reset,increment_rd_data,dat_i_reg)
+begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ dat_i_inc_reg <= (others => '0');
+ else
+ if increment_rd_data = '1' then
+ dat_i_inc_reg <= dat_i_reg + 1;
+ else
+ dat_i_inc_reg <= dat_i_inc_reg;
+ end if;
+ end if;
+ end if;
+end process;
+
+snapshot:process(clock,reset,counter_snapshot)
+begin
+ if rising_edge(clock) then
+ if reset = '1' then
+-- for i in 0 to 6 loop
+ frame_counters_reg(0) <= (others => '0');
+ frame_counters_reg(1) <= (others => '0');
+ frame_counters_reg(2) <= (others => '0');
+ frame_counters_reg(3) <= (others => '0');
+ frame_counters_reg(4) <= (others => '0');
+ frame_counters_reg(5) <= (others => '0');
+ frame_counters_reg(6) <= (others => '0');
+ frame_counters_reg(7) <= (others => '0');
+-- end loop;
+ elsif counter_snapshot = '1' then
+-- for i in 0 to 6 loop
+ frame_counters_reg(0) <= frame_counters.count0;
+ frame_counters_reg(1) <= frame_counters.count1;
+ frame_counters_reg(2) <= frame_counters.count2;
+ frame_counters_reg(3) <= frame_counters.count3;
+ frame_counters_reg(4) <= frame_counters.count4;
+ frame_counters_reg(5) <= frame_counters.count5;
+ frame_counters_reg(6) <= frame_counters.count6;
+ frame_counters_reg(7) <= frame_counters.count7;
+-- end loop;
+ else
+-- for i in 0 to 6 loop
+ frame_counters_reg(0) <= frame_counters_reg(0);
+ frame_counters_reg(1) <= frame_counters_reg(1);
+ frame_counters_reg(2) <= frame_counters_reg(2);
+ frame_counters_reg(3) <= frame_counters_reg(3);
+ frame_counters_reg(4) <= frame_counters_reg(4);
+ frame_counters_reg(5) <= frame_counters_reg(5);
+ frame_counters_reg(6) <= frame_counters_reg(6);
+ frame_counters_reg(7) <= frame_counters_reg(7);
+-- end loop;
+ end if;
+ end if;
+end process;
+
+update_timer:
+process(clock,reset,update_complete)
+variable counter : integer range 0 to 100000000;
+begin
+ if rising_edge(clock) then
+ if reset = '1' then
+ update_counters <= '1';
+ counter := 100000000;
+ else
+ if update_complete = '1' then
+ update_counters <= '0';
+ counter := 0;
+ elsif counter = 100000000 then
+ update_counters <= '1';
+ counter := 100000000;
+ else
+ update_counters <= '0';
+ counter := counter + 1;
+ end if;
+ end if;
+ end if;
+end process;
+
+process(clock,reset,increment_counter_ptr,update_complete)
+begin
+ if rising_Edge(clock) then
+ if reset = '1' then
+ counter_ptr <= 0;
+ else
+ if increment_counter_ptr = '1' then
+ counter_ptr <= counter_ptr + 1;
+ elsif update_complete = '1' then
+ counter_ptr <= 0;
+ else
+ counter_ptr <= counter_ptr;
+ end if;
+ end if;
+ end if;
+end process;
+
+nxtstate_log:process(currentstate,fifo_empty,ack_i,lut_info.in_lut,update_counters,counter_ptr,
+ fifo_data_out,lut_ptr,lut_info.lut_pointer,dat_i_inc_reg,frame_counters_reg,
+ dat_o_reg,lut_port_address_reg,lut_port_delim_address_reg,new_counter_address_reg,
+ counter_address_reg,frame_counter_address_reg)
+begin
+ case currentstate is
+
+ when reset_state =>
+ nextstate <= idle_0_0;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ adr_o <= (others => '0');
+ dat_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when idle_0_0 =>
+ nextstate <= idle_0;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ adr_o <= lut_start_address;--SHARED_MEM_LUT_SRC_START & "0000000000000";
+ dat_o <= X"12345678";
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when idle_0 =>
+ if ack_i = '1' then
+ nextstate <= idle;
+ else
+ nextstate <= idle_0;
+ end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ adr_o <= lut_start_address;--SHARED_MEM_LUT_SRC_START & "0000000000000";--conv_std_logic_vector(active_ptr,13);
+ dat_o <= X"12345678";
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when idle =>
+ if update_counters = '1' then
+ nextstate <= update_counters_2_ddr;
+ elsif fifo_empty = '0' then
+ nextstate <= pop_fifo;--lut_search;
+-- if fifo_empty = '0' then --and update_counters = '0' then
+-- nextstate <= lut_search;
+-- elsif update_counters = '1' then
+-- nextstate <= update_counters_2_ddr;
+ else
+ nextstate <= idle;
+ end if;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when lut_search =>
+ nextstate <= register_ddr_address;--read_lut;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '1';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when register_ddr_address =>
+ nextstate <= read_lut;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '1';
+
+ when read_lut =>
+ if lut_info.in_lut = true then
+ nextstate <= read_ddr;
+ else
+ nextstate <= write_1_to_ddr;--load_lut_value;
+ end if;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when load_lut_value =>
+ nextstate <= register_ddr_address_2;--store_lut_2_ddr;--pop_fifo;--write_1_to_ddr;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '1';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when register_ddr_address_2 =>
+ nextstate <= store_lut_2_ddr;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '1';
+
+ when store_lut_2_ddr =>
+-- if ack_i = '1' then
+-- nextstate <= store_lut_delim;--pop_fifo;
+-- else
+ nextstate <= store_lut_2_ddr_0;
+-- end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= dat_o_reg;--conv_std_logic_vector(lut_ptr-1,15) & fifo_data_out(16 downto 0);
+ adr_o <= lut_port_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr-1),13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when store_lut_2_ddr_0 =>
+ if ack_i = '1' then
+ nextstate <= store_lut_delim_wait;--pop_fifo;
+ else
+ nextstate <= store_lut_2_ddr_0;
+ end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= dat_o_reg;--conv_std_logic_vector(lut_ptr-1,15) & fifo_data_out(16 downto 0);
+ adr_o <= lut_port_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr-1),13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when store_lut_delim_wait =>
+ nextstate <= store_lut_delim;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when store_lut_delim =>
+-- if ack_i = '1' then
+-- nextstate <= pop_fifo;
+-- else
+ nextstate <= store_lut_delim_0;
+-- end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= X"12345678";
+ adr_o <= lut_port_delim_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr),13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when store_lut_delim_0 =>
+ if ack_i = '1' then
+ nextstate <= idle;--pop_fifo;
+ else
+ nextstate <= store_lut_delim_0;
+ end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= X"12345678";
+ adr_o <= lut_port_delim_address_reg;--SHARED_MEM_LUT_SRC_START & conv_std_logic_vector((lut_ptr),13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when write_1_to_ddr =>
+-- if ack_i = '1' then
+-- nextstate <= load_lut_value;--pop_fifo;
+-- else
+ nextstate <= write_1_to_ddr_0;
+-- end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= X"00000001";
+ adr_o <= new_counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_ptr,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when write_1_to_ddr_0 =>
+ if ack_i = '1' then
+ nextstate <= load_lut_value;--pop_fifo;
+ else
+ nextstate <= write_1_to_ddr_0;
+ end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= X"00000001";
+ adr_o <= new_counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_ptr,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+
+ when pop_fifo =>
+ nextstate <= pop_fifo_wait;--idle;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '1';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when pop_fifo_wait =>
+ nextstate <= lut_search;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+ when read_ddr =>
+-- if ack_i = '1' then
+-- nextstate <= increment_ddr_read_data;
+-- else
+ nextstate <= read_ddr_0;
+-- end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when read_ddr_0 =>
+ if ack_i = '1' then
+ nextstate <= increment_ddr_read_data;
+ else
+ nextstate <= read_ddr_0;
+ end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when increment_ddr_read_data =>
+ nextstate <= write_inc_data_2_ddr;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '1';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when write_inc_data_2_ddr =>
+-- if ack_i = '1' then
+-- nextstate <= pop_fifo;
+-- else
+ nextstate <= write_inc_data_2_ddr_0;
+-- end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= dat_i_inc_reg;--dat_i_reg + 1;--counter_data;
+ adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when write_inc_data_2_ddr_0 =>
+ if ack_i = '1' then
+ nextstate <= idle;--pop_fifo;
+ else
+ nextstate <= write_inc_data_2_ddr_0;
+ end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= dat_i_inc_reg;--dat_i_reg + 1;--counter_data;
+ adr_o <= counter_address_reg;--SHARED_MEM_PREFIX_SOURCE & conv_std_logic_vector(lut_info.lut_pointer,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when update_counters_2_ddr =>
+ nextstate <= update_counters_2_ddr_0;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '1';
+ register_address <= '0';
+
+ when update_counters_2_ddr_0 =>
+-- if ack_i = '1' then
+-- nextstate <= check_counter_ptr;--inc_counter_ptr;
+-- else
+ nextstate <= update_counters_2_ddr_1;
+-- end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= frame_counters_reg(counter_ptr);
+ adr_o <= frame_counter_address_reg;--SHARED_MEM_COUNTER_START & conv_std_logic_vector(counter_ptr,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when update_counters_2_ddr_1 =>
+ if ack_i = '1' then
+ nextstate <= check_counter_ptr;--inc_counter_ptr;
+ else
+ nextstate <= update_counters_2_ddr_1;
+ end if;
+ cyc_o <= '1';
+ stb_o <= '1';
+ we_o <= '1';
+ dat_o <= frame_counters_reg(counter_ptr);
+ adr_o <= frame_counter_address_reg;--SHARED_MEM_COUNTER_START & conv_std_logic_vector(counter_ptr,13);
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when check_counter_ptr =>
+ if counter_ptr = MAX_NUM_FRAME_COUNTERS-1 then
+ nextstate <= completed_update;
+ else
+ nextstate <= inc_counter_ptr;
+ end if;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <='0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when inc_counter_ptr =>
+-- if counter_ptr = 6 then
+-- nextstate <= completed_update;
+-- else
+ nextstate <= inc_counter_ptr_wait;--update_counters_2_ddr;
+-- end if;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '1';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when inc_counter_ptr_wait =>
+ nextstate <= update_counters_2_ddr;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when completed_update =>
+ nextstate <= idle;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '1';
+ counter_snapshot <= '0';
+ register_address <= '0';
+
+ when others =>
+ nextstate <= idle;
+ cyc_o <= '0';
+ stb_o <= '0';
+ we_o <= '0';
+ dat_o <= (others => '0');
+ adr_o <= (others => '0');
+ fifo_pop <= '0';
+ load_lut <= '0';
+ enable_lut_search <= '0';
+ increment_rd_data <= '0';
+ increment_counter_ptr <= '0';
+ update_complete <= '0';
+ counter_snapshot <= '0';
+ register_address <= '0';
+ end case;
+end process;
+
+curstate_log:process(clock,reset,nextstate)
+begin
+ if (clock'event AND clock = '1') then
+ if reset = '1' then
+ currentstate <= reset_state;
+ else
+ currentstate <= nextstate;
+ end if;
+
+ end if;
+end process;
+
+end Behavioral;
+
---------------------------------------------------------------------------------- |
-- |
-- This file is a part of Technica Corporation Wizardry Project |
-- |
-- Copyright (C) 2004-2009, Technica Corporation |
-- |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
-- |
---------------------------------------------------------------------------------- |
---------------------------------------------------------------------------------- |
-- Module Name: fsm_ppt - Behavioral |
-- Project Name: Wizardry |
-- Target Devices: Virtex 4 ML401 |
-- Description: Keeps track of which ports have been encountered and |
-- Revision: 1.0 |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
use work.port_block_constants.all; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity fsm_ppt is |
Port ( clock : in STD_LOGIC; |
reset : in STD_LOGIC; |
frame_counters : in frame_counters_type; |
fifo_empty : in STD_LOGIC; |
lut_info : in lut_check; |
lut_ptr : in integer range 0 to MAX_NUM_PORTS_2_FIND-1; |
fifo_data_out : in STD_LOGIC_VECTOR (16 downto 0); |
ack_i : in STD_LOGIC; |
dat_i : in STD_LOGIC_VECTOR (31 downto 0); |
dat_o : out STD_LOGIC_VECTOR (31 downto 0); |
adr_o : out STD_LOGIC_VECTOR (21 downto 0); |
cyc_o : out STD_LOGIC; |
stb_o : out STD_LOGIC; |
we_o : out STD_LOGIC; |
fifo_pop : out STD_LOGIC; |
load_lut : out STD_LOGIC; |
enable_lut_search : out STD_LOGIC); |
end fsm_ppt; |
|
architecture Behavioral of fsm_ppt is |
|
type statetype is (reset_state,idle_0_0,idle_0,idle,lut_search,read_lut,read_ddr, |
load_lut_value,write_1_to_ddr,pop_fifo,pop_fifo_wait, |
increment_ddr_read_data,write_inc_data_2_ddr,store_lut_2_ddr, |
store_lut_2_ddr_0,update_counters_2_ddr,update_counters_2_ddr_0, |
inc_counter_ptr,completed_update,store_lut_delim,store_lut_delim_0, |
inc_counter_ptr_wait,check_counter_ptr,write_1_to_ddr_0,read_ddr_0, |
check_fifo,write_inc_data_2_ddr_0,store_lut_delim_wait, |
register_ddr_address,register_ddr_address_2,update_counters_2_ddr_1); |
|