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  • This comparison shows the changes necessary to convert path 
    /theia_gpu/branches/beta_2.0/rtl
    from Rev 229 to Rev 230
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  •

Rev 229 → Rev 230

/aDefinitions.v
32,7 → 32,7
`define CP_TOP `THEIA_TOP.CP
`define VP_TOP `THEIA_TOP.VPX[ CVPID ].VP
 
`define CONTROL_PROCESSOR_OP_WIDTH 5
`define CONTROL_PROCESSOR_OP_WIDTH 8
`define CONTROL_PROCESSOR_OP_NOP `CONTROL_PROCESSOR_OP_WIDTH'd0
`define CONTROL_PROCESSOR_OP_DELIVER_COMMAND `CONTROL_PROCESSOR_OP_WIDTH'd1
`define CONTROL_PROCESSOR_OP_ADD `CONTROL_PROCESSOR_OP_WIDTH'd2
79,6 → 79,7
`define MCU_COPYMEMBLOCK_TAG_BIT 31
`define MCU_COPYMEMBLOCKCMD_SRCOFF_RNG 63:32
`define MCU_COPYMEMBLOCKCMD_VPMASK_RNG 79:64
`define MCU_VPMASK_LEN (79-64)
//`define MCU_REQUEST_TYPE_BIT 80 //See if it is CPBLOCKCOPY or VPCOMMAND
`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPCODEMEM 1'b1
`define MCU_COPYMEMBLOCKCMD_DSTTYPE_VPDATAMEM 1'b0
134,16 → 135,16
`define OPERATION_MUL 4'b0011
`define OPERATION_SQRT 4'b0100
`define OPERATION_LOGIC 4'b0101
`define OPERATION_OUT 4'b0110
`define OPERATION_IO 4'b0110
 
 
`define RS_ADD0 1 //001
`define RS_ADD1 2 //010
`define RS_DIV 3 //011
`define RS_MUL 4 //100
`define RS_SQRT 5 //101
`define RS_LOGIC 6 //110
`define RS_IO 7 //111
`define RS_ADD0 4'd1 //001
`define RS_ADD1 4'd2 //010
`define RS_DIV 4'd3 //011
`define RS_MUL 4'd4 //100
`define RS_SQRT 4'd5 //101
`define RS_LOGIC 4'd6 //110
`define RS_IO 4'd7 //111
//----------------------------------------------------------------
//Issue bus packet structure
 
189,6 → 190,8
`define MOD_ISSUE_SRC0RS_RNG 99:96
`define MOD_ISSUE_SRC0_DATA_RNG 95:0
 
 
 
`define MOD_ISSUE_TAG1_RNG 8:0
`define MOD_ISSUE_TAG0_RNG 8:0
 
304,6 → 307,8
`define BRANCH_IF_ZERO_OR_SIGN 3'b101 //<=
`define BRANCH_IF_ZERO_OR_NOT_SIGN 3'b110 //>=
//---------------------------------------------------------------
`define IO_OPERATION_OMWRITE 3'b0
`define IO_OPERATION_TMREAD 3'b1
 
`define SRC_RET_ADDR_RNG 95:64
`define X_RNG 95:64
/Module_RadixRMul.v
68,7 → 68,7
input wire Reset,
input wire[31:0] A,
input wire[31:0] B,
output wire[63:0] R,
output wire[31:0] R, //Warning, this sould be 64 bis as in Theia v1.0, I am loosing lots of precision in here!
input wire iUnscaled,
input wire iInputReady,
output wire OutputReady
335,6 → 335,6
assign R_pre2 = ( (SignA ^ SignB) == 1) ? ~R_pre1 + 1'b1 : R_pre1;
 
//assign R = R_pre2 >> `SCALE;
assign R = R_pre2;
assign R = R_pre2[31:0];
 
endmodule
/Module_IO_Station.v
1,24 → 1,24
`include "aDefinitions.v"
 
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
 
33,9 → 33,15
output wire oCommitResquest,
input wire iCommitGranted,
output wire oBusy,
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
output wire oOMEMWriteEnable
//OMEM
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
output wire oOMEMWriteEnable,
//TMEM
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress, //3 * 32 addresses to read from TMEM
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData, //Contains the data read from the TMEM, 3 * 32 bit words
input wire iTMEMDataAvailable, //This is set to one once the TMEM read transaction is complete
output wire oTMEMDataRequest //Set to one to indicate a TMEM read request
);
 
44,48 → 50,104
wire wRS_OMWRITE_Trigger;
wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandA;
wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandB;
wire [`DATA_ROW_WIDTH-1:0] wResult;
wire wCommitGranted;
 
//ReservationStation_1Cycle RS
ReservationStation RS
wire [2:0] wIOOperation;
wire wIOTrigger,wIOTrigger_Pre;
wire ReadInProgress_Delay;
wire wExeDone_pre1,wExeDone_pre2,wExeDone_pre3,wExeDone_pre4;
wire wCommitResquest;
 
//assign oTMEMDataRequest = (wIOTrigger && wIOOperation == `IO_OPERATION_TMREAD ) ? wIOTrigger : 1'b0;
wire ReadInProgress;
assign ReadInProgress = (wIOOperation == `IO_OPERATION_TMREAD) ? 1'b1 : 1'b0;
 
assign oTMEMDataRequest = ((wIOTrigger | ~iTMEMDataAvailable) & ReadInProgress ) ? 1'b1:1'b0;//wIOTrigger : 1'b0;
 
 
assign oTMEMReadAddress = wRS1_OperandA; //Three separate 32 bit addresses comes here, for 3 addresses
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) WOP_FFD0 //TODO: This should be 1 bit
( Clock, Reset, 1'b1 , wIOTrigger_Pre | wExeDone_pre1 | wExeDone_pre2, wIOTrigger );
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) WOP_CR //TODO: This should be 1 bit
( Clock, Reset, ReadInProgress , wCommitResquest, oCommitResquest );
///////////////////////////
//
// wIOOperation
// 000 OMEM
// 001 TMEM
// 010 MAILBOX
//
///////////////////////////
wire wBusy;
 
ReservationStation_EX RS_EX
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iIssueBus( iIssueBus ),
.iCommitBus( iCommitBus ),
.iMyId( iId ),
.iExecutionDone( wExeDone ),
.iResult( wResult ),
.iResult( iTMEMReadData ),
.iCommitGranted( wCommitGranted ),
.oSrc1Latched( wRS1_OperandB ),
.oSrc0Latched( wRS1_OperandA ),
.oBusy( oBusy ),
.oTrigger( wRS_OMWRITE_Trigger )
.oBusy( wBusy ),
.oScale( wIOOperation ),
.oTrigger( wIOTrigger_Pre ),
///
.oCommitRequest( wCommitResquest ),
.oId( oCommitData[`COMMIT_RSID_RNG] ),
.oWE( oCommitData[`COMMIT_WE_RNG] ),
.oDestination( oCommitData[`COMMIT_DST_RNG] ),
.oResult( {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]} )
 
);
 
assign oBusy = (ReadInProgress)? /*oTMEMDataRequest*/ ~iTMEMDataAvailable : wBusy; /// | wIOTrigger_Pre | wExeDone_pre1 | wExeDone_pre2 | wExeDone;
 
assign oCommitResquest = 1'b0; //This is always zero since we are writting anything into the RF
assign oCommitData = `COMMIT_PACKET_SIZE'd0; //This is always zero since we are writting anything into the RF
assign oOMEMWriteData = wRS1_OperandA; //Write 96 bits to external memory OMEM
assign oOMEMWriteAddress = wRS1_OperandB; //Each 32 bit words has the write address
//assign oCommitResquest = 1'b0; //This is always zero since we are not writting anything into the RF
//assign oCommitData = `COMMIT_PACKET_SIZE'd0; //This is always zero since we are not writting anything into the RF
assign oOMEMWriteEnable = (wIOTrigger && wIOOperation == `IO_OPERATION_OMWRITE ) ? wIOTrigger : 1'b0;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD0
( Clock, Reset, 1'b1 , wRS_OMWRITE_Trigger | wExeDone_pre1 | wExeDone_pre2, oOMEMWriteEnable );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 96 ) FFD_SRC0
( Clock, Reset, wIOTrigger_Pre , wRS1_OperandA, oOMEMWriteData );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 96 ) FFD_SRC1
( Clock, Reset, wIOTrigger_Pre , wRS1_OperandB, oOMEMWriteAddress );
 
 
//assign oOMEMWriteData = wRS1_OperandA; //Write 96 bits to external memory OMEM
//assign oOMEMWriteAddress = wRS1_OperandB; //Each 32 bit words has the write address
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD0
( Clock, Reset, 1'b1 , wIOTrigger_Pre | wExeDone_pre1 | wExeDone_pre2, wIOTrigger );
 
//It takes 3 clock cycles to write the 96 bits into OMEM
wire wExeDone_pre1,wExeDone_pre2;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD1
( Clock, Reset, 1'b1 , wRS_OMWRITE_Trigger, wExeDone_pre1 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD2
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD1
( Clock, Reset, 1'b1 , wIOTrigger_Pre, wExeDone_pre1 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD2
( Clock, Reset, 1'b1 , wExeDone_pre1, wExeDone_pre2 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD3
( Clock, Reset, 1'b1 , wExeDone_pre2, wExeDone );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD3
( Clock, Reset, 1'b1 , wExeDone_pre2, wExeDone_pre3 );
 
assign wCommitGranted = wExeDone;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD4
( Clock, Reset, 1'b1 , wExeDone_pre3, wExeDone_pre4 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD5
( Clock, Reset, 1'b1 ,oTMEMDataRequest , ReadInProgress_Delay );
 
assign wExeDone = (ReadInProgress_Delay) ? iTMEMDataAvailable : wExeDone_pre3;
assign wCommitGranted = (ReadInProgress_Delay) ? wExeDone : wExeDone_pre4;
//assign wCommitGranted = wExeDone;
 
endmodule
/Unit_ControlProcessor.v
21,7 → 21,7
***********************************************************************************/
 
 
`define CONTROL_PROCESSOR_OP_WIDTH 5
 
`define CONTROL_PROCESSOR_ADDR_WIDTH 8
`define CONTROL_PROCESSOR_ISSUE_CMD_RNG 24:0
`define CONTROL_PROCESSOR_INSTRUCTION_WIDTH 32
71,8 → 71,8
wire [`CONTROL_PROCESSOR_OP_WIDTH-1:0] wOperation;
reg [`WIDTH-1:0] rResult;
wire [`WIDTH-1:0] wPrevResult;
wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0] wSourceAddr0,wSourceAddr1,wDestination,wPrevDestination;
wire [`WIDTH-1:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
wire [`CONTROL_PROCESSOR_ADDR_WIDTH-1:0] wSourceAddr0,wSourceAddr1,wDestination,wPrevDestination,wIPInitialValue;
wire [`WIDTH-1:0] wSourceData0,wSourceData1,wImmediateValue;
 
 
assign oControlBus = rIssueCommand;
120,7 → 120,7
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Initial( wIPInitialValue + `CONTROL_PROCESSOR_ADDR_WIDTH'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
/Module_MemoryController.v
171,11 → 171,12
.Q( ADR_O )
);
 
wire [`MCU_VPMASK_LEN-1:0] wWE_SelectMask;
assign wWE_SelectMask = wCurrentRequest[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG];
 
 
SELECT_1_TO_N # ( $clog2(`MAX_CORES), `MAX_CORES ) WESEL
(
.Sel(wCurrentRequest[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG]),
.Sel(wWE_SelectMask[$clog2(`MAX_CORES)-1:0]),
.En( ~oFifoEmpty),
.O( WE_O )
);
/Module_OMemInterface.v
1,6 → 1,25
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
//------------------------------------------------------------------------------
module Module_OMemInterface
(
input wire Clock,
15,33 → 34,33
);
wire [2:0] wCurrentWord;
assign WE_O = iWriteEnable;
 
CIRCULAR_SHIFTLEFT_POSEDGE #(3) SHL
(
.Clock(Clock),
.Enable(iWriteEnable),
.Reset(Reset),
.Initial(3'b1),
.O(wCurrentWord)
 
CIRCULAR_SHIFTLEFT_POSEDGE #(3) SHL
(
.Clock(Clock),
.Enable(iWriteEnable),
.Reset(Reset),
.Initial(3'b1),
.O(wCurrentWord)
);
 
MUXFULLPARALELL_3SEL_WALKINGONE # ( `WB_WIDTH ) MUX1
(
.Sel( wCurrentWord ),
MUXFULLPARALELL_3SEL_WALKINGONE # ( `WB_WIDTH ) MUX1
(
.Sel( wCurrentWord ),
.I3(iAddress[31:0]),
.I2(iAddress[63:32]),
.I1(iAddress[95:64]),
.O1( ADR_O )
.I1(iAddress[95:64]),
.O1( ADR_O )
);
MUXFULLPARALELL_3SEL_WALKINGONE # ( `WB_WIDTH ) MUX2
(
.Sel( wCurrentWord ),
MUXFULLPARALELL_3SEL_WALKINGONE # ( `WB_WIDTH ) MUX2
(
.Sel( wCurrentWord ),
.I3(iData[31:0]),
.I2(iData[63:32]),
.I1(iData[95:64]),
.O1( DAT_O )
.I1(iData[95:64]),
.O1( DAT_O )
);
endmodule
/FlowDumper.v
1,23 → 1,23
`include "aDefinitions.v"
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
//`define VP2_TOP( core ) `THEIA_TOP.\VPX[ core ].VP
`define MAX_OMEM_DUMP_SIZE 32
35,11 → 35,11
 
integer RESULT_FILE,VP_LOG,OMEM_LOG,VP_REG_LOG,i;
reg [255:1] VPLogFileName,OMEMLogFileName,RegLogFileName;
 
 
 
 
 
 
 
initial
begin
71,7 → 71,7
OMEM_LOG = $fopen(OMEMLogFileName);
for (i = 0; i < `MAX_OMEM_DUMP_SIZE; i = i +1)
begin
$fwrite(OMEM_LOG,"@%d\t%h\n",i,`THEIA_TOP.VPX[ CVPID ].OMEM.Ram[i]);
$fwrite(OMEM_LOG,"@%02d\t%h\n",i,`THEIA_TOP.VPX[ CVPID ].OMEM.Ram[i]);
end
$fclose(OMEM_LOG);
121,7 → 121,16
endcase
`DWRITE") ");
end
`RS_IO:`DWRITE" IO ");
`RS_IO:
begin
`DWRITE" IO ");
case (`VP_TOP.EXE.II0.oIssueBcast[`ISSUE_SCALE_RNG])
0: `DWRITE" OMWRITE ");
1: `DWRITE" TMREAD ");
default:
`DWRITE" UNKNOWN");
endcase
end
default:
`DWRITE" %b ",`VP_TOP.EXE.II0.oIssueBcast[`ISSUE_RSID_RNG]);
endcase
193,7 → 202,16
`RS_DIV: `DWRITE" DIV ");
`RS_MUL: `DWRITE" MUL ");
`RS_SQRT: `DWRITE" SQRT ");
`RS_IO: `DWRITE" IO ");
`RS_IO:
begin
`DWRITE" IO ");
case (`VP_TOP.EXE.II0.oIssueBcast[`ISSUE_SCALE_RNG])
0: `DWRITE" OMWRITE ");
1: `DWRITE" TMREAD ");
default:
`DWRITE" UNKNOWN");
endcase
end
default:
`DWRITE" %b ",`VP_TOP.EXE.II0.oIssueBcast[`ISSUE_SRC1RS_RNG]);
endcase
205,7 → 223,16
`RS_DIV: `DWRITE" DIV ");
`RS_MUL: `DWRITE" MUL ");
`RS_SQRT: `DWRITE" SQRT ");
`RS_IO: `DWRITE" IO ");
`RS_IO:
begin
`DWRITE" IO ");
case (`VP_TOP.EXE.II0.oIssueBcast[`ISSUE_SCALE_RNG])
0: `DWRITE" OMWRITE ");
1: `DWRITE" TMREAD ");
default:
`DWRITE" UNKNOWN");
endcase
end
default:
`DWRITE" %b ",`VP_TOP.EXE.II0.oIssueBcast[`ISSUE_SRC0RS_RNG]);
endcase
327,7 → 354,16
`RS_DIV: `DWRITE" DIV ");
`RS_MUL: `DWRITE" MUL ");
`RS_SQRT: `DWRITE" SQRT ");
`RS_IO: `DWRITE" IO ");
`RS_IO:
begin
`DWRITE" IO ");
case (`VP_TOP.EXE.II0.oIssueBcast[`ISSUE_SCALE_RNG])
0: `DWRITE" OMWRITE ");
1: `DWRITE" TMREAD ");
default:
`DWRITE" UNKNOWN");
endcase
end
default:
`DWRITE" %b ",`VP_TOP.EXE.II1.oIssueBcast[`ISSUE_SRC1RS_RNG]);
endcase
481,6 → 517,22
`DWRITE" %h %h %h \n",`VP_TOP.EXE.SQRT_STA.oCommitData[`COMMIT_X_RNG],`VP_TOP.EXE.SQRT_STA.oCommitData[`COMMIT_Y_RNG], `VP_TOP.EXE.SQRT_STA.oCommitData[`COMMIT_Z_RNG]);
end
//-----------------------------------------------------------------
if (`VP_TOP.EXE.IO_STA.iCommitGranted)
begin
`DWRITE"\n%dns\t VP[%d] COMMIT IO TMREAD R[%d]",$time,`VP_TOP.iVPID-1,`VP_TOP.EXE.IO_STA.oCommitData[`COMMIT_DST_RNG]);
case ( `VP_TOP.EXE.IO_STA.oCommitData[`COMMIT_WE_RNG] )
3'b000: `DWRITE".nowrite ");
3'b001: `DWRITE".z ");
3'b010: `DWRITE".y ");
3'b100: `DWRITE".x ");
3'b111: `DWRITE".xyz ");
default:
`DWRITE" %b ",`VP_TOP.EXE.IO_STA.oCommitData[`COMMIT_WE_RNG]);
endcase
`DWRITE" %h %h %h \n",`VP_TOP.EXE.IO_STA.oCommitData[`COMMIT_X_RNG],`VP_TOP.EXE.IO_STA.oCommitData[`COMMIT_Y_RNG], `VP_TOP.EXE.IO_STA.oCommitData[`COMMIT_Z_RNG]);
end
//-----------------------------------------------------------------
 
end //always
 
/Module_TMemInterface.v
0,0 → 1,144
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
//------------------------------------------------------------------------------
//
//
//
//
// Remarks:
// * TMI sends 3 read requests to the TMEM memory. The read requests has
// read address equal iAddress[X_RNG], iAddress[Y_RNG] and iAddress[Z_RNG]
// respectively.
// * TMI will set oData == 1 once the bus cycle is complete (this can take
// multiple clock cycles depending on the crossbar traffic
// * TMI needs to have iEnable == 1 for the entire duration of the read bus cycle,
// if the iEnable is set to zero before the bus transaction is complete then
// read operation will fail and the read data will not be presented into
// the oData output signal.
//
//------------------------------------------------------------------------------
module Module_TMemInterface
(
input wire Clock,
input wire Reset,
input wire iEnable,
input wire [`DATA_ROW_WIDTH-1:0] iAddress,
output wire [`DATA_ROW_WIDTH-1:0] oData,
output wire oDone,
 
input wire ACK_I,
input wire GNT_I,
input wire [`WB_WIDTH-1:0 ] DAT_I,
 
//WB Output Signals
output wire [`WB_WIDTH-1:0 ] ADR_O,
output wire WE_O,
output wire STB_O,
output wire CYC_O
 
 
);
 
wire [3:0] wCurrentWord;
wire wDone;
assign oDone = wDone;// & iEnable;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_DONE
(
.Clock(Clock),
.Reset(Reset),
.Enable( 1'b1 ),
.D(wCurrentWord[3]),
.Q(wDone)
);
 
 
//wire wShiftNow;
assign WE_O = 1'b0; //we only read
assign CYC_O = iEnable;
 
 
 
wire[2:0] wLatchNow;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 3 ) FFD_LATHCNOW
(
.Clock(Clock),
.Reset(Reset),
.Enable( 1'b1 ),
.D(wCurrentWord[2:0]),
.Q(wLatchNow)
);
 
 
 
SHIFTLEFT_POSEDGE #(4) SHL
(
.Clock(Clock),
.Enable(iEnable & GNT_I),//wShiftNow),
.Reset(Reset | ~iEnable ),
.Initial(4'b1),
.O(wCurrentWord)
);
 
MUXFULLPARALELL_3SEL_WALKINGONE # ( `WB_WIDTH ) MUX1
(
.Sel( wCurrentWord[2:0] ),
.I3(iAddress[31:0]),
.I2(iAddress[63:32]),
.I1(iAddress[95:64]),
.O1( ADR_O )
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFDX
(
.Clock(Clock),
.Reset(Reset),
.Enable( wLatchNow[0] & GNT_I),
.D(DAT_I),
.Q(oData[95:64])
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFDY
(
.Clock(Clock),
.Reset(Reset),
.Enable( wLatchNow[1] & GNT_I),
.D(DAT_I),
.Q(oData[63:32])
);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFDZ
(
.Clock(Clock),
.Reset( Reset ),
.Enable( wLatchNow[2] & GNT_I),
.D(DAT_I),
.Q(oData[31:0])
);
 
endmodule
//--------------------------------------------------------------------------
/ControlCodeDumper.v
1,5 → 1,5
`include "aDefinitions.v"
 
`include "aDefinitions.v"
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
18,133 → 18,157
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
module ContolCode_Dumper;
//wait( `CP_TOP.Reset == 0 );
always @ ( posedge `CP_TOP.Clock )
begin
case (`CP_TOP.wOperation)
//-------------------------------------
`CONTROL_PROCESSOR_OP_COPYBLOCK:
begin
$write("\n%dns CP: COPYBLOCK DSTID: %d BLKLEN: %d TAG: %d DSTOFF: %h SRCOFF: %h\n\n",$time,
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_BLKLEN_RNG],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCK_TAG_BIT],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_DSTOFF_RNG],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_SRCOFF_RNG]);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_DELIVER_COMMAND:
begin
$write("%dns CP: DELIVER_COMMAND VP[%d] ",$time,
`CP_TOP.wDestination);
case (`CP_TOP.wSourceAddr1)
`VP_COMMAND_START_MAIN_THREAD: $write( " START_MAIN_THREAD ");
`VP_COMMAND_STOP_MAIN_THREAD: $write( " STOP_MAIN_THREAD ");
***********************************************************************************/
 
//`define DEBUG_TO_STDOUT 1
 
`ifdef DEBUG_TO_STDOUT
`define DWRITE $write(
`else
`define DWRITE $fwrite(CP_LOG,
`endif
 
 
module ContolCode_Dumper;
//wait( `CP_TOP.Reset == 0 );
integer CP_LOG;
reg [255:1] CPLogFileName;
 
initial
begin
//Open output file
CP_LOG = $fopen("cp.log");
end
 
 
 
 
 
always @ ( posedge `CP_TOP.Clock )
begin
case (`CP_TOP.wOperation)
//-------------------------------------
`CONTROL_PROCESSOR_OP_COPYBLOCK:
begin
`DWRITE"\n%dns CP: COPYBLOCK DSTID: %d BLKLEN: %d TAG: %d DSTOFF: %h SRCOFF: %h\n\n",$time,
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_VPMASK_RNG],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_BLKLEN_RNG],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCK_TAG_BIT],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_DSTOFF_RNG],
`CP_TOP.oCopyBlockCommand[`MCU_COPYMEMBLOCKCMD_SRCOFF_RNG]);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_DELIVER_COMMAND:
begin
`DWRITE"%dns CP: DELIVER_COMMAND VP[%d] ",$time,
`CP_TOP.wDestination);
case (`CP_TOP.wSourceAddr1)
`VP_COMMAND_START_MAIN_THREAD: `DWRITE " START_MAIN_THREAD ");
`VP_COMMAND_STOP_MAIN_THREAD: `DWRITE " STOP_MAIN_THREAD ");
endcase
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_NOP:
begin
$write("%dns CP: NOP\n",$time);
end
//-------------------------------------
begin
`DWRITE"%dns CP: NOP\n",$time);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_EXIT:
begin
$write("%dns CP: EXIT\n",$time);
begin
`DWRITE"%dns CP: EXIT\n",$time);
//$stop;
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_ADD:
begin
if (`CP_TOP.rWriteEnable)
$write("%dns CP: ADD R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
begin
if (`CP_TOP.rWriteEnable)
`DWRITE"%dns CP: ADD R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_SUB:
begin
$write("%dns CP: SUB R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
begin
`DWRITE"%dns CP: SUB R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_AND:
begin
$write("%dns CP: AND R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
begin
`DWRITE"%dns CP: AND R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_OR:
begin
$write("%dns CP: OR R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
begin
`DWRITE"%dns CP: OR R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_SHL:
begin
$write("%dns CP: SHL R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
begin
`DWRITE"%dns CP: SHL R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_SHR:
begin
$write("%dns CP: SHR R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
begin
`DWRITE"%dns CP: SHR R[%d] R[%d]{%h} R[%d]{%h} = %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0,`CP_TOP.rResult);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_BLE:
begin
$write("%dns CP: BLE\n",$time);
`DWRITE"%dns CP: BLE\n",$time);
end
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_BL:
begin
$write("%dns CP: BL\n",$time);
`DWRITE"%dns CP: BL\n",$time);
end
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_BG:
begin
$write("%dns CP: BG\n",$time);
`DWRITE"%dns CP: BG\n",$time);
end
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_BGE:
begin
$write("%dns CP: BGE\n",$time);
end
`DWRITE"%dns CP: BGE\n",$time);
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_BEQ:
begin
$write("%dns CP: BEQ %d, R[%d] {%h} R[%d] {%h}\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0);
`DWRITE"%dns CP: BEQ %d, R[%d] {%h} R[%d] {%h}\n",$time,`CP_TOP.wDestination,`CP_TOP.wSourceAddr1,`CP_TOP.wSourceData1,`CP_TOP.wSourceAddr0,`CP_TOP.wSourceData0);
end
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_BNE:
begin
$write("%dns CP: BNE\n",$time);
`DWRITE"%dns CP: BNE\n",$time);
end
end
//-------------------------------------
`CONTROL_PROCESSOR_OP_BRANCH:
begin
$write("%dns CP: BRANCH %h\n",$time,`CP_TOP.wDestination );
end
//-------------------------------------
`CONTROL_PROCESSOR_ASSIGN:
begin
$write("%dns CP: ASSIGN R[%d] I(%h)= %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wImmediateValue,`CP_TOP.rResult);
`DWRITE"%dns CP: BRANCH %h\n",$time,`CP_TOP.wDestination );
end
//-------------------------------------
`CONTROL_PROCESSOR_ASSIGN:
begin
`DWRITE"%dns CP: ASSIGN R[%d] I(%h)= %h\n",$time,`CP_TOP.wDestination,`CP_TOP.wImmediateValue,`CP_TOP.rResult);
end
//-------------------------------------
default:
begin
end
//-------------------------------------
endcase
end
endmodule
 
//-------------------------------------
endcase
end
endmodule
 
/Module_RegisterFile.v
39,18 → 39,23
 
parameter DATA_CHANNEL_WIDTH = DATA_WIDTH / 3;
 
wire wEnableFrameOffsetOverwrite,wEnableControlRegOverwrite;
wire wEnableFrameOffsetOverwrite,wEnableControlRegOverwrite;
wire [`DATA_ADDRESS_WIDTH-1:0] wIndexRegister;
wire [`WIDTH-1:0] wDataX,wDataZ;
 
assign wEnableFrameOffsetOverwrite = (iWriteAddress == `SPR_CONTROL1) ? 1'b1 : 1'b0;
assign wEnableControlRegOverwrite = (iWriteAddress == `SPR_CONTROL0) ? 1'b1 : 1'b0;
assign wEnableControlRegOverwrite = (iWriteAddress == `SPR_CONTROL0) ? 1'b1 : 1'b0;
assign wDataX = iData[`X_RNG];
assign wDataZ = iData[`Z_RNG];
//This stores the frame offset register
 
//This stores the frame offset register
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) FDD_FRAMEOFFSET
( Clock, Reset, (wEnableFrameOffsetOverwrite & iWriteEnable[2]) ,iData[`X_RNG], oFrameOffset );
( Clock, Reset, (wEnableFrameOffsetOverwrite & iWriteEnable[2]) ,wDataX[`DATA_ADDRESS_WIDTH-1:0], oFrameOffset );
 
//This stores the index register
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) FDD_INDEXREGISTER
( Clock, Reset, (wEnableFrameOffsetOverwrite & iWriteEnable[0]) ,iData[`Z_RNG], wIndexRegister );
( Clock, Reset, (wEnableFrameOffsetOverwrite & iWriteEnable[0]) ,wDataZ[`DATA_ADDRESS_WIDTH-1:0], wIndexRegister );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FDD_CONTROLREGISTER
( Clock, Reset, (wEnableControlRegOverwrite & iWriteEnable[0]) ,iData[`Z_RNG], oThreadControlRegister );
/Module_BusArbitrer.v
0,0 → 1,80
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
 
 
module Module_BusArbitrer
(
input wire Clock,
input wire Reset,
 
input wire [`MAX_CORES-1:0] iRequest,
output wire [`MAX_CORES-1:0] oGrant,
output wire [`MAX_CORE_BITS-1:0] oBusSelect
);
 
wire[`MAX_CORES-1:0] wCurrentMasterMask;
wire[`MAX_CORE_BITS-1:0] wCurrentBusMaster;
wire wCurrentRequest;
 
//Just one requester can have the bus at a given
//point in time, the mask makes sure this happens
genvar i;
generate
for (i = 0; i < `MAX_CORES; i = i +1)
begin : ARB
assign oGrant[i] = iRequest[i] & wCurrentMasterMask[i];
end
endgenerate
 
 
//When a requester relinquishes the bus (by negating its [iRequest] signal),
//the switch is turned to the next position
//So while iRequest == 1 the ciruclar list will not move
 
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES) SHL_A
(
.Clock( Clock ),
.Enable( ~wCurrentRequest ),
.Reset( Reset ),
.Initial(`MAX_CORES'b1),
.O( wCurrentMasterMask )
);
 
assign oBusSelect = wCurrentBusMaster;
 
//Poll the current request
assign wCurrentRequest = iRequest[ wCurrentBusMaster ];
 
 
UPCOUNTER_POSEDGE # (`MAX_CORE_BITS ) UP1
(
.Clock( Clock ),
.Reset( Reset ),
.Initial( `MAX_CORE_BITS'd0 ),
.Enable(~wCurrentRequest),
.Q(wCurrentBusMaster)
);
 
endmodule
/Theia.v
19,111 → 19,148
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
//--------------------------------------------------------
 
module THEIA
(
input wire Clock,
input wire Reset,
input wire iEnable,
input wire [31:0] iMemReadData, //Data read from Main memory
input wire iMemDataAvailable,
output wire [31:0] oMemReadAddress,
output wire oMEM_ReadRequest
 
);
 
 
wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteAddress;
wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteData;
wire [`MAX_CORES-1:0] wMCU_2_VP_InstructionWriteEnable;
wire [`MCU_TAG_SIZE-1:0] wMCU_2_VP_Tag;
wire wMCU_2_VP_STB;
wire wMCU_2_VP_Cyc;
wire wMCU_2_VP_Mst;
wire [`MAX_CORES-1:0] wVP_2_MCU_ACK;
wire wVP_Slave_ACK;
wire [`MCU_REQUEST_SIZE-1:0] wCP_2MCU_BlockCopyCommand;
wire[`CBC_BUS_WIDTH-1:0] wCP_VP__ControlCommandBus;
wire wMCU_2_CP__FIFOEmpty;
//--------------------------------------------------------
 
module THEIA
(
input wire Clock,
input wire Reset,
input wire iEnable,
input wire [31:0] iMemReadData, //Data read from Main memory
input wire iMemDataAvailable,
output wire [31:0] oMemReadAddress,
output wire oMEM_ReadRequest,
input wire [`WB_WIDTH-1:0] TMDAT_I,
input wire [`WB_WIDTH-1:0] TMADR_I,
input wire TMWE_I,
input wire [`MAX_TMEM_BANKS-1:0] TMSEL_I
 
);
 
 
wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteAddress;
wire [`WB_WIDTH-1:0] wMCU_2_VP_InstructionWriteData;
wire [`MAX_CORES-1:0] wMCU_2_VP_InstructionWriteEnable;
wire [`MCU_TAG_SIZE-1:0] wMCU_2_VP_Tag;
wire wMCU_2_VP_STB;
wire wMCU_2_VP_Cyc;
wire wMCU_2_VP_Mst;
wire [`MAX_CORES-1:0] wVP_2_MCU_ACK;
wire wVP_Slave_ACK;
wire [`MCU_REQUEST_SIZE-1:0] wCP_2MCU_BlockCopyCommand;
wire[`CBC_BUS_WIDTH-1:0] wCP_VP__ControlCommandBus;
wire wMCU_2_CP__FIFOEmpty;
wire wOMem_WE[`MAX_CORES-1:0];
wire [`WB_WIDTH-1:0] wOMEM_Address[`MAX_CORES-1:0];
wire [`WB_WIDTH-1:0] wOMEM_Dat[`MAX_CORES-1:0];
 
 
//////////////////////////////////////////////
//
// The control processor
//
//////////////////////////////////////////////
ControlProcessor CP
(
.Clock( Clock ),
.Reset( Reset ),
.oControlBus( wCP_VP__ControlCommandBus ),
.iMCUFifoEmpty( wMCU_2_CP__FIFOEmpty ),
.oCopyBlockCommand( wCP_2MCU_BlockCopyCommand )
);
 
//////////////////////////////////////////////
//
// The control processor
//
//////////////////////////////////////////////
assign wVP_Slave_ACK = wVP_2_MCU_ACK[0] | wVP_2_MCU_ACK[1] | wVP_2_MCU_ACK[2] | wVP_2_MCU_ACK[3];
 
MemoryController #(`MAX_CORES) MCU
(
.Clock( Clock ),
.Reset( Reset ),
.iRequest( wCP_2MCU_BlockCopyCommand ),
.oMEM_ReadAddress( oMemReadAddress ),
.oMEM_ReadRequest( oMEM_ReadRequest ),
.oFifoEmpty( wMCU_2_CP__FIFOEmpty ),
.iMEM_ReadData( iMemReadData ),
.iMEM_DataAvailable( iMemDataAvailable ),
.DAT_O( wMCU_2_VP_InstructionWriteData ),
.ADR_O( wMCU_2_VP_InstructionWriteAddress ),
.STB_O( wMCU_2_VP_STB ),
.WE_O( wMCU_2_VP_InstructionWriteEnable ),
.TAG_O( wMCU_2_VP_Tag ),
.CYC_O( wMCU_2_VP_Cyc ),
.MST_O( wMCU_2_VP_Mst ),
.ACK_I( wVP_Slave_ACK )
);
 
//////////////////////////////////////////////
//
// The vector processors
//
//////////////////////////////////////////////
wire [`WB_WIDTH-1:0] wOMEM_Dat[`MAX_CORES-1:0];
 
 
 
 
//CROSS-BAR wires
 
 
wire [`MAX_TMEM_BANKS-1:0] wTMemWriteEnable;
wire [(`MAX_TMEM_BANKS*`WB_WIDTH)-1:0] wCrossBarDataRow; //Horizontal grid Buses comming from each bank
wire [(`MAX_CORES*`WB_WIDTH)-1:0] wCrossBarDataCollumn; //Vertical grid buses comming from each core.
wire [(`MAX_CORES*`WB_WIDTH)-1:0] wCrossBarAdressCollumn; //Vertical grid buses comming from each core. (physical addr).
wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0];
 
 
 
 
 
 
//////////////////////////////////////////////
//
// The control processor
//
//////////////////////////////////////////////
ControlProcessor CP
(
.Clock( Clock ),
.Reset( Reset ),
.oControlBus( wCP_VP__ControlCommandBus ),
.iMCUFifoEmpty( wMCU_2_CP__FIFOEmpty ),
.oCopyBlockCommand( wCP_2MCU_BlockCopyCommand )
);
 
//////////////////////////////////////////////
//
// The control processor
//
//////////////////////////////////////////////
assign wVP_Slave_ACK = wVP_2_MCU_ACK[0] | wVP_2_MCU_ACK[1] | wVP_2_MCU_ACK[2] | wVP_2_MCU_ACK[3];
 
MemoryController #(`MAX_CORES) MCU
(
.Clock( Clock ),
.Reset( Reset ),
.iRequest( wCP_2MCU_BlockCopyCommand ),
.oMEM_ReadAddress( oMemReadAddress ),
.oMEM_ReadRequest( oMEM_ReadRequest ),
.oFifoEmpty( wMCU_2_CP__FIFOEmpty ),
.iMEM_ReadData( iMemReadData ),
.iMEM_DataAvailable( iMemDataAvailable ),
.DAT_O( wMCU_2_VP_InstructionWriteData ),
.ADR_O( wMCU_2_VP_InstructionWriteAddress ),
.STB_O( wMCU_2_VP_STB ),
.WE_O( wMCU_2_VP_InstructionWriteEnable ),
.TAG_O( wMCU_2_VP_Tag ),
.CYC_O( wMCU_2_VP_Cyc ),
.MST_O( wMCU_2_VP_Mst ),
.ACK_I( wVP_Slave_ACK )
);
 
//////////////////////////////////////////////
//
// The vector processors
//
//////////////////////////////////////////////
genvar i;
generate
for (i = 0; i < `MAX_CORES; i = i +1)
begin : VPX
VectorProcessor VP
(
.Clock( Clock ),
.Reset( Reset ),
.iEnable( iEnable ),
.iVPID( i+1 ),
.iCpCommand( wCP_VP__ControlCommandBus ),
.MCU_STB_I( wMCU_2_VP_STB ),
.MCU_WE_I( wMCU_2_VP_InstructionWriteEnable[i] ),
.MCU_DAT_I( wMCU_2_VP_InstructionWriteData ),
.MCU_ADR_I( wMCU_2_VP_InstructionWriteAddress ),
.MCU_TAG_I( wMCU_2_VP_Tag ),
.MCU_ACK_O( wVP_2_MCU_ACK[i] ),
.MCU_MST_I( wMCU_2_VP_Mst ),
.MCU_CYC_I( wMCU_2_VP_Cyc ),
.OMEM_WE( wOMem_WE[i] ),
.OMEM_ADDR( wOMEM_Address[i] ),
.OMEM_DATA( wOMEM_Dat[i] )
 
);
begin : VPX
VectorProcessor VP
(
.Clock( Clock ),
.Reset( Reset ),
.iEnable( iEnable ),
.iVPID( i+1 ),
.iCpCommand( wCP_VP__ControlCommandBus ),
.MCU_STB_I( wMCU_2_VP_STB ),
.MCU_WE_I( wMCU_2_VP_InstructionWriteEnable[i] ),
.MCU_DAT_I( wMCU_2_VP_InstructionWriteData ),
.MCU_ADR_I( wMCU_2_VP_InstructionWriteAddress ),
.MCU_TAG_I( wMCU_2_VP_Tag ),
.MCU_ACK_O( wVP_2_MCU_ACK[i] ),
.MCU_MST_I( wMCU_2_VP_Mst ),
.MCU_CYC_I( wMCU_2_VP_Cyc ),
.OMEM_WE( wOMem_WE[i] ),
.OMEM_ADDR( wOMEM_Address[i] ),
.OMEM_DATA( wOMEM_Dat[i] ),
.TMEM_DAT_I( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ] ),
.TMEM_ADR_O( wTMemReadAdr[i] ),
.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
.TMEM_GNT_I( wTMEM_2_Core__Grant[i] )
 
);
//////////////////////////////////////////////
//
// The OMEM
//
//////////////////////////////////////////////
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, `OMEM_SIZE ) OMEM
(
.Clock( Clock ),
131,12 → 168,115
.iWriteAddress( wOMEM_Address[i] ),
.iDataIn( wOMEM_Dat[i] ),
.iReadAddress0( wOMEM_Address[i] )
//.oDataOut0( wOMEM_Dat[i] )
);
 
);
MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_TMEM_BANKS,`MAX_TMEM_BITS) MUXG1
(
.in_bus( wCrossBarDataRow ),
.sel( wCoreBankSelect[ i ][0+:`MAX_TMEM_BITS] ),
.out( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ] )
);
 
//If there are "n" banks, memory location "X" would reside in bank number X mod n.
//X mod 2^n == X & (2^n - 1)
assign wCoreBankSelect[i] = (wTMemReadAdr[i] & (`MAX_TMEM_BANKS-1));
 
//Each core has 1 bank request slot
//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
//be 1 at any given point in time. All bits zero means,
//we are not requesting to read from any memory bank.
SELECT_1_TO_N # ( `WIDTH, `MAX_TMEM_BANKS ) READDRQ
(
.Sel(wCoreBankSelect[ i]),
.En(wCORE_2_TMEM__Req[i]),
.O(wBankReadRequest[i])
);
 
//The address coming from the core is virtual adress, meaning it assumes linear
//address space, however, since memory is interleaved in a n-way memory we transform
//virtual adress into physical adress (relative to the bank) like this
//fadr = vadr / n = vadr >> log2(n)
 
assign wCrossBarAdressCollumn[(i*`WB_WIDTH)+:`WB_WIDTH] = (wTMemReadAdr[i] >> `MAX_CORE_BITS);
 
//Connect the granted signal to Arbiter of the Bank we want to read from
assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
 
end // for
endgenerate
 
 
endmodule
endgenerate
 
 
 
 
 
 
 
 
////////////// CROSS-BAR INTERCONECTION//////////////////////////
 
 
SELECT_1_TO_N # ( `MAX_TMEM_BANKS, `MAX_TMEM_BANKS ) TMWE_SEL
(
.Sel(TMSEL_I),
.En(TMWE_I),
.O(wTMemWriteEnable)
);
 
genvar Core,Bank;
generate
for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1)
begin : BANK
 
//The memory bank itself
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM
(
.Clock( Clock ),
.iWriteEnable( wTMemWriteEnable[Bank] ),
.iWriteAddress( TMADR_I ),
.iDataIn( TMDAT_I ),
.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid
.oDataOut0( wCrossBarDataRow[(`WB_WIDTH*Bank)+:`WB_WIDTH] ) //Connect to the Row of the grid
);
//Arbiter will Round-Robin Cores attempting to read from the same Bank
//at a given point in time
wire [`MAX_CORES-1:0] wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0];
Module_BusArbitrer ARB_TMEM
(
.Clock( Clock ),
.Reset( Reset ),
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_CORES ) FFD_GNT
(
.Clock(Clock),
.Reset(Reset),
.Enable( 1'b1 ),
.D(wBankReadGrantedDelay[Bank]),
.Q(wBankReadGranted[Bank])
);
 
MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_CORES,`MAX_CORE_BITS) MUXG2
(
.in_bus( wCrossBarAdressCollumn ),
.sel( wCurrentCoreSelected[ Bank ] ),
.out( wCrossBarAddressRow[ Bank ] )
);
end
endgenerate
 
////////////// CROSS-BAR INTERCONECTION//////////////////////////
 
endmodule
/Module_OperandModifiers.v
32,7 → 32,7
output wire [2:0] oScale,
input wire[`ISSUE_SRCTAG_SIZE-1:0] iTag,
input wire[`COMMIT_PACKET_SIZE-1:0] iData,
output wire[`COMMIT_PACKET_SIZE-1:0] oData,
output wire[`DATA_ROW_WIDTH-1:0] oData,
output wire[3:0] oRsID,
input wire[3:0] iKey,
output wire oRequest,
76,8 → 76,8
FFD_POSEDGE_SYNCRONOUS_RESET # ( `ISSUE_SRCTAG_SIZE ) FFD1
( Clock, Reset, iKeep ,iTag , oTag );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `COMMIT_PACKET_SIZE ) FFD2
( Clock, Reset, wMatch ,iData , oData );
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2
( Clock, Reset, wMatch ,iData[`DATA_ROW_WIDTH-1:0] , oData );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD3
( Clock, Reset, iKeep ,iRs , oRsID );
258,15 → 258,15
assign wRequest[0] = 1'b0;
ModfierQueue Q0
(
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs0 ),
.oRsID( wOutRs0 ),
.iTag( wInTag0 ),
.iScale( wInScale0 ),
.oScale( wOutScale0 ),
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs0 ),
.oRsID( wOutRs0 ),
.iTag( wInTag0 ),
.iScale( wInScale0 ),
.oScale( wOutScale0 ),
.iKeep( wKeep[0] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iData( iCommitBus ),
.oTag( wOutTag0 ),
.oData( wData0 ),
278,15 → 278,15
 
ModfierQueue Q1
(
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs1 ),
.oRsID( wOutRs1 ),
.iTag( wInTag1 ),
.iScale( wInScale1 ),
.oScale( wOutScale1 ),
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs1 ),
.oRsID( wOutRs1 ),
.iTag( wInTag1 ),
.iScale( wInScale1 ),
.oScale( wOutScale1 ),
.iKeep( wKeep[1] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iData( iCommitBus ),
.oTag( wOutTag1 ),
.oData( wData1 ),
298,15 → 298,15
 
ModfierQueue Q2
(
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs2 ),
.iTag( wInTag2 ),
.iScale( wInScale2 ),
.oScale( wOutScale2 ),
.oRsID( wOutRs2 ),
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs2 ),
.iTag( wInTag2 ),
.iScale( wInScale2 ),
.oScale( wOutScale2 ),
.oRsID( wOutRs2 ),
.iKeep( wKeep[2] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iData( iCommitBus ),
.oTag( wOutTag2 ),
.oData( wData2 ),
317,15 → 317,15
 
ModfierQueue Q3
(
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs3 ),
.oRsID( wOutRs3 ),
.iTag( wInTag3 ),
.iScale( wInScale3 ),
.oScale( wOutScale3 ),
.Clock( Clock ),
.Reset( Reset ),
.iRs( wInRs3 ),
.oRsID( wOutRs3 ),
.iTag( wInTag3 ),
.iScale( wInScale3 ),
.oScale( wOutScale3 ),
.iKeep( wKeep[3] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iKey( iCommitBus[`COMMIT_RSID_RNG] ),
.iData( iCommitBus ),
.oTag( wOutTag3 ),
.oData( wData3 ),
339,7 → 339,7
(
.Clock( Clock ),
.Reset( Reset ),
.iRequest0( wIssue),
.iRequest0( wIssue ),
.iRequest1( wRequest[1] & ~wIssue ), //Issues from IIU have priority
.iRequest2( wRequest[2] & ~wIssue ), //Issues from IIU have priority
.iRequest3( wRequest[3] & ~wIssue ), //Issues from IIU have priority,
355,47 → 355,47
 
 
wire[3:0] wBusSelector;
DECODER_ONEHOT_2_BINARY DECODER
DECODER_ONEHOT_2_BINARY # (.OUTPUT_WIDTH(4) )DECODER
(
.iIn( {1'b0,wGranted} ),
.iIn( {2'b0,wGranted} ),
.oOut( wBusSelector )
);
 
MUXFULLPARALELL_3SEL_GENERIC # (`ISSUE_SRCTAG_SIZE + `DATA_ROW_WIDTH ) MUX
(
.Sel(wBusSelector),
.I1( {`ISSUE_SRCTAG_SIZE'b0,`DATA_ROW_WIDTH'b0} ),
.I2( {wIssueBus[`ISSUE_SRC0_TAG_RNG],wIssueBus[`ISSUE_SRC0_DATA_RNG]} ),
.I3( {wOutTag0,wData0} ),
.I4( {wOutTag1,wData1} ),
.I5( {wOutTag2,wData2} ),
.I6( {wOutTag3,wData3} ),
.O1( wSrcA_Pre )
.Sel( wBusSelector[2:0] ),
.I1( {`ISSUE_SRCTAG_SIZE'b0,`DATA_ROW_WIDTH'b0} ),
.I2( {wIssueBus[`ISSUE_SRC0_TAG_RNG],wIssueBus[`ISSUE_SRC0_DATA_RNG]} ),
.I3( {wOutTag0,wData0} ),
.I4( {wOutTag1,wData1} ),
.I5( {wOutTag2,wData2} ),
.I6( {wOutTag3,wData3} ),
.O1( wSrcA_Pre )
);
MUXFULLPARALELL_3SEL_GENERIC # ( 4 ) MUX2
(
.Sel(wBusSelector),
.I1( 4'b0 ),
.I2( 4'b0 ),
.I3( wOutRs0 ),
.I4( wOutRs1 ),
.I5( wOutRs2 ),
.I6( wOutRs3 ),
.O1( wOutRsCommit )
.Sel(wBusSelector[2:0] ),
.I1( 4'b0 ),
.I2( 4'b0 ),
.I3( wOutRs0 ),
.I4( wOutRs1 ),
.I5( wOutRs2 ),
.I6( wOutRs3 ),
.O1( wOutRsCommit )
);
MUXFULLPARALELL_3SEL_GENERIC # ( 3 ) MUX3
(
.Sel(wBusSelector),
.I1( 3'b0 ),
.I2( 3'b0 ),
.I3( wOutScale0 ),
.I4( wOutScale1 ),
.I5( wOutScale2 ),
.I6( wOutScale3 ),
.O1( wSrcA_Scale )
.Sel( wBusSelector[2:0] ),
.I1( 3'b0 ),
.I2( 3'b0 ),
.I3( wOutScale0 ),
.I4( wOutScale1 ),
.I5( wOutScale2 ),
.I6( wOutScale3 ),
.O1( wSrcA_Scale )
);
wire [`DATA_ROW_WIDTH-1:0] wModIssueSource0, wModIssueSource1;
/Module_InstructionIssue.v
97,11 → 97,16
reg rTagMemoryWE,rTagMemOwner,rIssueNow,rIncrementPC,rPopFifo,rBypassFifo,rUseForwardedData;
reg rSetPCBranchTaken;
wire wBranchWithDependency;
wire wIO_Operation_TMWRITE;
 
 
 
wire wMtHasOnceMoreTimeSlot,wEnabled_Delay;
wire wIO_Operation;
assign wIO_Operation = (~wOp[0] & wOp[1] & wOp[2] & ~wOp[3]);
assign wIO_Operation = (~wOp[0] & wOp[1] & wOp[2] & ~wOp[3]);
 
assign wIO_Operation_TMWRITE = wIO_Operation && (iInstruction0[`INST_SCOP_RNG] == `IO_OPERATION_OMWRITE);
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD123
( Clock, Reset, 1'b1 , iEnable , wEnabled_Delay );
 
147,7 → 152,7
value of PC will get update the next clock cycle, and another clock cycle
after that the instruction will get updated.
1- If there is data waiting on the commit bus input port this cycle,
then do not queue this data into the FIFO but instead set
then do not queue this data into the input FIFO but instead set
set the score board write enable to 1, set the wSBWriteAddress
to the CommitPacket Destination range and update the score board
bit to zero, so than in the next state the score board bit associated
174,7 → 179,7
rNextState = `II_ISSUE_REQUEST_WITH_DATA_FWD;
else if (~wCommitBusInputFifo_Empty)
rNextState = `II_FIFO_UPDATE;
else if ( wReservationStationBusy | (iMtEnabled & ~wMtHasOnceMoreTimeSlot))
else if ( wReservationStationBusy | (iMtEnabled & ~wMtHasOnceMoreTimeSlot) /*| wIOWrite_Waiting_for_OMRead*/ )
rNextState = `II_FETCH_INSTRUCTION;
else
rNextState = `II_ISSUE_REQUEST;
185,7 → 190,7
//Then we shall stall the machine...
`II_ISSUE_REQUEST:
begin
rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation;
rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation_TMWRITE;
rTagMemOwner = `TAGMEM_OWNER_ISSUE;
rIssueNow = iEnable;
rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
211,7 → 216,7
*/
`II_ISSUE_REQUEST_WITH_DATA_FWD:
begin
rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation;
rTagMemoryWE = ~iInstruction0[`INST_BRANCH_BIT] & ~wIO_Operation_TMWRITE;
rTagMemOwner = `TAGMEM_OWNER_ISSUE;
rIssueNow = iEnable;
rIncrementPC = (iInstruction0[`INST_BRANCH_BIT] & ~wBranchWithDependency & iEnable);
325,13 → 330,16
wire[3:0] wReservationStation;
 
`ifdef ADDRESSING_MODES_DISABLED
//There a two possible ways to update the Score board. The SB can be update by the operation we just commited: iInstruction0
//or the SB can be updated by the value comming from the wResultFifoData
assign wSBWriteAddress
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:iInstruction0[`INST_DST_RNG])
: wResultFifoData[`COMMIT_DST_RNG];
`else
//There a two possible ways to update the Score board. The SB can be update by the operation we just commited: iInstruction0
//or the SB can be updated by the value comming from the wResultFifoData
assign wSBWriteAddress
= (rTagMemOwner == `TAGMEM_OWNER_ISSUE) ? ((rBypassFifo)?iResultBcast[`COMMIT_DST_RNG]:wDestinationIndex)
: wResultFifoData[`COMMIT_DST_RNG];
557,7 → 565,7
((iInstruction0[`INST_CODE_RNG] == `OPERATION_ADD ) && (iRStationBusy[ 0 ] && iRStationBusy[ 1 ])) ||
((iInstruction0[`INST_CODE_RNG] == `OPERATION_DIV ) && iRStationBusy[ 2 ]) ||
((iInstruction0[`INST_CODE_RNG] == `OPERATION_MUL ) && iRStationBusy[ 3 ]) ||
((iInstruction0[`INST_CODE_RNG] == `OPERATION_OUT ) && iRStationBusy[ 6 ])
((iInstruction0[`INST_CODE_RNG] == `OPERATION_IO ) && iRStationBusy[ 6 ])
);
 
assign wBranchWithDependency = (iInstruction0[`INST_BRANCH_BIT] && (wSource0_Station != 0 || wSource1_Station != 0));
564,6 → 572,9
 
 
assign wOp = iInstruction0[`INST_CODE_RNG];
//The next equations calculate the reservations stations ID based on the current operation and the availability
//of the RS's (that is if a given statation is busy choose another suitable 1). To understand this equations
//please refer to the table TBD in the architecture specification document
 
assign wReservationStation[0] =
(wOp[0] & ~wOp[1] & ~wOp[2] & ~wOp[3] & ~iRStationBusy[ 0 ]) |
605,6 → 616,8
assign wDestIndexDisplaced = (iInstruction0[`INST_DST_RNG] + iFrameOffset);
assign wDestinationIndex_NoIMM = (iInstruction0[`INST_DEST_ZERO]) ? wDestIndexDisplaced : iInstruction0[`INST_DST_RNG];
 
wire [`WIDTH-1:0 ] wSource1_X;
assign wSource1_X = wSource1_Temp[`X_RNG];
 
MUXFULLPARALELL_3SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) DSTMUX
(
612,7 → 625,7
.I1(iInstruction0[`INST_DST_RNG]),
.I2(wDestIndexDisplaced),
.I3(wDestIndexDisplaced),
.I4(wDestIndexDisplaced + wSource1_Temp[`X_RNG]),
.I4(wDestIndexDisplaced + wSource1_X[`DATA_ADDRESS_WIDTH-1:0]),
.I5(iInstruction0[`INST_DST_RNG]),
.I6(wDestIndexDisplaced),
.I7(iInstruction0[`INST_DST_RNG]),
/Module_Sqrt_Station.v
73,10 → 73,10
(
.Clock( Clock ),
.Reset( Reset ),
.Operand( wRS1_OperandA[`X_RNG] ),
.iOperand( {32'b0,wRS1_OperandA[`X_RNG]} ),
.iInputReady( wRS1_2_ADD_Trigger ),
.OutputReady(wExeDone ),
.Result( wResult )
.oOutputReady(wExeDone ),
.oResult( wResult )
);
 
 
/Unit_Execution.v
1,24 → 1,24
 
`include "aDefinitions.v"
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2012 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
module Unit_Execution
29,10 → 29,15
input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
input wire iInstructionMem_WriteEnable,
input wire [`INSTRUCTION_WIDTH-1:0] iInstructionMem_WriteData,
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
output wire oOMEMWriteEnable
 
//OMEM
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
output wire oOMEMWriteEnable,
//TMEM
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
input wire iTMEMDataAvailable,
output wire oTMEMDataRequest
);
 
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP0;
44,7 → 49,8
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data0;
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data1;
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wRS_2_II_Busy;
wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus,wModIssue;
wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus;
wire [`MOD_ISSUE_PACKET_SIZE-1:0] wModIssue;
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitRequest;
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitGrant;
wire [`COMMIT_PACKET_SIZE-1:0] wCommitBus;
62,36 → 68,36
wire [`WIDTH-1:0] wThreadControl;
 
// The Register File
RegisterFile # ( `DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH ) RF
(
RegisterFile # ( `DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH ) RF
(
.Clock( Clock ),
.Reset( Reset ),
.iWriteEnable( wCommitBus[`COMMIT_WE_RNG] ),
.iReadAddress0( wII_2_RF_Addr0 ),
.iReadAddress1( wII_2_RF_Addr1 ),
.Reset( Reset ),
.iWriteEnable( wCommitBus[`COMMIT_WE_RNG] ),
.iReadAddress0( wII_2_RF_Addr0 ),
.iReadAddress1( wII_2_RF_Addr1 ),
.iWriteAddress( wCommitBus[`COMMIT_DST_RNG] ),
.oFrameOffset( wFrameOffset ),
.oIndexRegister( wIndexRegister ),
.oThreadControlRegister( wThreadControl ),
.iData( wCommitBus[`COMMIT_DATA_RNG] ),
.oData0( wRF_2_II_Data0 ),
.oData1( wRF_2_II_Data1 )
.iData( wCommitBus[`COMMIT_DATA_RNG] ),
.oData0( wRF_2_II_Data0 ),
.oData1( wRF_2_II_Data1 )
);
 
 
 
 
//Code bank 0
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH, `INSTRUCTION_ADDR_WIDTH) IM
(
.Clock( Clock ),
.iWriteEnable( iInstructionMem_WriteEnable ),
.iReadAddress0( wII0_IP0 ),
.iReadAddress1( wII1_IP0 ),
.iWriteAddress( iInstructionMem_WriteAddress ),
.iDataIn( iInstructionMem_WriteData ),
.oDataOut0( wInstrThread0 ),
.oDataOut1( wInstrThread1 )
//Code bank 0
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH, `INSTRUCTION_ADDR_WIDTH) IM
(
.Clock( Clock ),
.iWriteEnable( iInstructionMem_WriteEnable ),
.iReadAddress0( wII0_IP0 ),
.iReadAddress1( wII1_IP0 ),
.iWriteAddress( iInstructionMem_WriteAddress ),
.iDataIn( iInstructionMem_WriteData ),
.oDataOut0( wInstrThread0 ),
.oDataOut1( wInstrThread1 )
);
 
 
100,12 → 106,12
wire [MaxThreads-1:0] wDelay;
 
 
UPCOUNTER_POSEDGE # (MaxThreads) UP111
(
.Clock( Clock), .Reset( Reset),
UPCOUNTER_POSEDGE # (MaxThreads) UP111
(
.Clock( Clock), .Reset( Reset),
.Initial(0),
.Enable(1'b1),
.Q(wDelay)
.Q(wDelay)
);
 
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII0_IP0,wII0_IP1;
124,16 → 130,16
 
wire [`MAX_THREADS-1:0] wCurrentActiveThread,wCurrentActiveThread_Pre,wCurrentActiveThread_Pre2;
 
CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( `MAX_THREADS ) THREAD_SELECT
CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( `MAX_THREADS ) THREAD_SELECT
(
.Clock( Clock ),
.Reset( Reset ),
.Initial(`MAX_THREADS'b1),
.Clock( Clock ),
.Reset( Reset ),
.Initial(`MAX_THREADS'b1),
.Enable( wDelay[0] /*& wDelay[1]*/ & wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
.O( wCurrentActiveThread_Pre )
);
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_THREADS ) FFD12
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_THREADS ) FFD12
( Clock, Reset, 1'b1 , wCurrentActiveThread_Pre , wCurrentActiveThread_Pre2 );
 
assign wCurrentActiveThread = (wThreadControl[`SPR_TCONTROL0_MT_ENABLED]) ? wCurrentActiveThread_Pre2 : `MAX_THREADS'b1;
148,27 → 154,27
 
InstructionIssue II0
(
.Clock( Clock ),
.Reset( Reset ),
.Clock( Clock ),
.Reset( Reset ),
.iEnable( wCurrentActiveThread[0] & iEnable),
.iFrameOffset( wFrameOffset ),
/* New Apr 06*/.iCodeOffset( `INSTRUCTION_ADDR_WIDTH'b0 ),
.iMtEnabled(wThreadControl[`SPR_TCONTROL0_MT_ENABLED]),
.iIndexRegister( wIndexRegister ),
.iIndexRegister( wIndexRegister ),
.iInstruction0( wInstrThread0 ),
// .iInstruction1( wIM_2_II_Instruction1 ),
.iSourceData0( wRF_2_II_Data0 ),
.iSourceData1( wRF_2_II_Data1 ),
.iRStationBusy( wRS_2_II_Busy ),
.iResultBcast( wCommitBus ),
.iResultBcast( wCommitBus ),
.iSignFlag( wSignFlag ),
.iZeroFlag( wZeroFlag ),
.iIgnoreResultBcast( wResultBCastDst[7] & wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
.oSourceAddress0( wII0_RF_Addr0 ),//wII_2_RF_Addr0 ),
.oSourceAddress0( wII0_RF_Addr0 ),//wII_2_RF_Addr0 ),
.oSourceAddress1( wII0_RF_Addr1 ),//wII_2_RF_Addr1 ),
.oIssueBcast( wII0_IBus ),//wIssueBus ),
.oIP0( wII0_IP0 )//wII_2_IM_IP0 ),
//.oIP1( wII0_IP1 )//wII_2_IM_IP1 )
//.oIP1( wII0_IP1 )//wII_2_IM_IP1 )
);
 
193,21 → 199,21
.iFrameOffset( wFrameOffset ),
.iCodeOffset( wThreadControl[`SPR_TCONTROL0_T0_INST_OFFSET_RNG] ),
.iMtEnabled( wThreadControl[`SPR_TCONTROL0_MT_ENABLED] ),
.iIndexRegister( wIndexRegister ),
.iIndexRegister( wIndexRegister ),
.iInstruction0( wInstrThread1 ),
.iSourceData0( wRF_2_II_Data0 ),
.iSourceData1( wRF_2_II_Data1 ),
.iRStationBusy( wRS_2_II_Busy ),
.iResultBcast( wCommitBus ),
.iResultBcast( wCommitBus ),
.iSignFlag( wSignFlag ),
.iZeroFlag( wZeroFlag ),
.iIgnoreResultBcast( ~wResultBCastDst[7] ),
.oSourceAddress0( wII1_RF_Addr0 ),
.oSourceAddress0( wII1_RF_Addr0 ),
.oSourceAddress1( wII1_RF_Addr1 ),
.oIssueBcast( wII1_IBus ),
.oIP0( wII1_IP0 )
//.oIP1( wII1_IP1 )
//.oIP1( wII1_IP1 )
);
 
215,7 → 221,7
 
OperandModifiers SMU
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iIssueBus( wIssueBus ),
.iCommitBus( wCommitBus ),
230,7 → 236,7
 
ADDER_STATION ADD_STA0
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iId( `RS_ADD0 ),
.iIssueBus( wModIssue ),
244,7 → 250,7
 
ADDER_STATION ADD_STA1
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iId( `RS_ADD1 ),
.iIssueBus( wModIssue ),
259,7 → 265,7
 
DIVISION_STATION DIV_STA
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iId( `RS_DIV ),
.iIssueBus( wModIssue ),
274,7 → 280,7
 
MUL_STATION MUL_STA
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iId( `RS_MUL ),
.iIssueBus( wModIssue ),
289,7 → 295,7
 
SQRT_STATION SQRT_STA
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iId( `RS_SQRT ),
.iIssueBus( wModIssue ),
305,7 → 311,7
 
LOGIC_STATION LOGIC_STA
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iId( `RS_LOGIC ),
.iIssueBus( wModIssue ),
319,7 → 325,7
 
IO_STATION IO_STA
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.iId( `RS_IO ),
.iIssueBus( wModIssue ),
328,9 → 334,15
.oCommitResquest( wStationCommitRequest[6] ),
.iCommitGranted( wStationCommitGrant[6] ),
.oBusy( wRS_2_II_Busy[6] ),
.oOMEMWriteAddress( oOMEMWriteAddress ),
.oOMEMWriteData( oOMEMWriteData ),
.oOMEMWriteEnable( oOMEMWriteEnable )
//OMEM
.oOMEMWriteAddress( oOMEMWriteAddress ),
.oOMEMWriteData( oOMEMWriteData ),
.oOMEMWriteEnable( oOMEMWriteEnable ),
//TMEM
.oTMEMReadAddress( oTMEMReadAddress ),
.iTMEMReadData( iTMEMReadData ),
.iTMEMDataAvailable( iTMEMDataAvailable ),
.oTMEMDataRequest( oTMEMDataRequest )
);
 
356,18 → 368,18
 
);
 
 
wire[3:0] wBusSelector;
wire [5:0] wBusSelector_Tmp;
wire[2:0] wBusSelector;
DECODER_ONEHOT_2_BINARY DECODER
(
.iIn( wStationCommitGrant ),
.oOut( wBusSelector )
.oOut( wBusSelector_Tmp )
);
assign wBusSelector = wBusSelector_Tmp[3:0];
 
 
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX
(
.Sel(wBusSelector),
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX //TODO I need one more entry for the IO
(
.Sel(wBusSelector),
.I1(`COMMIT_PACKET_SIZE'b0),
.I2(wCommitData_Adder0),
.I3(wCommitData_Adder1),
374,8 → 386,9
.I4(wCommitData_Div),
.I5(wCommitData_Mul),
.I6(wCommitData_Sqrt),
.I7(wCommitData_Logic),
.O1(wCommitBus)
.I7(wCommitData_Logic),
.I8(wCommitData_IO ),
.O1(wCommitBus)
);
 
/Module_Logic_Station.v
42,32 → 42,33
wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandA;
wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandB;
wire [`DATA_ROW_WIDTH-1:0] wAND,wOR,wResult;
wire [`SCALE_SIZE-1:0] wResultSelector_Temp;
wire [1:0] wResultSelector;
 
ReservationStation_1Cycle RS
(
.Clock( Clock ),
.Reset( Reset ),
.iIssueBus( iIssueBus ),
.iCommitBus( iCommitBus ),
.iMyId( iId ),
.iExecutionDone( wExeDone ),
.iResult( wResult ),
.iCommitGranted( iCommitGranted ),
.Clock( Clock ),
.Reset( Reset ),
.iIssueBus( iIssueBus ),
.iCommitBus( iCommitBus ),
.iMyId( iId ),
.iExecutionDone( wExeDone ),
.iResult( wResult ),
.iCommitGranted( iCommitGranted ),
.oSource1( wRS1_OperandA ),
.oSource0( wRS1_OperandB ),
.oBusy( oBusy ),
.oTrigger( wRS1_2_ADD_Trigger ),
.oCommitRequest( oCommitResquest ),
.oId( oCommitData[`COMMIT_RSID_RNG] ),
.oWE( oCommitData[`COMMIT_WE_RNG] ),
.oDestination( oCommitData[`COMMIT_DST_RNG] ),
.oScale( wResultSelector_Temp ),
.oResult( {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]} )
.oSource1( wRS1_OperandA ),
.oSource0( wRS1_OperandB ),
.oBusy( oBusy ),
.oTrigger( wRS1_2_ADD_Trigger ),
.oCommitRequest( oCommitResquest ),
.oId( oCommitData[`COMMIT_RSID_RNG] ),
.oWE( oCommitData[`COMMIT_WE_RNG] ),
.oDestination( oCommitData[`COMMIT_DST_RNG] ),
.oScale(wResultSelector),
.oResult( {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]})
);
 
assign wResultSelector = wResultSelector_Temp[1:0];
 
MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ROW_WIDTH ) MUX1
(
/Module_FixedPointSquareRoot.v
156,10 → 156,10
(
input wire Clock,
input wire Reset,
input wire[`LONG_WIDTH-1:0] Operand,
input wire[`LONG_WIDTH-1:0] iOperand,
input wire iInputReady,
output wire OutputReady,
output wire [`WIDTH-1:0] Result
output wire oOutputReady,
output wire [`WIDTH-1:0] oResult
);
 
 
169,12 → 169,12
.Reset( Reset ),
.Enable(1'b1 ),
.D( iInputReady ),
.Q( OutputReady )
.Q( oOutputReady )
);
 
//LUT only has values from 0 to 127, lets see if the value is bigger than that
wire wNotInLUT;
assign wNotInLUT = Operand[7+`SCALE];
assign wNotInLUT = iOperand[7+`SCALE];
//If the value is not on the LUT then divide by 64, so SQRT(x) = SQRT(64*x/64)
//=16*SQRT(x/64)
 
181,8 → 181,8
wire[`WIDTH-1:0] wScaledOperand;
 
assign wScaledOperand = (wNotInLUT == 1'b0 ) ?
{Operand[`WIDTH-1:`SCALE],{`SCALE{1'b0}}} : //Aproximate the Square root to an integer value
{6'b0,Operand[`WIDTH-1:`SCALE+6],{`SCALE{1'b0}}}; //Shift right two bits (divide by 4)
{iOperand[`WIDTH-1:`SCALE],{`SCALE{1'b0}}} : //Aproximate the Square root to an integer value
{6'b0,iOperand[`WIDTH-1:`SCALE+6],{`SCALE{1'b0}}}; //Shift right two bits (divide by 4)
 
wire [`WIDTH-1:0] wResult,wScaleResult;
SQUAREROOT_LUT SQRT
203,7 → 203,7
.Reset( Reset ),
.Enable(1'b1 ),
.D( wResult ),
.Q( Result )
.Q( oResult )
);
 
 
/Collaterals.v
47,87 → 47,87
end//always
 
endmodule
//------------------------------------------------
module PULSE
(
//------------------------------------------------
module PULSE
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire D,
output wire Q
);
 
wire wDelay;
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD (Clock,Reset,Enable,D,wDelay);
 
assign Q = (Enable) ? (D ^ wDelay) & D: 1'b0;
 
endmodule
//------------------------------------------------
module ADDER # (parameter SIZE=`WIDTH)
(
input wire Clock,
input wire Reset,
input wire iTrigger,
input wire [SIZE-1:0] iA,iB,
output wire [SIZE-1:0] oR,
output wire oDone
);
wire [SIZE-1:0] wR,wR_Delay;
assign wR = iA + iB;
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
assign oR = wR_Delay;
 
endmodule
//------------------------------------------------
module OR # (parameter SIZE=`WIDTH)
(
input wire Clock,
input wire Reset,
input wire iTrigger,
input wire [SIZE-1:0] iA,iB,
output wire [SIZE-1:0] oR,
output wire oDone
);
wire [SIZE-1:0] wR,wR_Delay;
assign wR = iA | iB;
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
assign oR = wR_Delay;
 
endmodule
//------------------------------------------------
module AND # (parameter SIZE=`WIDTH)
(
input wire Clock,
input wire Reset,
input wire iTrigger,
input wire [SIZE-1:0] iA,iB,
output wire [SIZE-1:0] oR,
output wire oDone
);
wire [SIZE-1:0] wR,wR_Delay;
assign wR = iA & iB;
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
assign oR = wR_Delay;
 
endmodule
output wire Q
);
 
wire wDelay;
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD (Clock,Reset,Enable,D,wDelay);
 
assign Q = (Enable) ? (D ^ wDelay) & D: 1'b0;
 
endmodule
//------------------------------------------------
module ADDER # (parameter SIZE=`WIDTH)
(
input wire Clock,
input wire Reset,
input wire iTrigger,
input wire [SIZE-1:0] iA,iB,
output wire [SIZE-1:0] oR,
output wire oDone
);
wire [SIZE-1:0] wR,wR_Delay;
assign wR = iA + iB;
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
assign oR = wR_Delay;
 
endmodule
//------------------------------------------------
module OR # (parameter SIZE=`WIDTH)
(
input wire Clock,
input wire Reset,
input wire iTrigger,
input wire [SIZE-1:0] iA,iB,
output wire [SIZE-1:0] oR,
output wire oDone
);
wire [SIZE-1:0] wR,wR_Delay;
assign wR = iA | iB;
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
assign oR = wR_Delay;
 
endmodule
//------------------------------------------------
module AND # (parameter SIZE=`WIDTH)
(
input wire Clock,
input wire Reset,
input wire iTrigger,
input wire [SIZE-1:0] iA,iB,
output wire [SIZE-1:0] oR,
output wire oDone
);
wire [SIZE-1:0] wR,wR_Delay;
assign wR = iA & iB;
 
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD0 (Clock,Reset,1'b1,iTrigger,oDone);
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # (SIZE) FFD (Clock,Reset,iTrigger,wR,wR_Delay);
assign oR = wR_Delay;
 
endmodule
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
 
136,40 → 136,43
begin
if (Reset)
Q <= Initial;
else
begin
else
begin
if (Enable)
Q <= Q + 1;
Q <= Q + 1;
end
end
 
endmodule
 
//----------------------------------------------------------------------
module DECODER_ONEHOT_2_BINARY
(
input wire [5:0] iIn,
output reg[5:0] oOut
);
 
always @ (*)
begin
case (iIn)
6'b000000: oOut = 0;
6'b000001: oOut = 1;
6'b000010: oOut = 2;
6'b000100: oOut = 3;
6'b001000: oOut = 4;
6'b010000: oOut = 5;
6'b100000: oOut = 6;
default:
oOut = 0;
endcase
end
endmodule
//----------------------------------------------------------------------
 
 
//----------------------------------------------------------------------
 
module DECODER_ONEHOT_2_BINARY # (parameter OUTPUT_WIDTH = 6)
(
input wire [6:0] iIn,
output reg[OUTPUT_WIDTH-1:0] oOut
);
 
always @ (*)
begin
case (iIn)
7'b0000000: oOut = 0;
7'b0000001: oOut = 1;
7'b0000010: oOut = 2;
7'b0000100: oOut = 3;
7'b0001000: oOut = 4;
7'b0010000: oOut = 5;
7'b0100000: oOut = 6;
7'b1000000: oOut = 7;
default:
oOut = 0;
endcase
end
endmodule
 
//----------------------------------------------------------------------
 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
(
input wire [SEL_WIDTH-1:0] Sel,
176,27 → 179,27
input wire En,
output wire [OUTPUT_WIDTH-1:0] O
);
 
reg[OUTPUT_WIDTH-1:0] shift;
 
always @ ( * )
begin
if (~En)
shift = 1;
else
shift = (1 << Sel);
 
 
end
 
assign O = ( ~En ) ? 0 : shift ;
 
//assign O = En & (1 << Sel);
 
endmodule
 
//----------------------------------------------------------------------
module MUXFULLPARALELL_GENERIC #(parameter WIDTH = `WIDTH, parameter CHANNELS = 4, parameter SELBITS = 2)
reg[OUTPUT_WIDTH-1:0] shift;
 
always @ ( * )
begin
if (~En)
shift = 1;
else
shift = (1 << Sel);
 
 
end
 
assign O = ( ~En ) ? 0 : shift ;
 
//assign O = En & (1 << Sel);
 
endmodule
 
//----------------------------------------------------------------------
module MUXFULLPARALELL_GENERIC #(parameter WIDTH = `WIDTH, parameter CHANNELS = 4, parameter SELBITS = 2)
(
 
input wire [(CHANNELS*WIDTH)-1:0] in_bus,
212,7 → 215,7
assign out = input_array[sel];
 
generate
for(ig=0; ig<CHANNELS; ig=ig+1)
for(ig=0; ig<CHANNELS; ig=ig+1)
begin: array_assignments
assign input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
end
237,7 → 240,7
 
2'b00: O1 = I1;
2'b01: O1 = I2;
2'b10: O1 = I3;
2'b10: O1 = I3;
2'b11: O1 = I4;
default: O1 = SIZE;
 
245,7 → 248,7
 
end
 
endmodule
endmodule
//------------------------------------------------------------------------
module MUXFULLPARALELL_3SEL_GENERIC # ( parameter SIZE=`WIDTH )
(
262,11 → 265,11
 
3'b000: O1 = I1;
3'b001: O1 = I2;
3'b010: O1 = I3;
3'b011: O1 = I4;
3'b100: O1 = I5;
3'b101: O1 = I6;
3'b110: O1 = I7;
3'b010: O1 = I3;
3'b011: O1 = I4;
3'b100: O1 = I5;
3'b101: O1 = I6;
3'b110: O1 = I7;
3'b111: O1 = I8;
default: O1 = SIZE;
 
275,12 → 278,12
end
 
endmodule
//------------------------------------------------------------------------
//------------------------------------------------------------------------
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
( input wire Clock,
input wire Reset,
input wire[SIZE-1:0] Initial,
input wire Enable,
input wire Enable,
output wire[SIZE-1:0] O
);
 
293,16 → 296,16
tmp <= Initial;
else
begin
if (Enable)
begin
if (tmp[SIZE-1])
begin
tmp <= Initial;
end
else
if (Enable)
begin
if (tmp[SIZE-1])
begin
tmp <= tmp << 1;
end
tmp <= Initial;
end
else
begin
tmp <= tmp << 1;
end
end
end
end
333,12 → 336,12
 
end
 
endmodule
endmodule
//------------------------------------------------
module MUXFULLPARALELL_3SEL_EN # ( parameter SIZE=`WIDTH )
(
input wire [1:0] SEL,
input wire [SIZE-1:0]I1, I2, I3,
input wire [SIZE-1:0]I1, I2, I3,
input wire EN,
output reg [SIZE-1:0] O1
);
346,7 → 349,7
always @( * )
 
begin
if (EN)
if (EN)
begin
case (SEL)
 
356,14 → 359,14
default: O1 = SIZE;
 
endcase
end
else
begin
O1 = I1;
end
else
begin
O1 = I1;
end
end
 
endmodule
endmodule
//------------------------------------------------
module MUXFULLPARALELL_4SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
(
380,7 → 383,7
 
4'b0001: O1 = I1;
4'b0010: O1 = I2;
4'b0100: O1 = I3;
4'b0100: O1 = I3;
4'b1000: O1 = I4;
default: O1 = SIZE;
 
579,7 → 582,7
endmodule
//--------------------------------------------------------------
/*
module FIFO_SYNCHRNOUS_RESET # ( parameter SIZE=`WIDTH, parameter DEPTH=16 )
module FIFO_SYNCHRNOUS_RESET # ( parameter SIZE=`WIDTH, parameter DEPTH=16 )
(
input wire Clock,
input wire Reset,
676,10 → 679,10
.oe_1 (rd_en) // output enable
);
 
endmodule
*/
 
 
endmodule
*/
 
 
module sync_fifo #( parameter DATA_WIDTH = 8, parameter DEPTH = 8 )
(
 
694,8 → 697,8
 
);
 
parameter ADDR_WIDTH = $clog2(DEPTH);
parameter ADDR_WIDTH = $clog2(DEPTH);
 
reg [ADDR_WIDTH : 0] rd_ptr; // note MSB is not really address
reg [ADDR_WIDTH : 0] wr_ptr; // note MSB is not really address
764,23 → 767,23
assign dout = mem[rd_loc];//rd_en ? mem[rd_loc]:'h0;
 
endmodule
 
//---------------------------------------------------------------------
 
/*
 
//---------------------------------------------------------------------
 
/*
Synchronous memory blocks have two independent address ports, allowing
for operations on two unique addresses simultaneously. A read operation and a write
operation can share the same port if they share the same address.
operation can share the same port if they share the same address.
In the synchronous RAM block architecture, there is no priority between the two
ports. Therefore, if you write to the same location on both ports at the same time, the
result is indeterminate in the device architecture.
result is indeterminate in the device architecture.
When a read and write operation occurs on the same port for
the same address, the new data being written to the memory is read. When a read and
write operation occurs on different ports for the same address, the old data in the
memory is read. Simultaneous writes to the same location on both ports results in
indeterminate behavior.
 
*/
indeterminate behavior.
 
*/
module RAM_DUAL_READ_DUAL_WRITE_PORT # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
(
input wire [(DATA_WIDTH-1):0] data_a, data_b,
801,7 → 804,7
end
else
q_a <= ram[addr_a];
end
end
always @ (posedge clk)
begin // Port b
813,13 → 816,13
else
q_b <= ram[addr_b];
end
endmodule
 
 
endmodule
 
 
module RAM_QUAD_PORT # ( parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6 )
(
input wire [(DATA_WIDTH-1):0] data_a, data_b,
input wire [(ADDR_WIDTH-1):0] waddr_a, waddr_b,
input wire [(ADDR_WIDTH-1):0] waddr_a, waddr_b,
input wire [(ADDR_WIDTH-1):0] raddr_a, raddr_b,
input wire we_a, we_b, clk,
output reg [(DATA_WIDTH-1):0] q_a, q_b
830,29 → 833,29
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clk)
begin // Port A
if (we_a)
if (we_a)
begin
ram[waddr_a] <= data_a;
ram[waddr_a] <= data_a;
q_a <= data_a;
end
end
else
q_a <= ram[waddr_a];
end
end
always @ (posedge clk)
begin // Port B
if (we_b)
if (we_b)
begin
ram[waddr_b] <= data_b;
ram[waddr_b] <= data_b;
q_b <= data_b;
end
end
else
q_b <= ram[waddr_b];
end
end
endmodule
//-------------------------------------------------------------------------------
endmodule
//-------------------------------------------------------------------------------
//----------------------------------------------------
// A four level, round-robin arbiter. This was
// orginally coded by WD Peterson in VHDL.
859,12 → 862,12
//----------------------------------------------------
module ROUND_ROBIN_ARBITER (
clk,
rst,
rst,
req4,
req3,
req2,
req1,
req0,
req0,
gnt4,
gnt3,
gnt2,
873,12 → 876,12
);
// --------------Port Declaration-----------------------
input clk;
input rst;
input rst;
input req4;
input req3;
input req2;
input req1;
input req0;
input req0;
output gnt4;
output gnt3;
output gnt2;
894,11 → 897,11
reg lgnt0 ;
reg lgnt1 ;
reg lgnt2 ;
reg lgnt3 ;
reg lgnt3 ;
reg lgnt4 ;
reg lasmask ;
reg lmask0 ;
reg lmask1 ;
reg lmask1 ;
reg lmask2 ;
reg ledge ;
908,36 → 911,36
lgnt0 <= 0;
lgnt1 <= 0;
lgnt2 <= 0;
lgnt3 <= 0;
lgnt3 <= 0;
lgnt4 <= 0;
end else begin
lgnt0 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & ~req3 & ~req2 & ~req1 & req0)
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & ~req3 & ~req2 & req0)
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req0)
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req0 )
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req0 )
| (~lcomreq & lmask2 & ~lmask1 & ~lmask0 & req0 )
| ( lcomreq & lgnt0 );
lgnt1 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req1)
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & ~req3 & ~req2 & req1 & ~req0)
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req1 & ~req0)
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req1 & ~req0)
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req1 & ~req0)
| (~lcomreq & lmask2 & ~lmask1 & ~lmask0 & req1 & ~req0)
| ( lcomreq & lgnt1);
lgnt2 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req2 & ~req1)
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & req2)
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & ~req3 & req2 & ~req1 & ~req0)
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req2 & ~req1 & ~req0)
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & ~req4 & req2 & ~req1 & ~req0)
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & req2 & ~req1 & ~req0)
| ( lcomreq & lgnt2);
lgnt3 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3 & ~req2 & ~req1)
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & ~req4 & req3 & ~req2)
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & req3)
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & ~req4 & req3)
| (~lcomreq & ~lmask2 & ~lmask2 & lmask1 & lmask0 & req3)
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & ~req4 & req3 & ~req2 & ~req1 & ~req0)
| ( lcomreq & lgnt3);
| ( lcomreq & lgnt3);
lgnt4 <=(~lcomreq & ~lmask2 & ~lmask1 & ~lmask0 & req4 & ~req3 & ~req2 & ~req1 & ~req0)
| (~lcomreq & ~lmask2 & ~lmask1 & lmask0 & req4 & ~req3 & ~req2 & ~req1 )
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & req4 & ~req3 & ~req2 )
| (~lcomreq & ~lmask2 & lmask1 & ~lmask0 & req4 & ~req3 & ~req2 )
| (~lcomreq & ~lmask2 & lmask1 & lmask0 & req4 & ~req3 )
| ( lcomreq & lmask2 & ~lmask1 & ~lmask0 & req4 )
| ( lcomreq & lgnt3);
957,8 → 960,8
//----------------------------------------------------
// comreq logic.
//----------------------------------------------------
assign lcomreq =
( req4 & lgnt4 )
assign lcomreq =
( req4 & lgnt4 )
| ( req3 & lgnt3 )
| ( req2 & lgnt2 )
| ( req1 & lgnt1 )
973,15 → 976,15
// lmask register.
//----------------------------------------------------
always @ (posedge clk )
if( rst ) begin
if( rst ) begin
lmask2 <= 0;
lmask1 <= 0;
lmask0 <= 0;
end else if(lasmask) begin
lmask0 <= 0;
end else if(lasmask) begin
lmask2 <= lgnt[2];
lmask1 <= lgnt[1];
lmask0 <= lgnt[0];
end else begin
end else begin
lmask2 <= lmask2;
lmask1 <= lmask1;
lmask0 <= lmask0;
991,7 → 994,7
assign gnt = lgnt;
//----------------------------------------------------
// Drive the outputs
//----------------------------------------------------
//----------------------------------------------------
assign gnt4 = lgnt4;
assign gnt3 = lgnt3;
assign gnt2 = lgnt2;
998,86 → 1001,90
assign gnt1 = lgnt1;
assign gnt0 = lgnt0;
endmodule
//-------------------------------------------------------------------------------
module ROUND_ROBIN_5_ENTRIES
(
input wire Clock,
input wire Reset,
input wire iRequest0,
input wire iRequest1,
input wire iRequest2,
input wire iRequest3,
input wire iRequest4,
output wire oGrant0,
output wire oGrant1,
output wire oGrant2,
output wire oGrant3,
output wire oGrant4,
output wire oPriorityGrant
 
);
wire wMaks2,wMaks1,wMaks0;
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4;
 
assign wGrant0 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
assign wGrant1 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
 
assign wGrant2 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
assign wGrant3 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant4 =
( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
 
assign oPriorityGrant = wGrant0;
 
endmodule
//-------------------------------------------------------------------------------
module ROUND_ROBIN_5_ENTRIES
(
input wire Clock,
input wire Reset,
input wire iRequest0,
input wire iRequest1,
input wire iRequest2,
input wire iRequest3,
input wire iRequest4,
output wire oGrant0,
output wire oGrant1,
output wire oGrant2,
output wire oGrant3,
output wire oGrant4,
output wire oPriorityGrant
 
);
wire wMaks2,wMaks1,wMaks0;
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4;
 
assign wGrant0 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
assign wGrant1 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0) ;
 
assign wGrant2 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
assign wGrant3 =
(wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant4 =
( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
 
assign oPriorityGrant = wGrant0;
wire wGrant1_Pre, wGrant2_Pre, wGrant3_Pre, wGrant4_Pre;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
 
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
 
( Clock, Reset, 1'b1 , wGrant1, wGrant1_Pre ); //If priority grant comes this cycle then we are having troubles...
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
 
( Clock, Reset, 1'b1 , wGrant2, wGrant2_Pre );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
 
( Clock, Reset, 1'b1 , wGrant3, wGrant3_Pre );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
 
 
 
 
reg [4:0] rCurrentState, rNextState;
( Clock, Reset, 1'b1 , wGrant4, wGrant4_Pre );
 
 
assign oGrant1 = wGrant1_Pre & ~oPriorityGrant;
assign oGrant2 = wGrant2_Pre & ~oPriorityGrant;
assign oGrant3 = wGrant3_Pre & ~oPriorityGrant;
assign oGrant4 = wGrant4_Pre & ~oPriorityGrant;
 
reg [4:0] rCurrentState, rNextState;
//Next states logic and Reset sequence
always @(posedge Clock )
begin
1087,152 → 1094,152
else
rCurrentState <= rNextState;
end
reg[2:0] rMask;
 
assign wMaks0 = rMask[0];
assign wMaks1 = rMask[1];
assign wMaks2 = rMask[2];
 
always @ ( * )
begin
case (rCurrentState)
//--------------------------------------
0:
begin
rMask = 3'd0;
rNextState = 1;
end
1:
begin
end
reg[2:0] rMask;
 
assign wMaks0 = rMask[0];
assign wMaks1 = rMask[1];
assign wMaks2 = rMask[2];
 
always @ ( * )
begin
case (rCurrentState)
//--------------------------------------
0: //Mask for grant 0
begin
rMask = 3'd0;
rNextState = 1;
end
1: //Mask for grant 1
begin
rMask = 3'd1;
rNextState = 2;
end
2:
begin
rMask = 3'd2;
rNextState = 3;
end
3:
begin
rMask = 3'd3;
rNextState = 4;
end
4:
begin
rMask = 3'd4;
rNextState = 0;
end
endcase
end
/*
rNextState = 2;
end
2:
begin
rMask = 3'd2;
rNextState = 3;
end
3:
begin
rMask = 3'd3;
rNextState = 4;
end
4:
begin
rMask = 3'd4;
rNextState = 0;
end
endcase
end
/*
UPCOUNTER_POSEDGE # (3) UP1
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.Initial( 3'b0 ),
.Enable( 1'b1 ),
.Initial( 3'b0 ),
.Enable( 1'b1 ),
.Q({wMaks2,wMaks1,wMaks0})
);
*/
endmodule
//-------------------------------------------------------------------------------
module ROUND_ROBIN_6_ENTRIES
(
input wire Clock,
input wire Reset,
input wire iRequest0,
input wire iRequest1,
input wire iRequest2,
input wire iRequest3,
input wire iRequest4,
input wire iRequest5,
output wire oGrant0,
output wire oGrant1,
output wire oGrant2,
output wire oGrant3,
output wire oGrant4,
output wire oGrant5,
output wire oPriorityGrant
 
);
wire wMaks2,wMaks1,wMaks0;
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5;
 
assign wGrant0 =
(wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
assign wGrant1 =
(wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
 
assign wGrant2 =
(wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
assign wGrant3 =
( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant4 =
( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant5 =
( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
 
assign oPriorityGrant = wGrant0;
 
);
*/
endmodule
//-------------------------------------------------------------------------------
module ROUND_ROBIN_6_ENTRIES
(
input wire Clock,
input wire Reset,
input wire iRequest0,
input wire iRequest1,
input wire iRequest2,
input wire iRequest3,
input wire iRequest4,
input wire iRequest5,
output wire oGrant0,
output wire oGrant1,
output wire oGrant2,
output wire oGrant3,
output wire oGrant4,
output wire oGrant5,
output wire oPriorityGrant
 
);
wire wMaks2,wMaks1,wMaks0;
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5;
 
assign wGrant0 =
(wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
assign wGrant1 =
(wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
 
assign wGrant2 =
(wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
assign wGrant3 =
( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant4 =
( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant5 =
( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
 
assign oPriorityGrant = wGrant0;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
 
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
 
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
 
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
 
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
 
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
 
 
reg [4:0] rCurrentState, rNextState;
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
 
 
reg [4:0] rCurrentState, rNextState;
//Next states logic and Reset sequence
always @(posedge Clock )
begin
1242,179 → 1249,179
else
rCurrentState <= rNextState;
end
reg[2:0] rMask;
 
assign wMaks0 = rMask[0];
assign wMaks1 = rMask[1];
assign wMaks2 = rMask[2];
 
always @ ( * )
begin
case (rCurrentState)
//--------------------------------------
0:
begin
rMask = 3'd0;
rNextState = 1;
end
1:
begin
rMask = 3'd1;
rNextState = 2;
end
2:
begin
rMask = 3'd2;
rNextState = 3;
end
3:
begin
rMask = 3'd3;
rNextState = 4;
end
4:
begin
rMask = 3'd4;
rNextState = 5;
end
5:
begin
rMask = 3'd5;
rNextState = 0;
end
endcase
end
/*
end
reg[2:0] rMask;
 
assign wMaks0 = rMask[0];
assign wMaks1 = rMask[1];
assign wMaks2 = rMask[2];
 
always @ ( * )
begin
case (rCurrentState)
//--------------------------------------
0:
begin
rMask = 3'd0;
rNextState = 1;
end
1:
begin
rMask = 3'd1;
rNextState = 2;
end
2:
begin
rMask = 3'd2;
rNextState = 3;
end
3:
begin
rMask = 3'd3;
rNextState = 4;
end
4:
begin
rMask = 3'd4;
rNextState = 5;
end
5:
begin
rMask = 3'd5;
rNextState = 0;
end
endcase
end
/*
UPCOUNTER_POSEDGE # (3) UP1
(
.Clock( Clock ),
.Clock( Clock ),
.Reset( Reset ),
.Initial( 3'b0 ),
.Enable( 1'b1 ),
.Initial( 3'b0 ),
.Enable( 1'b1 ),
.Q({wMaks2,wMaks1,wMaks0})
);
*/
endmodule
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
module ROUND_ROBIN_7_ENTRIES
(
input wire Clock,
input wire Reset,
input wire iRequest0,
input wire iRequest1,
input wire iRequest2,
input wire iRequest3,
input wire iRequest4,
input wire iRequest5,
input wire iRequest6,
output wire oGrant0,
output wire oGrant1,
output wire oGrant2,
output wire oGrant3,
output wire oGrant4,
output wire oGrant5,
output wire oGrant6,
output wire oPriorityGrant
 
);
wire wMaks2,wMaks1,wMaks0;
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5,wGrant6;
 
assign wGrant0 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
assign wGrant1 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6)
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
 
assign wGrant2 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
assign wGrant3 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant4 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6)
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant5 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6);
 
assign wGrant6 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
 
assign oPriorityGrant = wGrant0;
 
);
*/
endmodule
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
module ROUND_ROBIN_7_ENTRIES
(
input wire Clock,
input wire Reset,
input wire iRequest0,
input wire iRequest1,
input wire iRequest2,
input wire iRequest3,
input wire iRequest4,
input wire iRequest5,
input wire iRequest6,
output wire oGrant0,
output wire oGrant1,
output wire oGrant2,
output wire oGrant3,
output wire oGrant4,
output wire oGrant5,
output wire oGrant6,
output wire oPriorityGrant
 
);
wire wMaks2,wMaks1,wMaks0;
wire wGrant0,wGrant1,wGrant2,wGrant3,wGrant4,wGrant5,wGrant6;
 
assign wGrant0 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1)
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest0 );
assign wGrant1 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6)
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2)
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest1 & ~iRequest0);
 
assign wGrant2 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3)
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest2 & ~iRequest1 & ~iRequest0 );
assign wGrant3 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5 & ~iRequest4)
|(~wMaks2 & wMaks1 & wMaks0 & iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant4 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6)
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6 & ~iRequest5)
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
assign wGrant5 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 & ~iRequest6);
 
assign wGrant6 =
( wMaks2 & wMaks1 & ~wMaks0 & iRequest6 )
|( wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 )
|( wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 )
|(~wMaks2 & wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 )
|(~wMaks2 & wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 )
|(~wMaks2 & ~wMaks1 & wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 )
|(~wMaks2 & ~wMaks1 & ~wMaks0 & iRequest6 & ~iRequest5 & ~iRequest4 & ~iRequest3 & ~iRequest2 & ~iRequest1 & ~iRequest0 );
 
 
assign oPriorityGrant = wGrant0;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD0
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
 
( Clock, Reset, 1'b1 , wGrant0, oGrant0);
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
 
( Clock, Reset, 1'b1 , wGrant1, oGrant1 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
 
( Clock, Reset, 1'b1 , wGrant2, oGrant2 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
 
( Clock, Reset, 1'b1 , wGrant3, oGrant3 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
 
( Clock, Reset, 1'b1 , wGrant4, oGrant4 );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
 
 
( Clock, Reset, 1'b1 , wGrant5, oGrant5 );
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD6
( Clock, Reset, 1'b1 , wGrant6, oGrant6 );
 
 
reg [4:0] rCurrentState, rNextState;
( Clock, Reset, 1'b1 , wGrant6, oGrant6 );
 
 
reg [4:0] rCurrentState, rNextState;
//Next states logic and Reset sequence
always @(posedge Clock )
begin
1424,55 → 1431,55
else
rCurrentState <= rNextState;
end
reg[2:0] rMask;
 
assign wMaks0 = rMask[0];
assign wMaks1 = rMask[1];
assign wMaks2 = rMask[2];
 
always @ ( * )
begin
case (rCurrentState)
//--------------------------------------
0:
begin
rMask = 3'd0;
rNextState = 1;
end
1:
begin
rMask = 3'd1;
rNextState = 2;
end
2:
begin
rMask = 3'd2;
rNextState = 3;
end
3:
begin
rMask = 3'd3;
rNextState = 4;
end
4:
begin
rMask = 3'd4;
rNextState = 5;
end
5:
begin
rMask = 3'd5;
rNextState = 6;
end
6:
begin
rMask = 3'd6;
rNextState = 0;
end
endcase
end
 
end
reg[2:0] rMask;
 
assign wMaks0 = rMask[0];
assign wMaks1 = rMask[1];
assign wMaks2 = rMask[2];
 
always @ ( * )
begin
case (rCurrentState)
//--------------------------------------
0:
begin
rMask = 3'd0;
rNextState = 1;
end
1:
begin
rMask = 3'd1;
rNextState = 2;
end
2:
begin
rMask = 3'd2;
rNextState = 3;
end
3:
begin
rMask = 3'd3;
rNextState = 4;
end
4:
begin
rMask = 3'd4;
rNextState = 5;
end
5:
begin
rMask = 3'd5;
rNextState = 6;
end
6:
begin
rMask = 3'd6;
rNextState = 0;
end
endcase
end
 
endmodule
`endif
/Unit_IO.v
53,8 → 53,23
input wire iOMEM_WriteEnable,
output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
output wire OMEM_WE_O
output wire OMEM_WE_O,
 
//TMem
 
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadData,
input wire iTMEMDataRequest,
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadAddress,
output wire oTMEMDataAvailable,
 
input wire TMEM_ACK_I,
input wire [`WB_WIDTH-1:0] TMEM_DAT_I ,
output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
output wire TMEM_WE_O,
output wire TMEM_STB_O,
output wire TMEM_CYC_O,
input wire TMEM_GNT_I
 
);
 
 
96,5 → 111,25
);
 
 
 
Module_TMemInterface TMI
(
.Clock( CLK_I ),
.Reset( RST_I ),
.iEnable( iTMEMDataRequest ),
.iAddress( iTMEMReadAddress ),
.oData( oTMEMReadData ),
.oDone( oTMEMDataAvailable ),
 
.ACK_I( TMEM_ACK_I ),
.GNT_I( TMEM_GNT_I ),
.DAT_I( TMEM_DAT_I ),
.ADR_O( TMEM_ADR_O ),
.WE_O( TMEM_WE_O ),
.STB_O( TMEM_STB_O ),
.CYC_O( TMEM_CYC_O )
 
);
 
endmodule
/Module_VectorProcessor.v
38,7 → 38,14
output wire MCU_ACK_O,
output wire OMEM_WE,
output wire [`WB_WIDTH-1:0] OMEM_ADDR,
output wire [`WB_WIDTH-1:0] OMEM_DATA
output wire [`WB_WIDTH-1:0] OMEM_DATA,
input wire TMEM_ACK_I,
input wire [`WB_WIDTH-1:0] TMEM_DAT_I ,
output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
output wire TMEM_WE_O,
output wire TMEM_STB_O,
output wire TMEM_CYC_O,
input wire TMEM_GNT_I
 
51,6 → 58,11
wire [`DATA_ROW_WIDTH-1:0] wEXE_2_IO__OMEM_WriteData;
wire wEXE_2_IO__OMEM_WriteEnable;
 
 
wire [`DATA_ROW_WIDTH-1:0] wEXE_2__IO_TMEMAddress;
wire [`DATA_ROW_WIDTH-1:0] wIO_2_EXE__TMEMData;
wire wIO_2_EXE__DataAvailable;
wire wEXE_2_IO__DataRequest;
 
ControlUnit CONTROL
(
89,10 → 101,22
.iOMEM_WriteEnable( wEXE_2_IO__OMEM_WriteEnable ),
.OMEM_DAT_O( OMEM_DATA ),
.OMEM_ADR_O( OMEM_ADDR ),
.OMEM_WE_O( OMEM_WE )
.OMEM_WE_O( OMEM_WE ),
 
 
.oTMEMReadData( wIO_2_EXE__TMEMData ),
.iTMEMDataRequest( wEXE_2_IO__DataRequest ),
.iTMEMReadAddress( wEXE_2__IO_TMEMAddress ),
.oTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
 
.TMEM_ACK_I( TMEM_ACK_I ),
.TMEM_DAT_I( TMEM_DAT_I ),
.TMEM_ADR_O( TMEM_ADR_O ),
.TMEM_WE_O( TMEM_WE_O ),
.TMEM_STB_O( TMEM_STB_O ),
.TMEM_CYC_O( TMEM_CYC_O ),
.TMEM_GNT_I( TMEM_GNT_I )
 
);
 
Unit_Execution EXE
105,8 → 129,14
.iInstructionMem_WriteData( wIO_2_MEM__Instruction ),
.oOMEMWriteAddress( wEXE_2_IO__OMEM_WriteAddress ),
.oOMEMWriteData( wEXE_2_IO__OMEM_WriteData ),
.oOMEMWriteEnable( wEXE_2_IO__OMEM_WriteEnable )
.oOMEMWriteEnable( wEXE_2_IO__OMEM_WriteEnable ),
 
 
.oTMEMReadAddress( wEXE_2__IO_TMEMAddress ),
.iTMEMReadData( wIO_2_EXE__TMEMData ),
.iTMEMDataAvailable( wIO_2_EXE__DataAvailable ),
.oTMEMDataRequest( wEXE_2_IO__DataRequest )
 
);
endmodule
/Module_ReservationStation.v
1,5 → 1,4
`include "aDefinitions.v"
 
module ReservationStation
(
input wire Clock,
12,6 → 11,7
input wire [`DATA_ROW_WIDTH-1:0] iResult,
output wire [`DATA_ROW_WIDTH-1:0] oSource1,
output wire [`DATA_ROW_WIDTH-1:0] oSource0,
output wire [2:0] oScale,
output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
output wire [`DATA_ROW_WIDTH-1:0] oResult,
output wire [2:0] oWE,
18,7 → 18,7
output wire [3:0] oId,
output wire oBusy,
output wire oTrigger,
output wire oCommitRequest,
output wire oCommitRequest,
output wire [`DATA_ROW_WIDTH-1:0] oSrc0Latched,oSrc1Latched
);
38,7 → 38,7
wire wCommitFifoFull;
wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
 
 
assign oScale = wScale;
//assign wFIFO_Pop = iExecutionDone;
assign oCommitRequest = iExecutionDone;
assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
84,9 → 84,9
 
wire [3:0] wScale;
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
assign oSrc0Latched = wSrc0;
( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
assign oSrc0Latched = wSrc0;
assign oSrc1Latched = wSrc1;
 
assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
109,6 → 109,154
( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
 
*/
endmodule
 
module ReservationStation_EX
(
input wire Clock,
input wire Reset,
input wire [`MOD_ISSUE_PACKET_SIZE-1:0] iIssueBus,
input wire [`MOD_COMMIT_PACKET_SIZE-1:0] iCommitBus,
input wire [3:0] iMyId,
input wire iExecutionDone,
input wire iCommitGranted,
input wire [`DATA_ROW_WIDTH-1:0] iResult,
output wire [`DATA_ROW_WIDTH-1:0] oSource1,
output wire [`DATA_ROW_WIDTH-1:0] oSource0,
output wire [2:0] oScale,
output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination,
output wire [`DATA_ROW_WIDTH-1:0] oResult,
output wire [2:0] oWE,
output wire [3:0] oId,
output wire oBusy,
output wire oTrigger,
output wire oCommitRequest,
output wire [`DATA_ROW_WIDTH-1:0] oSrc0Latched,oSrc1Latched
);
 
wire wStall;
wire wLatchRequest;
wire [3:0] wSource1_RS;
wire [3:0] wSource0_RS;
//wire [3:0] wMyId;
wire wTrigger;
//wire wFIFO_Pop;
 
wire [`MOD_ISSUE_PACKET_SIZE-1:0] wIssue_Latched;
wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
wire [3:0] wID;
wire [2:0] wWE;
wire wCommitFifoFull;
wire [`ISSUE_SRCTAG_SIZE-1:0] wTag0,wTag1;
 
assign oScale = wScale;
//assign wFIFO_Pop = iExecutionDone;
assign oCommitRequest = iExecutionDone;
assign wLatchRequest = ( iIssueBus[`MOD_ISSUE_RSID_RNG] == iMyId) ? 1'b1 : 1'b0;
//If there are no dependencies then just trigger execution
//assign oTrigger = (wTrigger /*&& (iIssueBus[`ISSUE_SRC0RS_RNG] == 0) && (iIssueBus[`ISSUE_SRC1RS_RNG] == 0)*/ ) ? 1'b1 : 0;
 
wire wTrigger_Pre,wTrigger_Delay,DependencyResolved_Delay;
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDXXX
( Clock, Reset, 1'b1 , wTrigger_Pre, wTrigger_Delay );
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) ISSUE_FFDYYY
( Clock, Reset, 1'b1 , DependencyResolved, DependencyResolved_Delay );
 
assign wTrigger_Pre = ((wLatchRequest & ~wStall) | DependencyResolved);//( (wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus) & ~wStall);
 
//////////////HERE!!!!!!!!!!!!!!!!!!!!!
//assign oTrigger = wTrigger_Pre;//(DependencyResolved) ? wTrigger_Pre : wTrigger_Delay;
assign oTrigger = (DependencyResolved) ? wTrigger_Pre : (wTrigger_Delay & ~DependencyResolved_Delay);
//////////////HERE!!!!!!!!!!!!!!!!!!!!!
 
 
 
//assign wStall = (/*wLatchRequest*/(wBusy||wLatchRequest) && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ? 1'b1 : 1'b0;
 
///assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) ||
//((wBusy ) && (wSource1_RS != 0 || wSource0_RS != 0) ) ) ? 1'b1 : 1'b0;
wire DependencyDetected,DependencyResolved, wStall_Pre;
assign DependencyDetected = (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0));
assign DependencyResolved = ( wLatchData0FromCommitBus || wLatchData1FromCommitBus );
 
UPCOUNTER_POSEDGE # ( 1 ) STALL
(
.Clock( Clock ),
.Reset( Reset ),
.Enable( DependencyDetected | DependencyResolved ),
.Initial( 1'b0 ),
.Q( wStall_Pre )
);
 
assign wStall = ( (wLatchRequest && (iIssueBus[`MOD_ISSUE_SRC1RS_RNG] != 0 || iIssueBus[`MOD_ISSUE_SRC0RS_RNG] != 0)) || wStall_Pre);
 
 
//assign wStall = (wSource1_RS == 0 & wSource0_RS == 0) ? 1'b0 : 1'b1;
 
wire wLatchData0FromCommitBus;
wire wLatchData1FromCommitBus;
 
 
assign wLatchData0FromCommitBus = ((wSource0_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource0_RS)) ? 1'b1 : 1'b0;
assign wLatchData1FromCommitBus = ((wSource1_RS != 0) && (wStall == 1'b1) && (iCommitBus[`MOD_COMMIT_RSID_RNG] == wSource1_RS)) ? 1'b1 : 1'b0;
 
wire wBusy;
assign oBusy = wBusy | wCommitFifoFull & ~iCommitGranted;
wire wCommitGrantedDelay;
 
UPCOUNTER_POSEDGE # ( 1 ) BUSY
(
.Clock( Clock ),
.Reset( Reset ),
.Enable( wLatchRequest | iCommitGranted ),
.Initial( 1'b0 ),
.Q( wBusy )
);
 
 
 
 
 
assign oSource0 = (wLatchData0FromCommitBus) ? iCommitBus[`MOD_COMMIT_DATA_RNG] : iIssueBus[`MOD_ISSUE_SRC0_DATA_RNG];
assign oSource1 = (wLatchData1FromCommitBus) ? (iCommitBus[`MOD_COMMIT_DATA_RNG]) : iIssueBus[`MOD_ISSUE_SRC1_DATA_RNG];
assign wTrigger = ( wLatchRequest | wLatchData0FromCommitBus | wLatchData1FromCommitBus);
 
 
wire [`DATA_ROW_WIDTH-1:0] wSrc1,wSrc0;
//FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
//( Clock, Reset, wLatchRequest , iIssueBus, {wDstZero,wID,wWE,wDestination,wSource1_RS,wSource0_RS,wSrc1,wSrc0} );
 
wire [3:0] wScale;
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MOD_ISSUE_PACKET_SIZE ) ISSUE_FFD
( Clock, Reset, wLatchRequest , iIssueBus, {wID,wDestination,wWE,wScale,wSource1_RS,wSrc1,wSource0_RS,wSrc0} );
 
 
assign oSrc0Latched = (wLatchData0FromCommitBus)? oSource0 : wSrc0;
assign oSrc1Latched = (wLatchData1FromCommitBus)? oSource1 : wSrc1;
 
assign wTag0 = wSrc0[`MOD_ISSUE_TAG0_RNG];
assign wTag1 = wSrc1[`MOD_ISSUE_TAG0_RNG];
sync_fifo # (`COMMIT_PACKET_SIZE ) COMMIT_OUT_FIFO
(
.clk( Clock ),
.reset( Reset ),
.din( {wID,wWE,wDestination,iResult} ),
.wr_en( iExecutionDone ),
.rd_en( iCommitGranted ),
.dout( {oId,oWE,oDestination,oResult} ),
.full( wCommitFifoFull )
);
 
/*
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_Trigger
( Clock, Reset, 1'b1 , wLatchRequest, wTrigger );
 
*/
endmodule
 
//-------------------------------------------------------------------------------------------------

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