URL
https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
Subversion Repositories theia_gpu
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- This comparison shows the changes necessary to convert path
/theia_gpu/branches/gpu_16_cores/rtl/GPU/TOP
- from Rev 135 to Rev 137
- ↔ Reverse comparison
Rev 135 → Rev 137
/Theia.v
1,5 → 1,24
`timescale 1ns / 1ps |
`include "aDefinitions.v" |
/********************************************************************************** |
Theia, Ray Cast Programable graphic Processing Unit. |
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com) |
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This program is free software; you can redistribute it and/or |
modify it under the terms of the GNU General Public License |
as published by the Free Software Foundation; either version 2 |
of the License, or (at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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***********************************************************************************/ |
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//--------------------------------------------------------------------------- |
module THEIA |
12,21 → 31,13
//when this gets asserted (see documentation) |
//Wish Bone Interface |
input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone) |
//output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone) |
input wire ACK_I, //Input ack |
output wire ACK_O, //Output ack |
//output wire [`WB_WIDTH-1:0] ADR_O, //Output address |
input wire [`WB_WIDTH-1:0] ADR_I, //Input address |
//output wire WE_O, //Output write enable |
input wire WE_I, //Input write enable |
//output wire STB_O, //Strobe signal, see wishbone documentation |
input wire STB_I, //Strobe signal, see wishbone documentation |
//output wire CYC_O, //Bus cycle signal, see wishbone documentation |
input wire CYC_I, //Bus cycle signal, see wishbone documentation |
//output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation |
input wire [1:0] TGA_I, //Input address tag, see THEAI documentation |
//output wire [1:0] TGA_O, //Output address tag, see THEAI documentation |
//input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation |
input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed) |
input wire [`MAX_CORES-1:0] RENDREN_I, |
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85,11 → 96,10
wire [1:0] wTGA_I[`MAX_CORES-1:0]; |
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//wire [`MAX_CORES-1:0] wTMEM_ACK_I; |
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wire [`WB_WIDTH-1:0] wTMEM_Data; |
wire [`WB_WIDTH-1:0] wTMEM_Address[`MAX_CORES-1:0]; |
wire [`WB_WIDTH-1:0] wTMEM_ReadAddr; |
//wire [`MAX_CORES-1:0] wTMEM_STB_O; |
wire [`MAX_CORES-1:0] wTMEM_Resquest; |
wire [`MAX_CORES-1:0] wTMEM_Granted; |
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113,8 → 123,7
wire wTMEM_2_Core__Grant[`MAX_CORES-1:0]; |
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0]; |
//wire [`WB_WIDTH-1:0] wTMEM_2_Core_Data[`MAX_CORES-1:0]; //Vertical grid Buses going to each core. |
wire[7:0] wCoreBankSelect[`MAX_CORES-1:0]; |
wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0]; |
wire [`MAX_CORES-1:0] wGRDY_O; |
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123,25 → 132,12
wire [`MAX_CORES-1:0] wRCommited; |
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assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3]; |
assign GRDY_O = wGReady[0] & wGReady[1] & wGReady[2] & wGReady[3]; |
//---------------------------------------------------------------- |
//The next secuencial logic just AND all the wDone signals |
//I know that it would be much more elgant to just do parallel: |
//assign DONE_O = wDone[0] & wDone[1] & ... & wDone[MAX_CORES-1]; |
//However, I don't know how to achieve this with 'generate' statements |
//So coding a simple loop instead |
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3] & wRCommited[4] & wRCommited[5] & wRCommited[6] & wRCommited[7] & wRCommited[8] & wRCommited[9] & wRCommited[10] & wRCommited[11] & wRCommited[12] & wRCommited[13] & wRCommited[14] & wRCommited[15]; |
assign GRDY_O = wGReady[0] & wGReady[1] & wGReady[2] & wGReady[3] & wGReady[4] & wGReady[5] & wGReady[6] & wGReady[7] & wGReady[8] & wGReady[9] & wGReady[10] & wGReady[11] & wGReady[12] & wGReady[13] & wGReady[14] & wGReady[15]; |
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3] & wDone[4] & wDone[5] & wDone[6] & wDone[7] & wDone[8] & wDone[9] & wDone[10] & wDone[11] & wDone[12] & wDone[13] & wDone[14] & wDone[15]; |
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/* |
always @ (posedge CLK_I) |
begin : AND_DONE_SIGNALS |
integer k; |
DONE_O = wDone[0]; |
for (k=0;k<=`MAX_CORES;k=k+1) |
DONE_O=DONE_O & wDone[k+1]; |
end |
*/ |
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3]; //Replace this by a counter?? |
//---------------------------------------------------------------- |
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Module_BusArbitrer ARB1 |
155,11 → 151,7
); |
//---------------------------------------------------------------- |
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// assign DAT_O = wDAT_O[ wBusSelect ]; |
// assign TGA_O = wTGA_O[ wBusSelect ]; |
// assign ADR_O = wADR_O[ wBusSelect ]; |
// assign STB_O = wSTB_O[ wBusSelect ]; |
// assign WE_O = wWE_O[ wBusSelect ]; |
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assign ACK_O = wACK_O[ wBusSelect]; |
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wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0]; |
192,14 → 184,9
.CREG_I( CREG_I ), |
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//Master Signals |
//.WE_O ( wWE_O[i] ), |
//.STB_O( wSTB_O[i] ), |
.ACK_O( wACK_O[i] ), |
// .DAT_O( wDAT_O[i] ), |
//.ADR_O( wADR_O[i] ), |
.CYC_O( wBusRequest[i] ), |
.GNT_I( wBusGranted[i] ), |
//.TGA_O( wTGA_O[i] ), |
`ifdef DEBUG |
.iDebug_CoreID( i ), |
`endif |
208,8 → 195,6
.OMEM_ADR_O( wOMEM_Address[i] ), |
.OMEM_DAT_O( wOMEM_Dat[i] ), |
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.TMEM_DAT_I( wCrossBarDataCollumn[i] ), |
.TMEM_ADR_O( wTMemReadAdr[i] ), |
.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ), |
244,7 → 229,7
.Q(wGReady[i]) |
); |
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 500000 ) OMEM //10k mem |
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 250000 ) OMEM //500000 ) OMEM |
( |
.Clock( CLK_I ), |
.iWriteEnable( wOMem_WE[i] ), |
264,7 → 249,7
//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can |
//be 1 at any given point in time. All bits zero means, |
//we are not requesting to read from any memory bank. |
SELECT_1_TO_N # ( 8, 4 ) READDRQ |
SELECT_1_TO_N # ( `WIDTH, `MAX_CORES ) READDRQ |
( |
.Sel(wCoreBankSelect[ i]), |
.En(wCORE_2_TMEM__Req[i]), |
276,7 → 261,7
//virtual adress into physical adress (relative to the bank) like this |
//fadr = vadr / n = vadr >> log2(n) |
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assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> ((`MAX_TMEM_BANKS)/2)); |
assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> `MAX_CORE_BITS); |
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//Connect the granted signal to Arbiter of the Bank we want to read from |
assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i]; |
314,7 → 299,7
( |
.Clock( CLK_I ), |
.Reset( RST_I ), |
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),//wBankReadRequest[Bank] ), //The cores requesting to read from this Bank |
.iRequest( {wBankReadRequest[15][Bank],wBankReadRequest[14][Bank],wBankReadRequest[13][Bank],wBankReadRequest[12][Bank],wBankReadRequest[11][Bank],wBankReadRequest[10][Bank],wBankReadRequest[9][Bank],wBankReadRequest[8][Bank],wBankReadRequest[7][Bank],wBankReadRequest[6][Bank],wBankReadRequest[5][Bank],wBankReadRequest[4][Bank],wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}), |
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank |
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank |
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