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- This comparison shows the changes necessary to convert path
/theia_gpu/branches/gpu_8_cores/rtl/Collaterals
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Rev 136 → Rev 138
/aDefinitions.v
28,10 → 28,10
for simulation perfomance reasons mainly. |
*******************************************************************************/ |
|
`define MAX_CORES 16 //The number of cores, make sure you update MAX_CORE_BITS! |
`define MAX_CORE_BITS 4 // 2 ^ MAX_CORE_BITS = MAX_CORES |
`define MAX_TMEM_BANKS 16 //The number of memory banks for TMEM |
`define SELECT_ALL_CORES `MAX_CORES'b1111111111111111 //XXX: Change for more cores |
`define MAX_CORES 8 //The number of cores, make sure you update MAX_CORE_BITS! |
`define MAX_CORE_BITS 3 // 2 ^ MAX_CORE_BITS = MAX_CORES |
`define MAX_TMEM_BANKS 8 //The number of memory banks for TMEM |
`define SELECT_ALL_CORES `MAX_CORES'b11111111 //XXX: Change for more cores |
//--------------------------------------------------------------------------------- |
//Verilog provides a `default_nettype none compiler directive. When |
//this directive is set, implicit data types are disabled, which will make any |