URL
https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
Subversion Repositories theia_gpu
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- This comparison shows the changes necessary to convert path
/theia_gpu/branches/gpu_8_cores
- from Rev 128 to Rev 129
- ↔ Reverse comparison
Rev 128 → Rev 129
/rtl/Collaterals/aDefinitions.v
28,9 → 28,9
for simulation perfomance reasons mainly. |
*******************************************************************************/ |
|
`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS! |
`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES |
`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM |
`define MAX_CORES 8 //The number of cores, make sure you update MAX_CORE_BITS! |
`define MAX_CORE_BITS 3 // 2 ^ MAX_CORE_BITS = MAX_CORES |
`define MAX_TMEM_BANKS 8 //The number of memory banks for TMEM |
//--------------------------------------------------------------------------------- |
//Verilog provides a `default_nettype none compiler directive. When |
//this directive is set, implicit data types are disabled, which will make any |
/rtl/GPU/TOP/Theia.v
1,5 → 1,24
`timescale 1ns / 1ps |
`include "aDefinitions.v" |
/********************************************************************************** |
Theia, Ray Cast Programable graphic Processing Unit. |
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com) |
|
This program is free software; you can redistribute it and/or |
modify it under the terms of the GNU General Public License |
as published by the Free Software Foundation; either version 2 |
of the License, or (at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
|
***********************************************************************************/ |
|
//--------------------------------------------------------------------------- |
module THEIA |
12,21 → 31,13
//when this gets asserted (see documentation) |
//Wish Bone Interface |
input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone) |
//output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone) |
input wire ACK_I, //Input ack |
output wire ACK_O, //Output ack |
//output wire [`WB_WIDTH-1:0] ADR_O, //Output address |
input wire [`WB_WIDTH-1:0] ADR_I, //Input address |
//output wire WE_O, //Output write enable |
input wire WE_I, //Input write enable |
//output wire STB_O, //Strobe signal, see wishbone documentation |
input wire STB_I, //Strobe signal, see wishbone documentation |
//output wire CYC_O, //Bus cycle signal, see wishbone documentation |
input wire CYC_I, //Bus cycle signal, see wishbone documentation |
//output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation |
input wire [1:0] TGA_I, //Input address tag, see THEAI documentation |
//output wire [1:0] TGA_O, //Output address tag, see THEAI documentation |
//input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation |
input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed) |
input wire [`MAX_CORES-1:0] RENDREN_I, |
|
85,11 → 96,10
wire [1:0] wTGA_I[`MAX_CORES-1:0]; |
|
|
//wire [`MAX_CORES-1:0] wTMEM_ACK_I; |
|
wire [`WB_WIDTH-1:0] wTMEM_Data; |
wire [`WB_WIDTH-1:0] wTMEM_Address[`MAX_CORES-1:0]; |
wire [`WB_WIDTH-1:0] wTMEM_ReadAddr; |
//wire [`MAX_CORES-1:0] wTMEM_STB_O; |
wire [`MAX_CORES-1:0] wTMEM_Resquest; |
wire [`MAX_CORES-1:0] wTMEM_Granted; |
|
113,7 → 123,6
wire wTMEM_2_Core__Grant[`MAX_CORES-1:0]; |
|
wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0]; |
//wire [`WB_WIDTH-1:0] wTMEM_2_Core_Data[`MAX_CORES-1:0]; //Vertical grid Buses going to each core. |
wire[7:0] wCoreBankSelect[`MAX_CORES-1:0]; |
wire [`MAX_CORES-1:0] wGRDY_O; |
|
123,8 → 132,8
wire [`MAX_CORES-1:0] wRCommited; |
|
|
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3]; |
assign GRDY_O = wGReady[0] & wGReady[1] & wGReady[2] & wGReady[3]; |
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3] & wRCommited[4] & wRCommited[5] & wRCommited[6] & wRCommited[7]; |
assign GRDY_O = wGReady[0] & wGReady[1] & wGReady[2] & wGReady[3] & wGReady[4] & wGReady[5] & wGReady[6] & wGReady[7]; |
//---------------------------------------------------------------- |
//The next secuencial logic just AND all the wDone signals |
//I know that it would be much more elgant to just do parallel: |
141,7 → 150,7
DONE_O=DONE_O & wDone[k+1]; |
end |
*/ |
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3]; //Replace this by a counter?? |
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3] & wDone[4] & wDone[5] & wDone[6] & wDone[7]; //Replace this by a counter?? |
//---------------------------------------------------------------- |
|
Module_BusArbitrer ARB1 |
155,11 → 164,7
); |
//---------------------------------------------------------------- |
|
// assign DAT_O = wDAT_O[ wBusSelect ]; |
// assign TGA_O = wTGA_O[ wBusSelect ]; |
// assign ADR_O = wADR_O[ wBusSelect ]; |
// assign STB_O = wSTB_O[ wBusSelect ]; |
// assign WE_O = wWE_O[ wBusSelect ]; |
|
assign ACK_O = wACK_O[ wBusSelect]; |
|
wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0]; |
192,14 → 197,9
.CREG_I( CREG_I ), |
|
//Master Signals |
//.WE_O ( wWE_O[i] ), |
//.STB_O( wSTB_O[i] ), |
.ACK_O( wACK_O[i] ), |
// .DAT_O( wDAT_O[i] ), |
//.ADR_O( wADR_O[i] ), |
.CYC_O( wBusRequest[i] ), |
.GNT_I( wBusGranted[i] ), |
//.TGA_O( wTGA_O[i] ), |
`ifdef DEBUG |
.iDebug_CoreID( i ), |
`endif |
208,8 → 208,6
.OMEM_ADR_O( wOMEM_Address[i] ), |
.OMEM_DAT_O( wOMEM_Dat[i] ), |
|
|
|
.TMEM_DAT_I( wCrossBarDataCollumn[i] ), |
.TMEM_ADR_O( wTMemReadAdr[i] ), |
.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ), |
244,7 → 242,7
.Q(wGReady[i]) |
); |
|
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 500000 ) OMEM //10k mem |
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 250000 ) OMEM //500000 ) OMEM |
( |
.Clock( CLK_I ), |
.iWriteEnable( wOMem_WE[i] ), |
264,7 → 262,7
//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can |
//be 1 at any given point in time. All bits zero means, |
//we are not requesting to read from any memory bank. |
SELECT_1_TO_N # ( 8, 4 ) READDRQ |
SELECT_1_TO_N # ( `MAX_TMEM_BANKS, `MAX_CORES ) READDRQ |
( |
.Sel(wCoreBankSelect[ i]), |
.En(wCORE_2_TMEM__Req[i]), |
276,7 → 274,7
//virtual adress into physical adress (relative to the bank) like this |
//fadr = vadr / n = vadr >> log2(n) |
|
assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> ((`MAX_TMEM_BANKS)/2)); |
assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> `MAX_CORE_BITS); |
|
//Connect the granted signal to Arbiter of the Bank we want to read from |
assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i]; |
314,7 → 312,7
( |
.Clock( CLK_I ), |
.Reset( RST_I ), |
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),//wBankReadRequest[Bank] ), //The cores requesting to read from this Bank |
.iRequest( {wBankReadRequest[7][Bank],wBankReadRequest[6][Bank],wBankReadRequest[5][Bank],wBankReadRequest[4][Bank],wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),//wBankReadRequest[Bank] ), //The cores requesting to read from this Bank |
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank |
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank |
|
/rtl/GPU/CORES/CONTROL/Unit_Control.v
156,7 → 156,7
`ifdef DEBUG_CU |
always @ ( wHit ) |
begin |
`LOGME "*** Triangle HIT ***\n"); |
$display( "*** Triangle HIT ***\n"); |
end |
`endif |
|
180,7 → 180,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"%d CU_AFTER_RESET_STATE\n",$time); |
$display("%d CU_AFTER_RESET_STATE\n",$time); |
`endif |
|
//oRamBusOwner <= 0; |
207,7 → 207,7
begin |
//$display("CORE: %d CU_WAIT_FOR_INITIAL_CONFIGURATION", iDebug_CoreID); |
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_WAIT_FOR_INITIAL_CONFIGURATION\n",$time); |
// $display("%d Control: CU_WAIT_FOR_INITIAL_CONFIGURATION\n",$time); |
// `endif |
|
//oRamBusOwner <= 0; |
263,7 → 263,7
begin |
//$display("CORE: %d CU_CLEAR_REGISTERS", iDebug_CoreID); |
`ifdef DEBUG_CU |
`LOGME"%d CU_CLEAR_REGISTERS\n",$time); |
$display("%d CU_CLEAR_REGISTERS\n",$time); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
289,7 → 289,7
`CU_WAIT_CLEAR_REGISTERS: |
begin |
// `ifdef DEBUG_CU |
// `LOGME"%d CU_WAIT_CLEAR_REGISTERS\n",$time); |
// $display("%d CU_WAIT_CLEAR_REGISTERS\n",$time); |
// `endif |
//$display("CORE: %d CU_WAIT_CLEAR_REGISTERS", iDebug_CoreID); |
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
318,7 → 318,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"%d CU_ACK_CLEAR_REGISTERS\n", $time); |
$display("%d CU_ACK_CLEAR_REGISTERS\n", $time); |
`endif |
|
//$display("CORE: %d CU_ACK_CLEAR_REGISTERS", iDebug_CoreID); |
348,7 → 348,7
begin |
|
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_WAIT_FOR_CONFIG_DATA_READ\n",$time); |
// $display("%d Control: CU_WAIT_FOR_CONFIG_DATA_READ\n",$time); |
// `endif |
|
|
380,7 → 380,7
begin |
//$display("CORE: %d CU_PRECALCULATE_CONSTANTS", iDebug_CoreID); |
`ifdef DEBUG_CU |
`LOGME"%d Control: CU_PRECALCULATE_CONSTANTS\n", $time); |
$display("%d Control: CU_PRECALCULATE_CONSTANTS\n", $time); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
405,7 → 405,7
`CU_WAIT_FOR_CONSTANT: |
begin |
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_WAIT_FOR_CONSTANT\n", $time); |
// $display("%d Control: CU_WAIT_FOR_CONSTANT\n", $time); |
// `endif |
|
|
435,7 → 435,7
begin |
//$display("CORE: %d CU_ACK_PRECALCULATE_CONSTANTS", iDebug_CoreID); |
`ifdef DEBUG_CU |
`LOGME"%d Control: CU_ACK_PRECALCULATE_CONSTANTS\n", $time); |
$display("%d Control: CU_ACK_PRECALCULATE_CONSTANTS\n", $time); |
`endif |
|
|
462,7 → 462,7
`CU_TRIGGER_USERCONSTANTS: |
begin |
`ifdef DEBUG_CU |
`LOGME"%d Control: CU_TRIGGER_USERCONSTANTS\n",$time); |
$display("%d Control: CU_TRIGGER_USERCONSTANTS\n",$time); |
`endif |
|
//$display("CORE: %d CU_TRIGGER_USERCONSTANTS", iDebug_CoreID); |
489,7 → 489,7
begin |
|
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_WAIT_FOR_RGU\n",$time); |
// $display("%d Control: CU_WAIT_FOR_RGU\n",$time); |
// `endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
517,7 → 517,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"%d Control: CU_ACK_RGU\n",$time); |
$display("%d Control: CU_ACK_RGU\n",$time); |
`endif |
|
//$display("CORE: %d CU_ACK_USERCONSTANTS", iDebug_CoreID); |
574,7 → 574,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"CORE: %d CU_TRIGGER_RGU", iDebug_CoreID); |
$display("CORE: %d CU_TRIGGER_RGU", iDebug_CoreID); |
`endif |
|
|
600,7 → 600,7
begin |
|
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_WAIT_FOR_RGU\n",$time); |
// $display("%d Control: CU_WAIT_FOR_RGU\n",$time); |
// `endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
628,7 → 628,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"CORE: %d CU_ACK_RGU", iDebug_CoreID); |
$display("CORE: %d CU_ACK_RGU", iDebug_CoreID); |
`endif |
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
oCodeInstructioPointer <= 0; |
656,7 → 656,7
begin |
////$display("CU_TRIGGER_TCC"); |
`ifdef DEBUG_CU |
`LOGME"%d CORE %d Control: CU_TRIGGER_TCC\n",$time,iDebug_CoreID); |
$display("%d CORE %d Control: CU_TRIGGER_TCC\n",$time,iDebug_CoreID); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
748,7 → 748,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"%d CORE %d Control: CU_CHECK_HIT\n",$time,iDebug_CoreID); |
$display("%d CORE %d Control: CU_CHECK_HIT\n",$time,iDebug_CoreID); |
`endif |
|
|
783,7 → 783,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"%d Control: CU_TRIGGER_PSU_WITH_TEXTURE\n",$time); |
$display("%d Control: CU_TRIGGER_PSU_WITH_TEXTURE\n",$time); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
833,7 → 833,7
`CU_TRIGGER_MAIN: |
begin |
`ifdef DEBUG_CU |
`LOGME"%d CORE: %d Control: CU_TRIGGER_MAIN\n",$time,iDebug_CoreID); |
$display("%d CORE: %d Control: CU_TRIGGER_MAIN\n",$time,iDebug_CoreID); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
860,7 → 860,7
`CU_WAIT_FOR_MAIN: |
begin |
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_WAIT_FOR_MAIN\n",$time); |
// $display("%d Control: CU_WAIT_FOR_MAIN\n",$time); |
// `endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
894,7 → 894,7
`CU_ACK_MAIN: |
begin |
`ifdef DEBUG_CU |
`LOGME"%d CORE: %d Control: CU_ACK_MAIN\n",$time, iDebug_CoreID); |
$display("%d CORE: %d Control: CU_ACK_MAIN\n",$time, iDebug_CoreID); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_GFU; |
929,7 → 929,7
begin |
|
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_TRIGGER_PSU\n",$time); |
// $display("%d Control: CU_TRIGGER_PSU\n",$time); |
// `endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
958,7 → 958,7
`CU_ACK_PSU: |
begin |
`ifdef DEBUG_CU |
`LOGME"%d CORE: %d Control: CU_ACK_PSU\n",$time, iDebug_CoreID); |
$display("%d CORE: %d Control: CU_ACK_PSU\n",$time, iDebug_CoreID); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
989,7 → 989,7
`CU_TRIGGER_NPU: //Next Pixel Unit |
begin |
`ifdef DEBUG_CU |
`LOGME"%d CORE: %d Control: CU_TRIGGER_NPU\n",$time, iDebug_CoreID); |
$display("%d CORE: %d Control: CU_TRIGGER_NPU\n",$time, iDebug_CoreID); |
`endif |
$write("*"); |
|
1042,7 → 1042,7
`CU_ACK_NPU: |
begin |
`ifdef DEBUG_CU |
`LOGME"%d CORE: %d Control: CU_ACK_NPU\n",$time, iDebug_CoreID); |
$display("%d CORE: %d Control: CU_ACK_NPU\n",$time, iDebug_CoreID); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
1098,7 → 1098,7
`CU_TRIGGER_USERPIXELSHADER: |
begin |
`ifdef DEBUG_CU |
`LOGME"%d Control: CU_TRIGGER_PSU\n",$time); |
$display("%d Control: CU_TRIGGER_PSU\n",$time); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
1124,7 → 1124,7
begin |
|
// `ifdef DEBUG_CU |
// `LOGME"%d Control: CU_TRIGGER_PSU\n",$time); |
// $display("%d Control: CU_TRIGGER_PSU\n",$time); |
// `endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
1153,7 → 1153,7
`CU_ACK_USERPIXELSHADER: |
begin |
`ifdef DEBUG_CU |
`LOGME"%d Control: CU_ACK_PSU\n",$time); |
$display("%d Control: CU_ACK_PSU\n",$time); |
`endif |
|
//oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE; |
1183,7 → 1183,7
begin |
|
`ifdef DEBUG_CU |
`LOGME"%d Control: ERROR Undefined State\n",$time); |
$display("%d Control: ERROR Undefined State\n",$time); |
`endif |
|
//oRamBusOwner <= 0; |
/rtl/GPU/HOST/Module_Host.v
39,7 → 39,7
`define SELECT_INST_MEM 3'b00 |
`define SELECT_SCENE_MEM 3'b01 |
`define SELECT_GEO_MEM 3'b10 |
`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores |
`define SELECT_ALL_CORES `MAX_CORES'b11111111 //XXX: Change for more cores |
|
`define HOST_IDLE 0 |
`define HOST_WRITE_INSTRUCTION 1 |