OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /theia_gpu/branches/icarus_version/rtl
    from Rev 173 to Rev 174
    ↔ Reverse comparison
  •

Rev 173 → Rev 174

/Unit_MEM.v
1,5 → 1,11
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Module_RAM.v"
`include "Module_ROM.v"
`include "Module_SwapMemory.v"
`include "Module_ControlRegister.v"
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
340,4 → 346,4
 
 
endmodule
//-------------------------------------------------------------------
//-------------------------------------------------------------------
/Module_ExecutionFSM.v
1,5 → 1,7
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATAOR
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
400,4 → 402,4
end //always
`endif
 
endmodule
endmodule
/Module_Host.v
1,8 → 1,10
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Module_HostWBM.v"
`endif
 
 
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
34,7 → 36,7
 
 
`define MAX_VERTEX_IN_FRAME `WIDTH'd7 // WAS 8'd6
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
`define TAG_DATA_ADDRESS_TYPE 2'b10
`define SELECT_INST_MEM 3'b00
`define SELECT_SCENE_MEM 3'b01
63,39 → 65,53
//---------------------------------------------------------------
module Module_Host
(
input wire Clock,
input wire Reset,
input wire iEnable,
input wire iHostDataReadConfirmed,
input wire [`WB_WIDTH-1:0] iMemorySize,
input wire [`WB_WIDTH-1:0] iPrimitiveCount,
//To Memory
output wire [`WB_WIDTH-1:0] oReadAddress,
input wire [`WB_WIDTH-1:0] iReadData,
input wire iGPUCommitedResults,
//To Hub/Switch
output wire [`MAX_CORES-1:0] oCoreSelectMask,
output reg [1:0] oMemSelect,
output wire [`WB_WIDTH-1:0] DAT_O,
output wire [`WB_WIDTH-1:0] ADR_O,
output reg[1:0] TGA_O,
output reg[`MAX_CORES-1:0] RENDREN_O,
output wire CYC_O,
output wire STB_O,
output reg MST_O,
output wire WE_O,
input wire GRDY_I, //This means all the cores are done rading the primitive we send
output reg GACK_O, //We set this to ACK that the cored read the primitive
output wire STDONE_O,
output reg oHostDataAvailable,
input wire iGPUDone,
`ifndef NO_DISPLAY_STATS
input wire [`WIDTH-1:0] iDebugWidth,
`endif
input wire ACK_I
input wire Clock,
input wire Reset,
input wire iEnable,
input wire iHostDataReadConfirmed,
input wire [`WB_WIDTH-1:0] iMemorySize,
input wire [`WB_WIDTH-1:0] iPrimitiveCount,
//To Memory
output wire [`WB_WIDTH-1:0] oReadAddress,
input wire [`WB_WIDTH-1:0] iReadData,
input wire iGPUCommitedResults,
//To Hub/Switch
output reg [`MAX_CORES-1:0] oCoreSelectMask,
output reg [1:0] oMemSelect,
output wire [`WB_WIDTH-1:0] DAT_O,
output wire [`WB_WIDTH-1:0] ADR_O,
output reg[1:0] TGA_O,
output reg[`MAX_CORES-1:0] RENDREN_O,
output wire CYC_O,
output wire STB_O,
output reg MST_O,
output wire WE_O,
input wire GRDY_I, //This means all the cores are done rading the primitive we send
output reg GACK_O, //We set this to ACK that the cored read the primitive
output wire STDONE_O,
output reg oHostDataAvailable,
input wire iGPUDone,
`ifndef NO_DISPLAY_STATS
input wire [`WIDTH-1:0] iDebugWidth,
`endif
 
input wire ACK_I
);
wire wGPUDone;
 
//Need this flop to break combinatorial loop asserted by verilator!
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_DONE
(
.Clock(Clock),
.Reset(Reset),
.Enable( 1'b1 ),
.D(iGPUDone),
.Q(wGPUDone)
);
//---------------------------------------------------------------
wire wLastPrimitive;
assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
115,41 → 131,45
 
assign WE_O = MST_O;
 
assign oCoreSelectMask =
(rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
//assign oCoreSelectMask =
// (rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
 
wire wLastCoreSelected;
assign wLastCoreSelected = wCoreSelect[`MAX_CORES-1];
assign wLastValidReadAddress =
(oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
(oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
 
wire wLastParameter;
assign wLastParameter = (oReadAddress >= 32'h12) ? 1'b1 : 1'b0;
//--------------------------------------------------------
UPCOUNTER_POSEDGE # (`WB_WIDTH ) UPWADDR
(
.Clock( Clock ),
.Reset( Reset | rSetWriteAddr ),
.Enable( iEnable & wWBMDone ),
.Initial( rInitialWriteAddress ),
.Q( wWriteAddress )
);
UPCOUNTER_POSEDGE # (`WB_WIDTH ) UPWADDR
(
.Clock( Clock ),
.Reset( Reset | rSetWriteAddr ),
.Enable( iEnable & wWBMDone ),
.Initial( rInitialWriteAddress ),
.Q( wWriteAddress )
);
 
 
UPCOUNTER_POSEDGE # ( 32 ) PRIMCOUNT
(
.Clock( Clock ),
.Reset( Reset | rResetVertexCount ),
.Enable( iEnable & wWBMDone ),
.Initial( `WIDTH'b1 ),
.Q( wVertexCount )
);
UPCOUNTER_POSEDGE # ( 32 ) PRIMCOUNT
(
.Clock( Clock ),
.Reset( Reset | rResetVertexCount ),
.Enable( iEnable & wWBMDone ),
.Initial( `WIDTH'b1 ),
.Q( wVertexCount )
);
//--------------------------------------------------------
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
(
.Clock( Clock ),
.Reset( Reset ),
.Initial( `MAX_CORES'b1 ),
.Enable( rIncCoreSelect ),
.O( wCoreSelect )
.Clock( Clock ),
.Reset( Reset ),
.Initial( `MAX_CORES'b1 ),
.Enable( rIncCoreSelect ),
.O( wCoreSelect )
);
//--------------------------------------------------------
wire wShortCycle;
157,7 → 177,7
//for the other we send 3 packets per cycle
assign wShortCycle = (oMemSelect == `SELECT_INST_MEM) ? 1'b1 : 1'b0;
 
WBMaster WBM
WBMaster HOST_WBM
(
.Clock( Clock ),
.Reset( Reset | rWBMReset ),
166,9 → 186,9
.iWriteAddr( wWriteAddress ),
.oReadAddress( oReadAddress ),
.iReadData( iReadData ),
.iShortFlow( wShortCycle ),
.iShortFlow( wShortCycle ),
.STB_O( STB_O ),
.ACK_I( ACK_I ),
.CYC_O( CYC_O ),
179,13 → 199,13
 
//--------------------------------------------------------
// Current State Logic //
reg [7:0] rHostCurrentState,rHostNextState;
always @(posedge Clock or posedge Reset)
begin
if( Reset!=1 )
rHostCurrentState <= rHostNextState;
else
rHostCurrentState <= `HOST_IDLE;
reg [7:0] rHostCurrentState,rHostNextState;
always @(posedge Clock or posedge Reset)
begin
if( Reset!=1 )
rHostCurrentState <= rHostNextState;
else
rHostCurrentState <= `HOST_IDLE;
end
//--------------------------------------------------------
 
195,531 → 215,541
assign wLastVertexInFrame =
(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
 
// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
 
reg [31:0] StartTime;
 
// Host Finite State Machine //
always @( * )
begin
case (rHostCurrentState)
//----------------------------------------
//Wait for reset sequence to complete,
//Or until we are enabled
`HOST_IDLE:
begin
RenderedPixels = 0;
rWBMEnable = 0;
rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
rWBMReset = 0;
oMemSelect = 0;
TGA_O = 0;
MST_O = 0;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 0;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
if ( ~Reset & iEnable )
begin
$display("-I- HOST: Broadcasting User code to all Cores\n"); $fflush;
rHostNextState = `HOST_WRITE_INSTRUCTION;
end
else
rHostNextState = `HOST_IDLE;
end
//----------------------------------------
//Broadcast the instructions to all the cores
`HOST_WRITE_INSTRUCTION:
begin
StartTime = $time;
rWBMEnable = 1; //Enable Wish bone master
rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
rWBMReset = 0; //No need to reset since we just came from reset
oMemSelect = `SELECT_INST_MEM; //Start by sending the instructions
TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_INSTRUCTION;
end
//----------------------------------------
`HOST_WAIT_INSTRUCTION:
begin
rWBMEnable = ~wWBMDone;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_INST_MEM;
TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
if ( wWBMDone && ~wLastValidReadAddress )
rHostNextState = `HOST_WRITE_INSTRUCTION;
else if (wWBMDone && wLastValidReadAddress )
rHostNextState = `HOST_INITIAL_SCENE_PARAMS_STAGE;
else
rHostNextState = `HOST_WAIT_INSTRUCTION;
end
//----------------------------------------
/*
Make sure to read-pointer points to the
first memory address at te params memory
*/
`HOST_INITIAL_SCENE_PARAMS_STAGE:
begin
rWBMEnable = 0;
rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
rWBMReset = 1;
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
MST_O = 1; //Keep master signal in 1 for now
rInitialWriteAddress = 0; //We start writing from address zero now
rSetWriteAddr = 1;
rCoreBroadCast = 1; //Set to zero to unicast, starting from core 0
rIncCoreSelect = 0; //Set to unicast to the next core
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
$display("-I- HOST: Configuring Core Mask %b\n",oCoreSelectMask); $fflush;
rHostNextState = `HOST_WRITE_SCENE_PARAMS;
end
//----------------------------------------
//Broadcast the instructions to all the cores
`HOST_WRITE_SCENE_PARAMS:
begin
rWBMEnable = 1;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_SCENE_PARAMS;
end
//----------------------------------------
`HOST_WAIT_SCENE_PARAMS:
begin
rWBMEnable = ~wWBMDone;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
if ( wWBMDone && ~wLastParameter )
rHostNextState = `HOST_WRITE_SCENE_PARAMS;
else if (wWBMDone && wLastParameter )
rHostNextState = `HOST_PREPARE_CORE_CONFIG;
else
rHostNextState = `HOST_WAIT_SCENE_PARAMS;
end
//----------------------------------------
/*
This state set the read Write Address pointer to
CREG_PIXEL_2D_INITIAL_POSITION memory position,
also selects the scene MEM from the external MEM
MUX.
*/
`HOST_PREPARE_CORE_CONFIG:
begin
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
MST_O = 1; //Keep master signal in 1 for now
rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
rCoreBroadCast = 0; //Set to zero to unicast, starting from core 0
rIncCoreSelect = 0; //Set to unicast to the next core
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
end
//----------------------------------------
`HOST_UNICAST_CORE_CONFIG:
begin
rWBMEnable = 1;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 0;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_CORE_CONFIG;
end
//----------------------------------------
`HOST_WAIT_CORE_CONFIG:
begin
rWBMEnable = ~wWBMDone;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 0;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
if (wWBMDone && !(oReadAddress % 2))
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
else if (wWBMDone && (oReadAddress % 2) )
rHostNextState = `HOST_PREPARE_NEXT_CORE_CONFIG;
else
rHostNextState = `HOST_WAIT_CORE_CONFIG;
end
//----------------------------------------
/*
Reset the WBM to tell it to start reading
from address 0 at the Geometry memory.
*/
`HOST_PREPARE_NEXT_CORE_CONFIG:
begin
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
rCoreBroadCast = 0;
rIncCoreSelect = 1; //Moving to configure the next core now
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
if (wCoreSelect[`MAX_CORES-1] == 1)
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
else
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
end
//----------------------------------------
/*
Prepare the write address for the next primitive.
*/
`HOST_PREPARE_FOR_GEO_REQUESTS:
begin
rWBMEnable = 0; //Do not enable until we are resquested
rInitiaReadAddr = 32'hA; //Start reading from addr 0 @ GEO MEM
rWBMReset = 1; //Tell WBM to start reading from the addr bellow
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
rCoreBroadCast = 1; //From now on we only broadcast
rIncCoreSelect = 0; //Ignored during broadcasts
RENDREN_O = 0;
rResetVertexCount = 1;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
if (iGPUDone)
rHostNextState = `HOST_GPU_EXECUTION_DONE;
else
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
end
//----------------------------------------
`HOST_ACK_GEO_REQUEST:
begin
rWBMEnable = 0; //Do not enable until we are resquested
rInitiaReadAddr = 0; //Ignored
rWBMReset = 0; //Ignored
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
rCoreBroadCast = 1; //From now on we only broadcast
rIncCoreSelect = 0; //Ignored during broadcasts
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 1;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
end
//----------------------------------------
/*
Send the next primitive to the HUB/SWITCH unit
so that it gets broadcasted to all the cores
*/
`HOST_BROADCAST_NEXT_VERTEX:
begin
rWBMEnable = 1; //Start the Transmition
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1; //Start the Transmition
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_FOR_VERTEX;
end
//----------------------------------------
`HOST_WAIT_FOR_VERTEX:
begin
rWBMEnable = ~wWBMDone; //Disable WBM when it is donw
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1; //Start the Transmition
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
if (wWBMDone & ~wLastVertexInFrame )
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
else if (wWBMDone & wLastVertexInFrame )
rHostNextState = `HOST_GET_PRIMITIVE_COUNT;
else
rHostNextState = `HOST_WAIT_FOR_VERTEX;
/*
if (wWBMDone)
rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
else
rHostNextState = `HOST_WAIT_FOR_VERTEX;
*/
end
//----------------------------------------
`HOST_GET_PRIMITIVE_COUNT:
begin
rWBMEnable = 0; //Disable WBM when it is donw
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1; //Start the Transmition
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;//1;
if (wVertexCount >= iPrimitiveCount)
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
else
rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
end
//----------------------------------------
/*
we wait until all the cores are ready for the next primitive,
this happens when the iHostDataReadConfirmed signal
gets asserted
*/
`HOST_WAIT_DATA_READ_CONFIRMATION:
begin
rWBMEnable = 0; //Do not enable until we are resquested
rInitiaReadAddr = 0; //Ignored
rWBMReset = 0; //Continue from previous read address
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
rCoreBroadCast = 1; //From now on we only broadcast
rIncCoreSelect = 0; //Ignored during broadcasts
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 1;
if ( iHostDataReadConfirmed )
rHostNextState = `HOST_ACK_GEO_REQUEST;
else
rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
end
//----------------------------------------
`HOST_LAST_PRIMITIVE_REACHED:
begin
rWBMEnable = 0; //Disable WBM when it is donw
rInitiaReadAddr = 32'hA; //Reset primitive counter to first primitive
rWBMReset = 1; //Reset primitive counter to first primitive
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 1;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0; //Reset the vertex count to zero
GACK_O = 0;
//STDONE_O = 1;
oHostDataAvailable = 0;
begin
case (rHostCurrentState)
//----------------------------------------
//Wait for reset sequence to complete,
//Or until we are enabled
`HOST_IDLE:
begin
`ifndef VERILATOR
RenderedPixels = 0;
`endif
rWBMEnable = 0;
rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
rWBMReset = 0;
oMemSelect = 0;
TGA_O = 0;
MST_O = 0;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 0;
oCoreSelectMask = wCoreSelect;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
if ( ~Reset & iEnable )
begin
$display("-I- HOST: Broadcasting User code to all Cores\n");
`ifndef VERILATOR
$fflush;
`endif
rHostNextState = `HOST_WRITE_INSTRUCTION;
end
else
rHostNextState = `HOST_IDLE;
end
//----------------------------------------
//Broadcast the instructions to all the cores
`HOST_WRITE_INSTRUCTION:
begin
StartTime = $time;
rWBMEnable = 1; //Enable Wish bone master
rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
rWBMReset = 0; //No need to reset since we just came from reset
oMemSelect = `SELECT_INST_MEM; //Start by sending the instructions
TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_INSTRUCTION;
end
//----------------------------------------
`HOST_WAIT_INSTRUCTION:
begin
rWBMEnable = ~wWBMDone;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_INST_MEM;
TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
if ( wWBMDone && ~wLastValidReadAddress )
rHostNextState = `HOST_WRITE_INSTRUCTION;
else if (wWBMDone && wLastValidReadAddress )
rHostNextState = `HOST_INITIAL_SCENE_PARAMS_STAGE;
else
rHostNextState = `HOST_WAIT_INSTRUCTION;
end
//----------------------------------------
/*
Make sure to read-pointer points to the
first memory address at te params memory
*/
`HOST_INITIAL_SCENE_PARAMS_STAGE:
begin
rWBMEnable = 0;
rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
rWBMReset = 1;
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
MST_O = 1; //Keep master signal in 1 for now
rInitialWriteAddress = 0; //We start writing from address zero now
rSetWriteAddr = 1;
//rCoreBroadCast = 1; //Set to zero to unicast, starting from core 0
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0; //Set to unicast to the next core
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
$display("-I- HOST: Configuring Core Mask %b\n",oCoreSelectMask);
`ifndef VERILATOR
$fflush;
`endif
rHostNextState = `HOST_WRITE_SCENE_PARAMS;
end
//----------------------------------------
//Broadcast the instructions to all the cores
`HOST_WRITE_SCENE_PARAMS:
begin
rWBMEnable = 1;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_SCENE_PARAMS;
end
//----------------------------------------
`HOST_WAIT_SCENE_PARAMS:
begin
rWBMEnable = ~wWBMDone;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
if ( wWBMDone && ~wLastParameter )
rHostNextState = `HOST_WRITE_SCENE_PARAMS;
else if (wWBMDone && wLastParameter )
rHostNextState = `HOST_PREPARE_CORE_CONFIG;
else
rHostNextState = `HOST_WAIT_SCENE_PARAMS;
end
//----------------------------------------
/*
This state set the read Write Address pointer to
CREG_PIXEL_2D_INITIAL_POSITION memory position,
also selects the scene MEM from the external MEM
MUX.
*/
`HOST_PREPARE_CORE_CONFIG:
begin
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
MST_O = 1; //Keep master signal in 1 for now
rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
//rCoreBroadCast = 0; //Set to zero to unicast, starting from core 0
oCoreSelectMask = wCoreSelect;
rIncCoreSelect = 0; //Set to unicast to the next core
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
end
//----------------------------------------
`HOST_UNICAST_CORE_CONFIG:
begin
rWBMEnable = 1;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 0;
oCoreSelectMask = wCoreSelect;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_CORE_CONFIG;
end
//----------------------------------------
`HOST_WAIT_CORE_CONFIG:
begin
rWBMEnable = ~wWBMDone;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_SCENE_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 0;
oCoreSelectMask = wCoreSelect;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
if (wWBMDone && !(oReadAddress % 2))
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
else if (wWBMDone && (oReadAddress % 2) )
rHostNextState = `HOST_PREPARE_NEXT_CORE_CONFIG;
else
rHostNextState = `HOST_WAIT_CORE_CONFIG;
end
//----------------------------------------
/*
Reset the WBM to tell it to start reading
from address 0 at the Geometry memory.
*/
`HOST_PREPARE_NEXT_CORE_CONFIG:
begin
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
//rCoreBroadCast = 0;
oCoreSelectMask = wCoreSelect;
rIncCoreSelect = 1; //Moving to configure the next core now
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
if (wLastCoreSelected)//wCoreSelect[`MAX_CORES-1] == 1)
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
else
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
end
//----------------------------------------
/*
Prepare the write address for the next primitive.
*/
`HOST_PREPARE_FOR_GEO_REQUESTS:
begin
rWBMEnable = 0; //Do not enable until we are resquested
rInitiaReadAddr = 32'hA; //Start reading from addr 0 @ GEO MEM
rWBMReset = 1; //Tell WBM to start reading from the addr bellow
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
//rCoreBroadCast = 1; //From now on we only broadcast
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0; //Ignored during broadcasts
RENDREN_O = 0;
rResetVertexCount = 1;
GACK_O = 0;
oHostDataAvailable = 0;
if (wGPUDone)
rHostNextState = `HOST_GPU_EXECUTION_DONE;
else
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
end
//----------------------------------------
`HOST_ACK_GEO_REQUEST:
begin
rWBMEnable = 0; //Do not enable until we are resquested
rInitiaReadAddr = 0; //Ignored
rWBMReset = 0; //Ignored
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
//rCoreBroadCast = 1; //From now on we only broadcast
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0; //Ignored during broadcasts
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 1;
oHostDataAvailable = 0;
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
end
//----------------------------------------
/*
Send the next primitive to the HUB/SWITCH unit
so that it gets broadcasted to all the cores
*/
`HOST_BROADCAST_NEXT_VERTEX:
begin
rWBMEnable = 1; //Start the Transmition
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1; //Start the Transmition
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_WAIT_FOR_VERTEX;
end
//----------------------------------------
`HOST_WAIT_FOR_VERTEX:
begin
rWBMEnable = ~wWBMDone; //Disable WBM when it is donw
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1; //Start the Transmition
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
if (wWBMDone & ~wLastVertexInFrame )
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
else if (wWBMDone & wLastVertexInFrame )
rHostNextState = `HOST_GET_PRIMITIVE_COUNT;
else
rHostNextState = `HOST_WAIT_FOR_VERTEX;
end
//----------------------------------------
`HOST_GET_PRIMITIVE_COUNT:
begin
rWBMEnable = 0; //Disable WBM when it is donw
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1; //Start the Transmition
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;//1;
if (wVertexCount >= iPrimitiveCount)
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
else
rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
end
//----------------------------------------
/*
we wait until all the cores are ready for the next primitive,
this happens when the iHostDataReadConfirmed signal
gets asserted
*/
`HOST_WAIT_DATA_READ_CONFIRMATION:
begin
rWBMEnable = 0; //Do not enable until we are resquested
rInitiaReadAddr = 0; //Ignored
rWBMReset = 0; //Continue from previous read address
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
MST_O = 0; //The master signal goes to zero until request
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
//rCoreBroadCast = 1; //From now on we only broadcast
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0; //Ignored during broadcasts
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 1;
if ( iHostDataReadConfirmed )
rHostNextState = `HOST_ACK_GEO_REQUEST;
else
rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
end
//----------------------------------------
`HOST_LAST_PRIMITIVE_REACHED:
begin
rWBMEnable = 0; //Disable WBM when it is donw
rInitiaReadAddr = 32'hA; //Reset primitive counter to first primitive
rWBMReset = 1; //Reset primitive counter to first primitive
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 1;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = `SELECT_ALL_CORES;
rResetVertexCount = 0; //Reset the vertex count to zero
GACK_O = 0;
oHostDataAvailable = 0;
 
if (iGPUCommitedResults)
begin
`ifndef NO_DISPLAY_STATS
for (i = 0; i < `MAX_CORES; i = i + 1)
begin
$write(".");$fflush;
end
RenderedPixels = RenderedPixels + `MAX_CORES;
if ( RenderedPixels % iDebugWidth == 0)
$write("]%d\n[",RenderedPixels / iDebugWidth);$fflush;
`endif
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
end
else
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
end
//----------------------------------------
`HOST_GPU_EXECUTION_DONE:
begin
$display("THEIA Execution done in %dns\n",$time-StartTime);
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = 0;
TGA_O = 0;
MST_O = 0;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 0;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_GPU_EXECUTION_DONE;
end
//----------------------------------------
default:
begin
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = 0;
TGA_O = 0;
MST_O = 0;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
rCoreBroadCast = 0;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
//STDONE_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_IDLE;
end
//----------------------------------------
endcase
end
if (iGPUCommitedResults)
begin
`ifndef VERILATOR
`ifndef NO_DISPLAY_STATS
for (i = 0; i < `MAX_CORES; i = i + 1)
begin
$write(".");
`ifndef VERILATOR
$fflush;
`endif
end
RenderedPixels = RenderedPixels + `MAX_CORES;
if ( RenderedPixels % iDebugWidth == 0)
$write("]%d\n[",RenderedPixels / iDebugWidth);
`ifndef VERILATOR
$fflush;
`endif
`endif
`endif
 
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
end
else
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
end
//----------------------------------------
`HOST_GPU_EXECUTION_DONE:
begin
$display("THEIA Execution done in %dns\n",$time-StartTime);
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = 0;
TGA_O = 0;
MST_O = 0;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 0;
oCoreSelectMask = wCoreSelect;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_GPU_EXECUTION_DONE;
end
//----------------------------------------
default:
begin
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = 0;
TGA_O = 0;
MST_O = 0;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
//rCoreBroadCast = 0;
oCoreSelectMask = wCoreSelect;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
rHostNextState = `HOST_IDLE;
end
//----------------------------------------
endcase
end
 
endmodule
/Module_HostWBM.v
53,7 → 53,22
);
assign oDone = (iShortFlow) ? wXYZSel_Short[2] : wXYZSel_Long[3];
//`ifdef VERILATOR
wire wDone = (iShortFlow) ? wXYZSel_Short[2] : wXYZSel_Long[3];
//Adding FFD to break combinatorial loop.
//Host::wShortCycle -> WBM::iShortCycle -> WBM::wDone -> Host::wWBMDone -> Host::always ->Host::oMemSelect -> Host::wShortCycle
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_DONE
(
.Clock(Clock),
.Reset(Reset),
.Enable( 1'b1 ),
.D(wDone),
.Q(oDone)
);
//`else
// assign oDone = (iShortFlow) ? wXYZSel_Short[2] : wXYZSel_Long[3];
//`endif
assign DAT_O = iReadData;
 
assign CYC_O = iEnable;
/Module_InstructionFetch.v
1,5 → 1,9
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Collaterals.v"
`include "Module_FixedPointAddtionSubstraction.v"
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
212,4 → 216,4
 
endmodule
 
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
/Theia_Core.v
47,6 → 47,12
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Unit_Control.v"
`include "Unit_MEM.v"
`include "Unit_EXE.v"
`include "Unit_IO.v"
`endif
 
module THEIACORE
(
/Unit_IO.v
1,5 → 1,12
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Module_MEM2WBM.v"
`include "Module_OMemInterface.v"
`include "Module_TMemInterface.v"
`include "Module_WishBoneMaster.v"
`include "Module_WishBoneSlave.v"
`endif
`define ADR_IMM 1
`define ADR_POINTER 0
/**********************************************************************************
316,4 → 323,4
 
 
endmodule
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
/Module_VectorALU.v
1,5 → 1,12
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Module_Swizzle.v"
`include "Module_ArithmeticComparison.v"
`include "Module_RadixRMul.v"
`include "Module_FixedPointDivision.v"
`include "Module_FixedPointSquareRoot.v"
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
141,9 → 148,9
always @ ( * )
begin
if (iOperation == `RET)
oReturnFromSub <= OutputReady;
oReturnFromSub = OutputReady;
else
oReturnFromSub <= 1'b0;
oReturnFromSub = 1'b0;
end
 
1103,9 → 1110,10
//------------------------------------------------------------------------
//Output ready logic Stuff for Division...
//Some FFT will hopefully do the trick
 
wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC;
/* verilator lint_off UNOPTFLAT*/
wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC ;
wire wDivisionOutputReady;
/* verilator lint_on UNOPTFLAT*/
 
 
assign wAddSubAOutputReady = wAddSubA_OutputReady;
1278,4 → 1286,4
end
 
endmodule
//------------------------------------------------------------------------
//------------------------------------------------------------------------
/aDefinitions.v
27,7 → 27,7
constants are pre-compilation define directives. This is
for simulation perfomance reasons mainly.
*******************************************************************************/
 
//`define VERILATOR 1
`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM
/Module_WishBoneSlave.v
3,8 → 3,8
 
 
 
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b10
`define TAG_DATA_ADDRESS_TYPE 2'b01
`define TAG_WBS_INSTRUCTION_ADDRESS_TYPE 2'b10
`define TAG_WBS_DATA_ADDRESS_TYPE 2'b01
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
147,8 → 147,8
assign oDataBus = {wVx,wVy,wVz};
assign oInstructionBus = {wVx,wVy};
wire wIsInstructionAddress,wIsDataAddress;
assign wIsInstructionAddress = (wTGA_Latched == `TAG_INSTRUCTION_ADDRESS_TYPE) ? 1'b1 : 1'b0;
assign wIsDataAddress = (wTGA_Latched == `TAG_DATA_ADDRESS_TYPE ) ? 1'b1 : 1'b0;
assign wIsInstructionAddress = (wTGA_Latched == `TAG_WBS_INSTRUCTION_ADDRESS_TYPE) ? 1'b1 : 1'b0;
assign wIsDataAddress = (wTGA_Latched == `TAG_WBS_DATA_ADDRESS_TYPE ) ? 1'b1 : 1'b0;
 
assign oDataWriteEnable = (MST_I && !CYC_I && wIsInstructionAddress) ? 1'b1 : 1'b0;
assign oInstructionWriteEnable = ( MST_I && !CYC_I && wIsDataAddress) ? 1'b1 : 1'b0;
/Unit_Control.v
26,6 → 26,9
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Collaterals.v"
`endif
 
`define CU_AFTER_RESET_STATE 0
`define CU_WAIT_FOR_INITIAL_CONFIGURATION 1
/Unit_EXE.v
1,5 → 1,12
`timescale 1ns / 1ps
`include "aDefinitions.v"
`ifdef VERILATOR
`include "Module_InstructionEntryPoint.v"
`include "Module_InstructionFetch.v"
`include "Module_InstructionDecode.v"
`include "Module_VectorALU.v"
`include "Module_ExecutionFSM.v"
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
77,10 → 84,10
wire [`INSTRUCTION_WIDTH-1:0] CurrentInstruction;
//wire wIDU2_IFU__IDUBusy;
 
/* verilator lint_off UNOPTFLAT*/
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation /* verilator isolate_assignments*/;
/* verilator lint_on UNOPTFLAT*/
 
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation;
 
 
wire [`DATA_ROW_WIDTH-1:0] wSource0,wSource1;
wire [`DATA_ADDRESS_WIDTH-1:0] wDestination;
wire wInstructionAvailable;
272,4 → 279,4
 
 
endmodule
//---------------------------------------------------------------------
//---------------------------------------------------------------------
/Theia.v
1,23 → 1,26
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
`ifdef VERILATOR
`include "Theia_Core.v"
`endif
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
//---------------------------------------------------------------------------
135,9 → 138,9
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
assign HDL_O = wHostDataLatched[0] & wHostDataLatched[1] & wHostDataLatched[2] & wHostDataLatched[3];
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
 
 
 
 
 
//----------------------------------------------------------------
 
Module_BusArbitrer ARB1
215,22 → 218,22
 
);
UPCOUNTER_POSEDGE # (1) UP_RCOMMIT
(
UPCOUNTER_POSEDGE # (1) UP_RCOMMIT
(
.Clock( CLK_I ),
.Reset( RST_I | HDLACK_I ),
.Reset( RST_I | HDLACK_I ),
.Initial( 1'b0 ),
.Enable( wRCOMMIT_O[i] ),
.Q(wRCommited[i])
.Q(wRCommited[i])
);
UPCOUNTER_POSEDGE # (1) UP_GREADY
(
UPCOUNTER_POSEDGE # (1) UP_GREADY
(
.Clock( CLK_I ),
.Reset( RST_I | HDLACK_I ),
.Reset( RST_I | HDLACK_I ),
.Initial( 1'b0 ),
.Enable( wHDL_O[i] ),
.Q(wHostDataLatched[i])
.Q(wHostDataLatched[i])
);
 
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 250000 ) OMEM //500000 ) OMEM
303,7 → 306,7
(
.Clock( CLK_I ),
.Reset( RST_I ),
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
324,12 → 327,14
//bank at any given point in time
for (Core = 0; Core < `MAX_CORES; Core = Core + 1)
begin: CORE_CONNECT
`ifndef VERILATOR
//Connect the Data Collum of this core to the Data Row of current bank, only if the Core is looking for data stored in this bank
assign wCrossBarDataCollumn[ Core ] = ( wCoreBankSelect[ Core ] == Bank ) ? wCrossBarDataRow[ Bank ] : `WB_WIDTH'bz;
//Connect the Address Row of this Bank to the Address Column of the core, only if the Arbiter selected this core for reading
assign wCrossBarAddressRow[ Bank ] = ( wCurrentCoreSelected[ Bank ] == Core ) ? wCrossBarAdressCollumn[Core]: `WB_WIDTH'bz;
`endif
end
end
end
endgenerate
/Collaterals.v
1,3 → 1,6
`ifndef COLLATERALS_V
`define COLLATERALS_V
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
295,82 → 298,8
endmodule
 
//-----------------------------------------------------------
module UpCounter_16E
(
input wire Clock,
input wire Reset,
input wire [15:0] Initial,
input wire Enable,
output wire [15:0] Q
);
reg [15:0] Temp;
 
 
always @(posedge Clock or posedge Reset)
begin
if (Reset)
Temp = Initial;
else
if (Enable)
Temp = Temp + 1'b1;
end
assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_32
(
input wire Clock,
input wire Reset,
input wire [31:0] Initial,
input wire Enable,
output wire [31:0] Q
);
reg [31:0] Temp;
 
 
always @(posedge Clock or posedge Reset)
begin
if (Reset)
begin
Temp = Initial;
end
else
begin
if (Enable)
begin
Temp = Temp + 1'b1;
end
end
end
assign Q = Temp;
 
endmodule
//-----------------------------------------------------------
module UpCounter_3
(
input wire Clock,
input wire Reset,
input wire [2:0] Initial,
input wire Enable,
output wire [2:0] Q
);
reg [2:0] Temp;
 
 
always @(posedge Clock or posedge Reset)
begin
if (Reset)
Temp = Initial;
else
if (Enable)
Temp = Temp + 3'b1;
end
assign Q = Temp;
 
endmodule
 
 
module FFD32_POSEDGE
(
input wire Clock,
407,33 → 336,7
end
 
endmodule
//------------------------------------------------
 
module MUXFULLPARALELL_16bits_2SEL_X
(
input wire [1:0] Sel,
input wire [15:0]I1, I2, I3,
output reg [15:0] O1
);
 
 
 
always @( * )
 
begin
 
case (Sel)
 
2'b00: O1 = I1;
2'b01: O1 = I2;
2'b10: O1 = I3;
default: O1 = 16'b0;
 
endcase
 
end
 
endmodule
//------------------------------------------------
module MUXFULLPARALELL_16bits_2SEL
(
486,3 → 389,5
endmodule
//--------------------------------------------------------------
 
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.