URL
https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
Subversion Repositories theia_gpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/theia_gpu/branches/icarus_version/rtl
- from Rev 174 to Rev 175
- ↔ Reverse comparison
Rev 174 → Rev 175
/Module_Swizzle.v
23,7 → 23,7
`SWIZZLE_YYY: SwizzleX = Source0_Y; |
`SWIZZLE_ZZZ: SwizzleX = Source0_Z; |
`SWIZZLE_YXZ: SwizzleX = Source0_Y; |
default: SwizzleX = `DATA_ROW_WIDTH'd0; |
default: SwizzleX = `WIDTH'd0; |
endcase |
end |
//----------------------------------------------------- |
34,7 → 34,7
`SWIZZLE_YYY: SwizzleY = Source0_Y; |
`SWIZZLE_ZZZ: SwizzleY = Source0_Z; |
`SWIZZLE_YXZ: SwizzleY = Source0_X; |
default: SwizzleY = `DATA_ROW_WIDTH'd0; |
default: SwizzleY = `WIDTH'd0; |
endcase |
end |
//----------------------------------------------------- |
45,7 → 45,7
`SWIZZLE_YYY: SwizzleZ = Source0_Y; |
`SWIZZLE_ZZZ: SwizzleZ = Source0_Z; |
`SWIZZLE_YXZ: SwizzleZ = Source0_Z; |
default: SwizzleZ = `DATA_ROW_WIDTH'd0; |
default: SwizzleZ = `WIDTH'd0; |
endcase |
end |
//----------------------------------------------------- |
/Module_RadixRMul.v
302,18 → 302,19
wPartialResult1_4,wPartialResult1_5,wPartialResult1_6,wPartialResult1_7; |
|
|
assign wPartialResult1_0 = (wPartialResult0) + (wPartialResult1<<2); |
assign wPartialResult1_1 = (wPartialResult2 << 4) + (wPartialResult3<<6); |
assign wPartialResult1_2 = (wPartialResult4 << 8) + (wPartialResult5<<10); |
assign wPartialResult1_3 = (wPartialResult6 << 12)+ (wPartialResult7<<14); |
assign wPartialResult1_4 = (wPartialResult8 << 16)+ (wPartialResult9<<18); |
assign wPartialResult1_5 = (wPartialResult10 << 20) + (wPartialResult11<< 22); |
assign wPartialResult1_6 = (wPartialResult12 << 24) + (wPartialResult13 << 26); |
assign wPartialResult1_7 = (wPartialResult14 << 28) + (wPartialResult15 << 30); |
|
assign wPartialResult1_0 = ({32'b0,wPartialResult0}) + ({32'b0,wPartialResult1}<<2); |
assign wPartialResult1_1 = ({32'b0,wPartialResult2} << 4) + ({32'b0,wPartialResult3}<<6); |
assign wPartialResult1_2 = ({32'b0,wPartialResult4} << 8) + ({32'b0,wPartialResult5}<<10); |
assign wPartialResult1_3 = ({32'b0,wPartialResult6} << 12)+ ({32'b0,wPartialResult7}<<14); |
assign wPartialResult1_4 = ({32'b0,wPartialResult8} << 16)+ ({32'b0,wPartialResult9}<<18); |
assign wPartialResult1_5 = ({32'b0,wPartialResult10} << 20) + ({32'b0,wPartialResult11}<< 22); |
assign wPartialResult1_6 = ({32'b0,wPartialResult12} << 24) + ({32'b0,wPartialResult13} << 26); |
assign wPartialResult1_7 = ({32'b0,wPartialResult14} << 28) + ({32'b0,wPartialResult15} << 30); |
|
|
|
|
wire [63:0] wPartialResult2_0,wPartialResult2_1,wPartialResult2_2,wPartialResult2_3; |
|
assign wPartialResult2_0 = wPartialResult1_0 + wPartialResult1_1; |
/Module_ExecutionFSM.v
21,55 → 21,54
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
|
***********************************************************************************/ |
`define EXEU_AFTER_RESET 0 |
`define EXEU_INITIAL_STATE 1 |
`define EXEU_WAIT_FOR_DECODE 2 |
`define EXEU_FETCH_DECODED_INST 3 |
`define EXEU_WAIT_FOR_ALU_EXECUTION 4 |
`define EXEU_WRITE_BACK_TO_RAM 5 |
`define EXEU_HANDLE_JUMP 7 |
`define EXEU_AFTER_RESET 0 |
`define EXEU_INITIAL_STATE 1 |
`define EXEU_WAIT_FOR_DECODE 2 |
`define EXEU_FETCH_DECODED_INST 3 |
`define EXEU_WAIT_FOR_ALU_EXECUTION 4 |
`define EXEU_WRITE_BACK_TO_RAM 5 |
`define EXEU_HANDLE_JUMP 7 |
|
|
|
module ExecutionFSM |
( |
input wire Clock, |
input wire Reset, |
input wire Clock, |
input wire Reset, |
|
input wire iDecodeDone, |
input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation, |
input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination, |
inout wire[`DATA_ROW_WIDTH-1:0] RAMBus, |
//output reg ReadyForNextInstruction, |
output wire oJumpFlag , |
output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp , |
output wire oRAMWriteEnable , |
output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress , |
output wire oExeLatchedValues, |
output reg oBusy , |
input wire iDecodeDone, |
input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation, |
input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination, |
inout wire[`DATA_ROW_WIDTH-1:0] RAMBus, |
output wire oJumpFlag , |
output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp , |
output wire oRAMWriteEnable , |
output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress , |
output wire oExeLatchedValues, |
output reg oBusy , |
|
//ALU ports and control signals |
output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation, |
output wire [`WIDTH-1:0] oALUChannelX1, |
output wire [`WIDTH-1:0] oALUChannelY1, |
output wire [`WIDTH-1:0] oALUChannelZ1, |
output wire [`WIDTH-1:0] oALUChannelX2, |
output wire [`WIDTH-1:0] oALUChannelY2, |
output wire [`WIDTH-1:0] oALUChannelZ2, |
output wire oTriggerALU, |
output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation, |
output wire [`WIDTH-1:0] oALUChannelX1, |
output wire [`WIDTH-1:0] oALUChannelY1, |
output wire [`WIDTH-1:0] oALUChannelZ1, |
output wire [`WIDTH-1:0] oALUChannelX2, |
output wire [`WIDTH-1:0] oALUChannelY2, |
output wire [`WIDTH-1:0] oALUChannelZ2, |
output wire oTriggerALU, |
|
input wire [`WIDTH-1:0] iALUResultX, |
input wire [`WIDTH-1:0] iALUResultY, |
input wire [`WIDTH-1:0] iALUResultZ, |
input wire iALUOutputReady, |
input wire iBranchTaken, |
input wire iBranchNotTaken, |
input wire [`WIDTH-1:0] iALUResultX, |
input wire [`WIDTH-1:0] iALUResultY, |
input wire [`WIDTH-1:0] iALUResultZ, |
input wire iALUOutputReady, |
input wire iBranchTaken, |
input wire iBranchNotTaken, |
|
|
`ifdef DEBUG |
input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP, |
input wire [`MAX_CORES-1:0] iDebug_CoreID, |
input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP, |
input wire [`MAX_CORES-1:0] iDebug_CoreID, |
`endif |
//Data forward Signals |
output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination |
94,11 → 93,11
|
//Don't allow me to write back back if the operation is a NOP |
`ifdef DEBUG |
assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && |
(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT; |
assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && |
(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT; |
`else |
assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP; |
`endif |
assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP; |
`endif |
|
|
assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz; |
115,11 → 114,11
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination |
( |
.Clock( Clock ),//wLatchNow ), |
.Reset( Reset), |
.Enable( wLatchNow ),//1'b1 ), |
.D( iDestination ), |
.Q(oRAMWriteAddress) |
.Clock( Clock ),//wLatchNow ), |
.Reset( Reset), |
.Enable( wLatchNow ),//1'b1 ), |
.D( iDestination ), |
.Q(oRAMWriteAddress) |
); |
|
//Data forwarding |
133,13 → 132,13
always @(posedge Clock or posedge Reset) |
begin |
|
|
|
|
|
if (Reset) |
CurrentState <= `EXEU_AFTER_RESET; |
CurrentState <= `EXEU_AFTER_RESET; |
else |
CurrentState <= NextState; |
|
CurrentState <= NextState; |
|
end |
//------------------------------------------------ |
|
147,83 → 146,83
always @( * ) |
begin |
case (CurrentState) |
//------------------------------------------ |
`EXEU_AFTER_RESET: |
begin |
//ReadyForNextInstruction = 1; |
oBusy = 0; |
rInputLatchesEnabled = 1; |
|
|
NextState = `EXEU_WAIT_FOR_DECODE; |
end |
//------------------------------------------ |
/** |
At the same time iDecodeDone goes to 1, our Flops |
will store the value, so next clock cycle we can |
tell IDU to go ahead and decode the next instruction |
in the pipeline. |
*/ |
`EXEU_WAIT_FOR_DECODE: |
begin |
|
//------------------------------------------ |
`EXEU_AFTER_RESET: |
begin |
//ReadyForNextInstruction = 1; |
oBusy = 0; |
rInputLatchesEnabled = 1; |
|
|
NextState = `EXEU_WAIT_FOR_DECODE; |
end |
//------------------------------------------ |
/** |
At the same time iDecodeDone goes to 1, our Flops |
will store the value, so next clock cycle we can |
tell IDU to go ahead and decode the next instruction |
in the pipeline. |
*/ |
`EXEU_WAIT_FOR_DECODE: |
begin |
|
|
//ReadyForNextInstruction = 1; |
oBusy = 0; |
rInputLatchesEnabled = 1; |
|
|
if ( iDecodeDone ) //This same thing triggers the ALU |
NextState = `EXEU_WAIT_FOR_ALU_EXECUTION; |
else |
NextState = `EXEU_WAIT_FOR_DECODE; |
end |
//------------------------------------------ |
/* |
If the instruction is aritmetic then pass the parameters |
the ALU, else if it store iOperation then... |
*/ |
`EXEU_WAIT_FOR_ALU_EXECUTION: |
begin |
//ReadyForNextInstruction = 1; |
oBusy = 0; |
rInputLatchesEnabled = 1; |
|
|
if ( iDecodeDone ) //This same thing triggers the ALU |
NextState = `EXEU_WAIT_FOR_ALU_EXECUTION; |
else |
NextState = `EXEU_WAIT_FOR_DECODE; |
end |
//------------------------------------------ |
/* |
If the instruction is aritmetic then pass the parameters |
the ALU, else if it store iOperation then... |
*/ |
`EXEU_WAIT_FOR_ALU_EXECUTION: |
begin |
|
//ReadyForNextInstruction = 0; //* |
oBusy = 1; |
rInputLatchesEnabled = 0; //NO INTERRUPTIONS WHILE WE WAIT!! |
|
//ReadyForNextInstruction = 0; //* |
oBusy = 1; |
rInputLatchesEnabled = 0; //NO INTERRUPTIONS WHILE WE WAIT!! |
|
|
|
if ( iALUOutputReady ) /////This same thing enables writing th results to RAM |
NextState = `EXEU_WAIT_FOR_DECODE; |
else |
NextState = `EXEU_WAIT_FOR_ALU_EXECUTION; |
end |
//------------------------------------------ |
`EXEU_WRITE_BACK_TO_RAM: |
begin |
|
//ReadyForNextInstruction = 0; |
oBusy = 1; |
rInputLatchesEnabled = 1; |
|
if ( iDecodeDone ) |
NextState = `EXEU_WAIT_FOR_ALU_EXECUTION; |
else |
NextState = `EXEU_WAIT_FOR_DECODE; |
|
end |
|
//------------------------------------------ |
default: |
begin |
|
//ReadyForNextInstruction = 1; |
oBusy = 0; |
rInputLatchesEnabled = 1; |
|
if ( iALUOutputReady ) /////This same thing enables writing th results to RAM |
NextState = `EXEU_WAIT_FOR_DECODE; |
else |
NextState = `EXEU_WAIT_FOR_ALU_EXECUTION; |
end |
//------------------------------------------ |
`EXEU_WRITE_BACK_TO_RAM: |
begin |
|
//ReadyForNextInstruction = 0; |
oBusy = 1; |
rInputLatchesEnabled = 1; |
|
if ( iDecodeDone ) |
NextState = `EXEU_WAIT_FOR_ALU_EXECUTION; |
else |
NextState = `EXEU_WAIT_FOR_DECODE; |
|
end |
|
//------------------------------------------ |
default: |
begin |
|
//ReadyForNextInstruction = 1; |
oBusy = 0; |
rInputLatchesEnabled = 1; |
|
NextState = `EXEU_AFTER_RESET; |
end |
//------------------------------------------ |
endcase |
NextState = `EXEU_AFTER_RESET; |
end |
//------------------------------------------ |
endcase |
end |
|
//----------------------------------------------------------------------- |
233,12 → 232,12
initial |
begin |
|
$display("Opening ucode dump file....\n"); |
ucode_file = $fopen("Code.log","w"); |
$fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n"); |
$display("Opening Register lof file...\n"); |
reg_log = $fopen("Registers.log","w"); |
|
$display("Opening ucode dump file....\n"); |
ucode_file = $fopen("Code.log","w"); |
$fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n"); |
$display("Opening Register lof file...\n"); |
reg_log = $fopen("Registers.log","w"); |
|
end |
|
`endif //Ucode dump |
250,156 → 249,156
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource1[95:64] ), |
.Q(wALUChannelX1) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource1[95:64] ), |
.Q(wALUChannelX1) |
); |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource1[63:32] ), |
.Q(wALUChannelY1) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource1[63:32] ), |
.Q(wALUChannelY1) |
); |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource1[31:0] ), |
.Q(wALUChannelZ1) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource1[31:0] ), |
.Q(wALUChannelZ1) |
); |
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource0[95:64] ), |
.Q(wALUChannelX2) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource0[95:64] ), |
.Q(wALUChannelX2) |
); |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource0[63:32] ), |
.Q(wALUChannelY2) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource0[63:32] ), |
.Q(wALUChannelY2) |
); |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource0[31:0] ), |
.Q(wALUChannelZ2) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( wLatchNow ), |
.D( iSource0[31:0] ), |
.Q(wALUChannelZ2) |
); |
|
|
always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE) |
begin |
`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP); |
end |
always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE) |
begin |
`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP); |
end |
|
always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE) |
begin |
if ( iALUOutputReady ) |
begin |
|
|
if (iBranchTaken) |
`LOGME"<BT>"); |
|
if (iBranchNotTaken ) |
`LOGME"<BNT>"); |
|
if (oRAMWriteEnable) |
`LOGME"<WE>"); |
|
`LOGME "(%dns ",$time); |
case ( oALUOperation ) |
`RETURN: `LOGME"RETURN"); |
`ADD: `LOGME"ADD"); |
`SUB: `LOGME"SUB"); |
`DIV: `LOGME"DIV"); |
`MUL: `LOGME"MUL"); |
`MAG: `LOGME"MAG"); |
`JGX: `LOGME"JGX"); |
`JLX: `LOGME"JLX"); |
`JGEX: `LOGME"JGEX"); |
`JGEY: `LOGME"JGEY"); |
`JGEZ: `LOGME"JGEZ"); |
`JLEX: `LOGME"JLEX"); |
`JLEY: `LOGME"JLEY"); |
`JLEZ: `LOGME"JLEZ"); |
`JMP: `LOGME"JMP"); |
`ZERO: `LOGME"ZERO"); |
`JNEX: `LOGME"JNEX"); |
`JNEY: `LOGME"JNEY"); |
`JNEZ: `LOGME"JNEZ"); |
`JEQX: `LOGME"JEQX"); |
`JEQY: `LOGME"JEQY"); |
`JEQZ: `LOGME"JEQZ"); |
`CROSS: `LOGME"CROSS"); |
`DOT: `LOGME"DOT"); |
`SETX: `LOGME"SETX"); |
`SETY: `LOGME"SETY"); |
`SETZ: `LOGME"SETZ"); |
`NOP: `LOGME"NOP"); |
`COPY: `LOGME"COPY"); |
`INC: `LOGME"INC"); |
`DEC: `LOGME"DEC"); |
`MOD: `LOGME"MOD"); |
`FRAC: `LOGME"FRAC"); |
`NEG: `LOGME"NEG"); |
`SWIZZLE3D: `LOGME"SWIZZLE3D"); |
`MULP: `LOGME"MULP"); |
`XCHANGEX: `LOGME"XCHANGEX"); |
`IMUL: `LOGME"IMUL"); |
`UNSCALE: `LOGME"UNSCALE"); |
`INCX: `LOGME"INCX"); |
`INCY: `LOGME"INCY"); |
`INCZ: `LOGME"INCZ"); |
`OMWRITE: `LOGME"OMWRITE"); |
`TMREAD: `LOGME"TMREAD"); |
`LEA: `LOGME"LEA"); |
`CALL: `LOGME"CALL"); |
`RET: `LOGME"RET"); |
`DEBUG_PRINT: |
begin |
`LOGME"DEBUG_PRINT"); |
|
end |
default: |
begin |
`LOGME"**********ERROR UNKNOWN OP*********"); |
$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation); |
// $stop(); |
end |
endcase |
|
`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ", |
oRAMWriteAddress, |
wALUChannelX1,wALUChannelY1,wALUChannelZ1, |
wALUChannelX2,wALUChannelY2,wALUChannelZ2 |
|
); |
|
if (oALUOperation == `RETURN) |
`LOGME"\n\n\n"); |
|
end |
end //always |
|
always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE ) |
begin |
if ( iALUOutputReady ) |
`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ); |
end //always |
always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE) |
begin |
if ( iALUOutputReady ) |
begin |
|
|
if (iBranchTaken) |
`LOGME"<BT>"); |
|
if (iBranchNotTaken ) |
`LOGME"<BNT>"); |
|
if (oRAMWriteEnable) |
`LOGME"<WE>"); |
|
`LOGME "(%dns ",$time); |
case ( oALUOperation ) |
`RETURN: `LOGME"RETURN"); |
`ADD: `LOGME"ADD"); |
`SUB: `LOGME"SUB"); |
`DIV: `LOGME"DIV"); |
`MUL: `LOGME"MUL"); |
`MAG: `LOGME"MAG"); |
`JGX: `LOGME"JGX"); |
`JLX: `LOGME"JLX"); |
`JGEX: `LOGME"JGEX"); |
`JGEY: `LOGME"JGEY"); |
`JGEZ: `LOGME"JGEZ"); |
`JLEX: `LOGME"JLEX"); |
`JLEY: `LOGME"JLEY"); |
`JLEZ: `LOGME"JLEZ"); |
`JMP: `LOGME"JMP"); |
`ZERO: `LOGME"ZERO"); |
`JNEX: `LOGME"JNEX"); |
`JNEY: `LOGME"JNEY"); |
`JNEZ: `LOGME"JNEZ"); |
`JEQX: `LOGME"JEQX"); |
`JEQY: `LOGME"JEQY"); |
`JEQZ: `LOGME"JEQZ"); |
`CROSS: `LOGME"CROSS"); |
`DOT: `LOGME"DOT"); |
`SETX: `LOGME"SETX"); |
`SETY: `LOGME"SETY"); |
`SETZ: `LOGME"SETZ"); |
`NOP: `LOGME"NOP"); |
`COPY: `LOGME"COPY"); |
`INC: `LOGME"INC"); |
`DEC: `LOGME"DEC"); |
`MOD: `LOGME"MOD"); |
`FRAC: `LOGME"FRAC"); |
`NEG: `LOGME"NEG"); |
`SWIZZLE3D: `LOGME"SWIZZLE3D"); |
`MULP: `LOGME"MULP"); |
`XCHANGEX: `LOGME"XCHANGEX"); |
`IMUL: `LOGME"IMUL"); |
`UNSCALE: `LOGME"UNSCALE"); |
`INCX: `LOGME"INCX"); |
`INCY: `LOGME"INCY"); |
`INCZ: `LOGME"INCZ"); |
`OMWRITE: `LOGME"OMWRITE"); |
`TMREAD: `LOGME"TMREAD"); |
`LEA: `LOGME"LEA"); |
`CALL: `LOGME"CALL"); |
`RET: `LOGME"RET"); |
`DEBUG_PRINT: |
begin |
`LOGME"DEBUG_PRINT"); |
|
end |
default: |
begin |
`LOGME"**********ERROR UNKNOWN OP*********"); |
$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation); |
// $stop(); |
end |
endcase |
|
`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ", |
oRAMWriteAddress, |
wALUChannelX1,wALUChannelY1,wALUChannelZ1, |
wALUChannelX2,wALUChannelY2,wALUChannelZ2 |
|
); |
|
if (oALUOperation == `RETURN) |
`LOGME"\n\n\n"); |
|
end |
end //always |
|
always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE ) |
begin |
if ( iALUOutputReady ) |
`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ); |
end //always |
`endif |
|
endmodule |
/Module_FixedPointAddtionSubstraction.v
24,7 → 24,7
input wire Reset, |
input wire[`LONG_WIDTH-1:0] A, |
input wire[`LONG_WIDTH-1:0] B, |
output reg[`LONG_WIDTH-1:0] R, |
output wire [`LONG_WIDTH-1:0] R, |
input wire iOperation, |
input wire iInputReady, //Is the input data valid? |
output wire OutputReady //Our output data is ready! |
49,20 → 49,6
); |
|
|
//------------------------------- |
always @ (posedge Clock) |
begin |
assign R = ( A + wB ); |
|
if (iInputReady == 1) |
begin |
R = ( A + wB ); |
end |
else |
begin |
R = 64'hFFFFFFFF; |
|
end |
|
end // always |
|
endmodule |
/Module_Host.v
38,9 → 38,9
`define MAX_VERTEX_IN_FRAME `WIDTH'd7 // WAS 8'd6 |
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01 |
`define TAG_DATA_ADDRESS_TYPE 2'b10 |
`define SELECT_INST_MEM 3'b00 |
`define SELECT_SCENE_MEM 3'b01 |
`define SELECT_GEO_MEM 3'b10 |
`define SELECT_INST_MEM 2'b00 |
`define SELECT_SCENE_MEM 2'b01 |
`define SELECT_GEO_MEM 2'b10 |
|
|
`define HOST_IDLE 0 |
213,10 → 213,10
reg [63:0] RenderedPixels; |
wire wLastVertexInFrame; |
assign wLastVertexInFrame = |
(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0; |
(wVertexCount % `MAX_VERTEX_IN_FRAME == 32'b0 ) ? 1'b1 : 1'b0; |
|
|
reg [31:0] StartTime; |
reg [63:0] StartTime; |
|
// Host Finite State Machine // |
always @( * ) |
376,7 → 376,6
MST_O = 1; |
rInitialWriteAddress = 0; |
rSetWriteAddr = 0; |
//rCoreBroadCast = 1; |
oCoreSelectMask = `SELECT_ALL_CORES; |
rIncCoreSelect = 0; |
RENDREN_O = 0; |
403,14 → 402,13
rWBMEnable = 0; |
rInitiaReadAddr = 0; |
rWBMReset = 0; |
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory |
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM |
MST_O = 1; //Keep master signal in 1 for now |
rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores |
rSetWriteAddr = 1; //Set to use the initial write address bellow |
//rCoreBroadCast = 0; //Set to zero to unicast, starting from core 0 |
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory |
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM |
MST_O = 1; //Keep master signal in 1 for now |
rInitialWriteAddress = {16'b0,`CREG_PIXEL_2D_INITIAL_POSITION}; //The address from which to start wrting @ the cores |
rSetWriteAddr = 1; //Set to use the initial write address bellow |
oCoreSelectMask = wCoreSelect; |
rIncCoreSelect = 0; //Set to unicast to the next core |
rIncCoreSelect = 0; //Set to unicast to the next core |
RENDREN_O = 0; |
rResetVertexCount = 0; |
GACK_O = 0; |
461,9 → 459,9
oHostDataAvailable = 0; |
|
|
if (wWBMDone && !(oReadAddress % 2)) |
if (wWBMDone && ((oReadAddress % 2) == `WB_WIDTH'b0)) |
rHostNextState = `HOST_UNICAST_CORE_CONFIG; |
else if (wWBMDone && (oReadAddress % 2) ) |
else if (wWBMDone && ((oReadAddress % 2) != `WB_WIDTH'b0)) |
rHostNextState = `HOST_PREPARE_NEXT_CORE_CONFIG; |
else |
rHostNextState = `HOST_WAIT_CORE_CONFIG; |
481,12 → 479,11
rWBMReset = 0; |
oMemSelect = `SELECT_GEO_MEM; |
TGA_O = `TAG_DATA_ADDRESS_TYPE; |
MST_O = 0; //The master signal goes to zero until request |
rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores |
rSetWriteAddr = 1; //Set to use the initial write address bellow |
//rCoreBroadCast = 0; |
MST_O = 0; //The master signal goes to zero until request |
rInitialWriteAddress = {16'b0,`CREG_PIXEL_2D_INITIAL_POSITION}; //Write starting from this location on the cores |
rSetWriteAddr = 1; //Set to use the initial write address bellow |
oCoreSelectMask = wCoreSelect; |
rIncCoreSelect = 1; //Moving to configure the next core now |
rIncCoreSelect = 1; //Moving to configure the next core now |
RENDREN_O = 0; |
rResetVertexCount = 0; |
GACK_O = 0; |
510,9 → 507,8
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading |
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores |
MST_O = 0; //The master signal goes to zero until request |
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores |
rInitialWriteAddress = {16'b0,`CREG_V0}; //Write starting from this location on the cores |
rSetWriteAddr = 1; //Set to use the initial write address bellow |
//rCoreBroadCast = 1; //From now on we only broadcast |
oCoreSelectMask = `SELECT_ALL_CORES; |
rIncCoreSelect = 0; //Ignored during broadcasts |
RENDREN_O = 0; |
535,9 → 531,8
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading |
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores |
MST_O = 0; //The master signal goes to zero until request |
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores |
rInitialWriteAddress = {16'b0,`CREG_V0}; //Write starting from this location on the cores |
rSetWriteAddr = 1; //Set to use the initial write address bellow |
//rCoreBroadCast = 1; //From now on we only broadcast |
oCoreSelectMask = `SELECT_ALL_CORES; |
rIncCoreSelect = 0; //Ignored during broadcasts |
RENDREN_O = 0; |
614,7 → 609,6
MST_O = 1; //Start the Transmition |
rInitialWriteAddress = 0; |
rSetWriteAddr = 0; |
//rCoreBroadCast = 1; |
oCoreSelectMask = `SELECT_ALL_CORES; |
rIncCoreSelect = 0; |
RENDREN_O = `SELECT_ALL_CORES; |
642,9 → 636,8
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading |
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores |
MST_O = 0; //The master signal goes to zero until request |
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores |
rInitialWriteAddress = {16'b0,`CREG_V0}; //Write starting from this location on the cores |
rSetWriteAddr = 1; //Set to use the initial write address bellow |
//rCoreBroadCast = 1; //From now on we only broadcast |
oCoreSelectMask = `SELECT_ALL_CORES; |
rIncCoreSelect = 0; //Ignored during broadcasts |
RENDREN_O = `SELECT_ALL_CORES; |
668,7 → 661,6
MST_O = 1; |
rInitialWriteAddress = 0; |
rSetWriteAddr = 0; |
//rCoreBroadCast = 1; |
oCoreSelectMask = `SELECT_ALL_CORES; |
rIncCoreSelect = 0; |
RENDREN_O = `SELECT_ALL_CORES; |
707,7 → 699,7
//---------------------------------------- |
`HOST_GPU_EXECUTION_DONE: |
begin |
$display("THEIA Execution done in %dns\n",$time-StartTime); |
$display("THEIA Execution done in %xns\n",$time-StartTime); |
rWBMEnable = 0; |
rInitiaReadAddr = 0; |
rWBMReset = 0; |
716,7 → 708,6
MST_O = 0; |
rInitialWriteAddress = 0; |
rSetWriteAddr = 0; |
//rCoreBroadCast = 0; |
oCoreSelectMask = wCoreSelect; |
rIncCoreSelect = 0; |
RENDREN_O = 0; |
738,7 → 729,6
MST_O = 0; |
rInitialWriteAddress = 0; |
rSetWriteAddr = 0; |
//rCoreBroadCast = 0; |
oCoreSelectMask = wCoreSelect; |
rIncCoreSelect = 0; |
RENDREN_O = 0; |
/Module_InstructionEntryPoint.v
17,8 → 17,8
assign oInstructionAddr = (oTriggerIFU) ? oEntryPoint : iInitialCodeAddress; |
assign oEPU_Busy = iTrigger | oTriggerIFU; |
|
/* |
|
|
FFD_POSEDGE_ASYNC_RESET # ( 1 ) FFD1 |
( |
.Clock(Clock), |
26,6 → 26,15
.D(iTrigger), |
.Q(oTriggerIFU) |
); |
*/ |
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1), |
.D(iTrigger), |
.Q(oTriggerIFU) |
); |
|
assign oEntryPoint = (oTriggerIFU) ? iIMemInput[`ROM_ADDRESS_WIDTH-1:0] : `ROM_ADDRESS_WIDTH'b0; |
|
/Module_VectorALU.v
32,36 → 32,35
//-------------------------------------------------------------- |
module VectorALU |
( |
input wire Clock, |
input wire Reset, |
input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation, |
input wire[`WIDTH-1:0] iChannel_Ax, |
input wire[`WIDTH-1:0] iChannel_Bx, |
input wire[`WIDTH-1:0] iChannel_Ay, |
input wire[`WIDTH-1:0] iChannel_By, |
input wire[`WIDTH-1:0] iChannel_Az, |
input wire[`WIDTH-1:0] iChannel_Bz, |
output wire [`WIDTH-1:0] oResultA, |
output wire [`WIDTH-1:0] oResultB, |
output wire [`WIDTH-1:0] oResultC, |
input wire iInputReady, |
output reg oBranchTaken, |
output reg oBranchNotTaken, |
output reg oReturnFromSub, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iCurrentIP, |
|
//Connections to the O Memory |
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress, |
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData, |
output wire oOMEM_WriteEnable, |
//Connections to the R Memory |
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress, |
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData, |
input wire iTMEMDataAvailable, |
output wire oTMEMDataRequest, |
|
output reg OutputReady |
|
input wire Clock, |
input wire Reset, |
input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation, |
input wire[`WIDTH-1:0] iChannel_Ax, |
input wire[`WIDTH-1:0] iChannel_Bx, |
input wire[`WIDTH-1:0] iChannel_Ay, |
input wire[`WIDTH-1:0] iChannel_By, |
input wire[`WIDTH-1:0] iChannel_Az, |
input wire[`WIDTH-1:0] iChannel_Bz, |
output wire [`WIDTH-1:0] oResultA, |
output wire [`WIDTH-1:0] oResultB, |
output wire [`WIDTH-1:0] oResultC, |
input wire iInputReady, |
output reg oBranchTaken, |
output reg oBranchNotTaken, |
output reg oReturnFromSub, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iCurrentIP, |
|
//Connections to the O Memory |
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress, |
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData, |
output wire oOMEM_WriteEnable, |
//Connections to the R Memory |
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress, |
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData, |
input wire iTMEMDataAvailable, |
output wire oTMEMDataRequest, |
output reg OutputReady |
|
); |
|
|
73,13 → 72,13
|
//-------------------------------------------------------------- |
|
reg [7:0] InputReadyA,InputReadyB,InputReadyC; |
reg [7:0] InputReadyA,InputReadyB,InputReadyC; |
|
//------------------------------------------------------ |
/* |
This is the block that takes care of all tha arithmetic |
comparisons. Supported operations are <,>,<=,>=,==,!= |
|
This is the block that takes care of all tha arithmetic |
comparisons. Supported operations are <,>,<=,>=,==,!= |
|
*/ |
//------------------------------------------------------ |
reg [`WIDTH-1:0] wMultiplicationA_Ax; |
104,23 → 103,23
|
FFD32_POSEDGE ResultAFFD |
( |
.Clock( OutputReady ), |
.D( ResultA ), |
.Q( oResultA ) |
.Clock( OutputReady ), |
.D( ResultA ), |
.Q( oResultA ) |
); |
|
FFD32_POSEDGE ResultBFFD |
( |
.Clock( OutputReady ), |
.D( ResultB ), |
.Q( oResultB ) |
.Clock( OutputReady ), |
.D( ResultB ), |
.Q( oResultB ) |
); |
|
FFD32_POSEDGE ResultCFFD |
( |
.Clock( OutputReady ), |
.D( ResultC ), |
.Q( oResultC ) |
.Clock( OutputReady ), |
.D( ResultC ), |
.Q( oResultC ) |
); |
//-------------------------------------------------------------------- |
|
128,14 → 127,14
|
Swizzle3D Swizzle1 |
( |
.Source0_X( iChannel_Bx ), |
.Source0_Y( iChannel_By ), |
.Source0_Z( iChannel_Bz ), |
.iOperation( iChannel_Ax ), |
|
.SwizzleX( wSwizzleOutputX ), |
.SwizzleY( wSwizzleOutputY ), |
.SwizzleZ( wSwizzleOutputZ ) |
.Source0_X( iChannel_Bx ), |
.Source0_Y( iChannel_By ), |
.Source0_Z( iChannel_Bz ), |
.iOperation( iChannel_Ax ), |
|
.SwizzleX( wSwizzleOutputX ), |
.SwizzleY( wSwizzleOutputY ), |
.SwizzleZ( wSwizzleOutputZ ) |
); |
//--------------------------------------------------------------------- |
wire [`LONG_WIDTH-1:0] wModulus2N_ResultA,wModulus2N_ResultB,wModulus2N_ResultC; |
147,20 → 146,20
|
always @ ( * ) |
begin |
if (iOperation == `RET) |
oReturnFromSub = OutputReady; |
else |
oReturnFromSub = 1'b0; |
if (iOperation == `RET) |
oReturnFromSub = OutputReady; |
else |
oReturnFromSub = 1'b0; |
|
end |
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_AWE |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( 1'b1 ), |
.D( IOW_Operation ), |
.Q( wOMEM_We ) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( 1'b1 ), |
.D( IOW_Operation ), |
.Q( wOMEM_We ) |
); |
|
assign oOMEM_WriteEnable = wOMEM_We & IOW_Operation; |
167,19 → 166,19
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD1_A |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( iInputReady ), |
.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ), |
.Q( oOMEMWriteAddress) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( iInputReady ), |
.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ), |
.Q( oOMEMWriteAddress) |
); |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( iInputReady ), |
.D( {iChannel_Bx,iChannel_By,iChannel_Bz} ), |
.Q( oOMEMWriteData ) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( iInputReady ), |
.D( {iChannel_Bx,iChannel_By,iChannel_Bz} ), |
.Q( oOMEMWriteData ) |
); |
|
|
189,11 → 188,11
/* |
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( 1'b1 ), |
.D( iTMEMDataAvailable ), |
.Q( wTMReadOutputReady ) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( 1'b1 ), |
.D( iTMEMDataAvailable ), |
.Q( wTMReadOutputReady ) |
); |
*/ |
//assign oTMEMReadAddress = {iChannel_Ax,iChannel_Ay,iChannel_Az}; |
206,59 → 205,59
wire wTMEMRequest; |
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE123 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( 1'b1 ), |
.D( wOpTRead ), |
.Q( wTMEMRequest ) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( 1'b1 ), |
.D( wOpTRead ), |
.Q( wTMEMRequest ) |
); |
assign oTMEMDataRequest = wTMEMRequest & wOpTRead; |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B445 |
( |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( iInputReady & wOpTRead ), |
.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ), |
.Q( oTMEMReadAddress ) |
.Clock( Clock ), |
.Reset( Reset), |
.Enable( iInputReady & wOpTRead ), |
.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ), |
.Q( oTMEMReadAddress ) |
); |
|
/* |
This MUX will select the apropiated X,Y or Z depending on |
wheter it is XYZ iOperation. This gets defined by the bits 3 and 4 |
of iOperation, and only applies for oBranchTaken and Store operations. |
This MUX will select the apropiated X,Y or Z depending on |
wheter it is XYZ iOperation. This gets defined by the bits 3 and 4 |
of iOperation, and only applies for oBranchTaken and Store operations. |
*/ |
|
wire wArithmeticComparison_Result; |
wire ArithmeticComparison_InputReady; |
wire ArithmeticComparison_OutputReady; |
reg[`WIDTH-1:0] ArithmeticComparison_A,ArithmeticComparison_B; |
wire wArithmeticComparison_Result; |
wire ArithmeticComparison_InputReady; |
wire ArithmeticComparison_OutputReady; |
reg[`WIDTH-1:0] ArithmeticComparison_A,ArithmeticComparison_B; |
|
|
always @ ( * ) |
begin |
case ( {iOperation[4],iOperation[3]} ) |
2'b01: ArithmeticComparison_A = iChannel_Ax; |
2'b10: ArithmeticComparison_A = iChannel_Ay; |
2'b11: ArithmeticComparison_A = iChannel_Az; |
default: ArithmeticComparison_A = 0; //Should never happen |
endcase |
case ( {iOperation[4],iOperation[3]} ) |
2'b01: ArithmeticComparison_A = iChannel_Ax; |
2'b10: ArithmeticComparison_A = iChannel_Ay; |
2'b11: ArithmeticComparison_A = iChannel_Az; |
default: ArithmeticComparison_A = 0; //Should never happen |
endcase |
end |
//--------------------------------------------------------------------- |
always @ ( * ) |
begin |
case ( {iOperation[4],iOperation[3]} ) |
2'b01: ArithmeticComparison_B = iChannel_Bx; |
2'b10: ArithmeticComparison_B = iChannel_By; |
2'b11: ArithmeticComparison_B = iChannel_Bz; |
default: ArithmeticComparison_B = 0; //Should never happen |
endcase |
case ( {iOperation[4],iOperation[3]} ) |
2'b01: ArithmeticComparison_B = iChannel_Bx; |
2'b10: ArithmeticComparison_B = iChannel_By; |
2'b11: ArithmeticComparison_B = iChannel_Bz; |
default: ArithmeticComparison_B = 0; //Should never happen |
endcase |
end |
|
//--------------------------------------------------------------------- |
/* |
The onbly instance of Aritmetic comparison in the ALU, |
ArithmeticComparison operations matches the 3 LSB of |
Global ALU iOperation for oBranchTaken Instruction family |
The onbly instance of Aritmetic comparison in the ALU, |
ArithmeticComparison operations matches the 3 LSB of |
Global ALU iOperation for oBranchTaken Instruction family |
*/ |
|
assign ArithmeticComparison_InputReady = iInputReady; |
267,13 → 266,13
|
ArithmeticComparison ArithmeticComparison_1 |
( |
.Clock( Clock ), |
.X( ArithmeticComparison_A ), |
.Y( ArithmeticComparison_B ), |
.iOperation( iOperation[2:0] ), |
.iInputReady( ArithmeticComparison_InputReady ), |
.OutputReady( ArithmeticComparison_OutputReady ), |
.Result( wArithmeticComparisonResult ) |
.Clock( Clock ), |
.X( ArithmeticComparison_A ), |
.Y( ArithmeticComparison_B ), |
.iOperation( iOperation[2:0] ), |
.iInputReady( ArithmeticComparison_InputReady ), |
.OutputReady( ArithmeticComparison_OutputReady ), |
.Result( wArithmeticComparisonResult ) |
); |
|
|
282,25 → 281,25
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_A |
( |
|
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationA_Ax ), |
.B( wMultiplicationA_Bx ), |
.R( wMultiplicationA_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationA_InputReady ), |
.OutputReady( wMultiplicationA_OutputReady ) |
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationA_Ax ), |
.B( wMultiplicationA_Bx ), |
.R( wMultiplicationA_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationA_InputReady ), |
.OutputReady( wMultiplicationA_OutputReady ) |
); |
|
//-------------------------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationA_Ax = iChannel_Ay; // Ay * Bz |
`MAG: wMultiplicationA_Ax = iChannel_Ax; |
`MULP: wMultiplicationA_Ax = iChannel_Ax; //Az = Ax * Ay |
default: wMultiplicationA_Ax = iChannel_Ax; // Ax * Bx |
endcase |
case (iOperation) |
`CROSS: wMultiplicationA_Ax = iChannel_Ay; // Ay * Bz |
`MAG: wMultiplicationA_Ax = iChannel_Ax; |
`MULP: wMultiplicationA_Ax = iChannel_Ax; //Az = Ax * Ay |
default: wMultiplicationA_Ax = iChannel_Ax; // Ax * Bx |
endcase |
end |
//-------------------------------------------------------------------- |
|
307,25 → 306,25
//assign wMultiplicationA_Ax = iChannel_Ax; |
|
assign wMultiplicationA_InputReady |
= (iOperation == `CROSS || |
iOperation == `DOT || |
iOperation == `MUL || |
iOperation == `IMUL || |
iOperation == `MAG || |
iOperation == `MULP |
) ? iInputReady : 0; |
|
= (iOperation == `CROSS || |
iOperation == `DOT || |
iOperation == `MUL || |
iOperation == `IMUL || |
iOperation == `MAG || |
iOperation == `MULP |
) ? iInputReady : 0; |
|
//-------------------------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`MUL,`IMUL: wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx |
`MAG: wMultiplicationA_Bx = iChannel_Ax; //Ax^2 |
`DOT: wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx |
`CROSS: wMultiplicationA_Bx = iChannel_Bz; // Ay * Bz |
`MULP: wMultiplicationA_Bx = iChannel_Ay; //Az = Ax * Ay |
default: wMultiplicationA_Bx = 32'b0; |
endcase |
case (iOperation) |
`MUL,`IMUL: wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx |
`MAG: wMultiplicationA_Bx = iChannel_Ax; //Ax^2 |
`DOT: wMultiplicationA_Bx = iChannel_Bx; //Ax*Bx |
`CROSS: wMultiplicationA_Bx = iChannel_Bz; // Ay * Bz |
`MULP: wMultiplicationA_Bx = iChannel_Ay; //Az = Ax * Ay |
default: wMultiplicationA_Bx = 32'b0; |
endcase |
end |
//-------------------------------------------------------------------- |
|
341,14 → 340,14
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_B |
( |
|
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationB_Ay ), |
.B( wMultiplicationB_By ), |
.R( wMultiplicationB_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationB_InputReady ), |
.OutputReady( wMultiplicationB_OutputReady ) |
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationB_Ay ), |
.B( wMultiplicationB_By ), |
.R( wMultiplicationB_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationB_InputReady ), |
.OutputReady( wMultiplicationB_OutputReady ) |
); |
|
|
356,33 → 355,33
|
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationB_Ay = iChannel_Az; // Az * By |
`MAG: wMultiplicationB_Ay = iChannel_Ay; |
default: wMultiplicationB_Ay = iChannel_Ay; // Ay * By |
endcase |
case (iOperation) |
`CROSS: wMultiplicationB_Ay = iChannel_Az; // Az * By |
`MAG: wMultiplicationB_Ay = iChannel_Ay; |
default: wMultiplicationB_Ay = iChannel_Ay; // Ay * By |
endcase |
end |
//---------------------------------------------------- |
assign wMultiplicationB_InputReady |
= (iOperation == `CROSS || |
iOperation == `DOT || |
iOperation == `MUL || |
iOperation == `IMUL || |
iOperation == `MAG ) ? iInputReady : 0; |
|
= (iOperation == `CROSS || |
iOperation == `DOT || |
iOperation == `MUL || |
iOperation == `IMUL || |
iOperation == `MAG ) ? iInputReady : 0; |
|
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`MUL,`IMUL: wMultiplicationB_By = iChannel_By; //Ay*By |
`MAG: wMultiplicationB_By = iChannel_Ay; //Ay^2 |
`DOT: wMultiplicationB_By = iChannel_By; //Ay*By |
`CROSS: wMultiplicationB_By = iChannel_By; // Az * By |
default: wMultiplicationB_By = 32'b0; |
endcase |
case (iOperation) |
`MUL,`IMUL: wMultiplicationB_By = iChannel_By; //Ay*By |
`MAG: wMultiplicationB_By = iChannel_Ay; //Ay^2 |
`DOT: wMultiplicationB_By = iChannel_By; //Ay*By |
`CROSS: wMultiplicationB_By = iChannel_By; // Az * By |
default: wMultiplicationB_By = 32'b0; |
endcase |
end |
//---------------------------------------------------- |
|
|
//------------------------------------------------------ |
reg [`WIDTH-1:0] wMultiplicationC_Az; |
reg [`WIDTH-1:0] wMultiplicationC_Bz; |
394,14 → 393,14
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_C |
( |
|
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationC_Az ), |
.B( wMultiplicationC_Bz ), |
.R( wMultiplicationC_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationC_InputReady ), |
.OutputReady( wMultiplicationC_OutputReady ) |
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationC_Az ), |
.B( wMultiplicationC_Bz ), |
.R( wMultiplicationC_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationC_InputReady ), |
.OutputReady( wMultiplicationC_OutputReady ) |
); |
|
|
408,35 → 407,35
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationC_Az = iChannel_Az; //Az*Bx |
`MAG: wMultiplicationC_Az = iChannel_Az; |
default: wMultiplicationC_Az = iChannel_Az; //Az*Bz |
endcase |
case (iOperation) |
`CROSS: wMultiplicationC_Az = iChannel_Az; //Az*Bx |
`MAG: wMultiplicationC_Az = iChannel_Az; |
default: wMultiplicationC_Az = iChannel_Az; //Az*Bz |
endcase |
end |
//---------------------------------------------------- |
|
assign wMultiplicationC_InputReady |
= ( |
iOperation == `CROSS || |
iOperation == `DOT || |
iOperation == `MUL || |
iOperation == `IMUL || |
iOperation == `MAG |
) ? iInputReady : 0; |
|
= ( |
iOperation == `CROSS || |
iOperation == `DOT || |
iOperation == `MUL || |
iOperation == `IMUL || |
iOperation == `MAG |
) ? iInputReady : 0; |
|
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`MUL,`IMUL: wMultiplicationC_Bz = iChannel_Bz; //Az*Bz |
`MAG: wMultiplicationC_Bz = iChannel_Az; //Ay^2 |
`DOT: wMultiplicationC_Bz = iChannel_Bz; //Az*Bz |
`CROSS: wMultiplicationC_Bz = iChannel_Bx; //Az*Bx |
default: wMultiplicationC_Bz = 32'b0; |
endcase |
case (iOperation) |
`MUL,`IMUL: wMultiplicationC_Bz = iChannel_Bz; //Az*Bz |
`MAG: wMultiplicationC_Bz = iChannel_Az; //Ay^2 |
`DOT: wMultiplicationC_Bz = iChannel_Bz; //Az*Bz |
`CROSS: wMultiplicationC_Bz = iChannel_Bx; //Az*Bx |
default: wMultiplicationC_Bz = 32'b0; |
endcase |
end |
//---------------------------------------------------- |
//---------------------------------------------------- |
|
reg [`WIDTH-1:0] wMultiplicationD_Aw; |
reg [`WIDTH-1:0] wMultiplicationD_Bw; |
448,37 → 447,37
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_D |
( |
|
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationD_Aw ), |
.B( wMultiplicationD_Bw ), |
.R( wMultiplicationD_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationD_InputReady ), |
.OutputReady( wMultiplicationD_OutputReady ) |
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationD_Aw ), |
.B( wMultiplicationD_Bw ), |
.R( wMultiplicationD_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationD_InputReady ), |
.OutputReady( wMultiplicationD_OutputReady ) |
); |
|
assign wMultiplicationD_InputReady |
= (iOperation == `CROSS ) ? iInputReady : 0; |
= (iOperation == `CROSS ) ? iInputReady : 0; |
|
|
//---------------------------------------------------- |
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationD_Aw = iChannel_Ax; //Ax*Bz |
default: wMultiplicationD_Aw = 32'b0; |
endcase |
case (iOperation) |
`CROSS: wMultiplicationD_Aw = iChannel_Ax; //Ax*Bz |
default: wMultiplicationD_Aw = 32'b0; |
endcase |
end |
//---------------------------------------------------- |
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationD_Bw = iChannel_Bz; //Ax*Bz |
default: wMultiplicationD_Bw = 32'b0; |
endcase |
case (iOperation) |
`CROSS: wMultiplicationD_Bw = iChannel_Bz; //Ax*Bz |
default: wMultiplicationD_Bw = 32'b0; |
endcase |
end |
//---------------------------------------------------- |
//---------------------------------------------------- |
reg [`WIDTH-1:0] wMultiplicationE_Ak; |
reg [`WIDTH-1:0] wMultiplicationE_Bk; |
wire [`LONG_WIDTH-1:0] wMultiplicationE_Result; |
489,38 → 488,38
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_E |
( |
|
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationE_Ak ), |
.B( wMultiplicationE_Bk ), |
.R( wMultiplicationE_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationE_InputReady ), |
.OutputReady( wMultiplicationE_OutputReady ) |
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationE_Ak ), |
.B( wMultiplicationE_Bk ), |
.R( wMultiplicationE_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationE_InputReady ), |
.OutputReady( wMultiplicationE_OutputReady ) |
); |
|
assign wMultiplicationE_InputReady |
= (iOperation == `CROSS ) ? iInputReady : 0; |
|
|
//---------------------------------------------------- |
= (iOperation == `CROSS ) ? iInputReady : 0; |
|
|
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationE_Ak = iChannel_Ax; //Ax*By |
default: wMultiplicationE_Ak = 32'b0; |
endcase |
case (iOperation) |
`CROSS: wMultiplicationE_Ak = iChannel_Ax; //Ax*By |
default: wMultiplicationE_Ak = 32'b0; |
endcase |
end |
//---------------------------------------------------- |
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationE_Bk = iChannel_By; //Ax*By |
default: wMultiplicationE_Bk = 32'b0; |
endcase |
end |
|
//---------------------------------------------------- |
case (iOperation) |
`CROSS: wMultiplicationE_Bk = iChannel_By; //Ax*By |
default: wMultiplicationE_Bk = 32'b0; |
endcase |
end |
|
//---------------------------------------------------- |
reg [`WIDTH-1:0] wMultiplicationF_Al; |
reg [`WIDTH-1:0] wMultiplicationF_Bl; |
wire [`LONG_WIDTH-1:0] wMultiplicationF_Result; |
531,35 → 530,35
RADIX_R_MUL_32_FULL_PARALLEL MultiplicationChannel_F |
( |
|
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationF_Al ), |
.B( wMultiplicationF_Bl ), |
.R( wMultiplicationF_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationF_InputReady ), |
.OutputReady( wMultiplicationF_OutputReady ) |
.Clock( Clock ), |
.Reset( Reset ), |
.A( wMultiplicationF_Al ), |
.B( wMultiplicationF_Bl ), |
.R( wMultiplicationF_Result ), |
.iUnscaled( wMultiplcationUnscaled ), |
.iInputReady( wMultiplicationF_InputReady ), |
.OutputReady( wMultiplicationF_OutputReady ) |
); |
assign wMultiplicationF_InputReady |
= (iOperation == `CROSS ) ? iInputReady : 0; |
|
|
//---------------------------------------------------- |
= (iOperation == `CROSS ) ? iInputReady : 0; |
|
|
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationF_Al = iChannel_Ay; //Ay*Bx |
default: wMultiplicationF_Al = 32'b0; |
endcase |
case (iOperation) |
`CROSS: wMultiplicationF_Al = iChannel_Ay; //Ay*Bx |
default: wMultiplicationF_Al = 32'b0; |
endcase |
end |
//---------------------------------------------------- |
//---------------------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wMultiplicationF_Bl = iChannel_Bx; //Ay*Bx |
default: wMultiplicationF_Bl = 32'b0; |
endcase |
end |
case (iOperation) |
`CROSS: wMultiplicationF_Bl = iChannel_Bx; //Ay*Bx |
default: wMultiplicationF_Bl = 32'b0; |
endcase |
end |
//------------------------------------------------------ |
wire [`WIDTH-1:0] wDivisionA_Result; |
wire wDivisionA_OutputReady; |
566,7 → 565,7
wire wDivisionA_InputReady; |
|
assign wDivisionA_InputReady = |
( iOperation == `DIV) ? iInputReady : 0; |
( iOperation == `DIV) ? iInputReady : 0; |
|
SignedIntegerDivision DivisionChannel_A |
( |
573,7 → 572,7
.Clock( Clock ), |
.Reset( Reset ), |
.iDividend( iChannel_Ax ), |
.iDivisor( iChannel_Bx ), |
.iDivisor( iChannel_Bx ), |
.oQuotient( wDivisionA_Result[`WIDTH-1:0] ), |
.iInputReady( wDivisionA_InputReady ), |
.OutputReady( wDivisionA_OutputReady ) |
585,7 → 584,7
wire wDivisionB_InputReady; |
|
assign wDivisionB_InputReady = |
( iOperation == `DIV) ? iInputReady : 0; |
( iOperation == `DIV) ? iInputReady : 0; |
|
SignedIntegerDivision DivisionChannel_B |
( |
605,7 → 604,7
|
|
assign wDivisionC_InputReady = |
( iOperation == `DIV) ? iInputReady : 0; |
( iOperation == `DIV) ? iInputReady : 0; |
|
SignedIntegerDivision DivisionChannel_C |
( |
620,9 → 619,9
); |
//-------------------------------------------------------------- |
/* |
First addtion block instance goes here. |
Note that all inputs/outputs to the block |
are wires. It has two MUXES one for each entry. |
First addtion block instance goes here. |
Note that all inputs/outputs to the block |
are wires. It has two MUXES one for each entry. |
*/ |
reg [`LONG_WIDTH-1:0] wAddSubA_Ax,wAddSubA_Bx; |
wire [`LONG_WIDTH-1:0] wAddSubA_Result; |
631,12 → 630,12
wire wAddSubA_OutputReady; |
|
assign wAddSubA_Operation |
= ( |
iOperation == `SUB |
|| iOperation == `CROSS |
|| iOperation == `DEC |
|| iOperation == `MOD |
) ? 1 : 0; |
= ( |
iOperation == `SUB |
|| iOperation == `CROSS |
|| iOperation == `DEC |
|| iOperation == `MOD |
) ? 1 : 0; |
|
FixedAddSub AddSubChannel_A |
( |
646,8 → 645,8
.B( wAddSubA_Bx ), |
.R( wAddSubA_Result ), |
.iOperation( wAddSubA_Operation ), |
.iInputReady( wAddSubA_InputReady ), |
.OutputReady( wAddSubA_OutputReady ) |
.iInputReady( wAddSubA_InputReady ), |
.OutputReady( wAddSubA_OutputReady ) |
); |
//Diego |
|
657,32 → 656,32
//InpuReady Mux A |
always @ ( * ) |
begin |
case (iOperation) |
`ADD: wAddSubA_InputReady = iInputReady; |
`SUB: wAddSubA_InputReady = iInputReady; |
`INC,`INCX,`INCY,`INCZ: wAddSubA_InputReady = iInputReady; |
`DEC: wAddSubA_InputReady = iInputReady; |
`MOD: wAddSubA_InputReady = iInputReady; |
|
`MAG: wAddSubA_InputReady = wMultiplicationOutputReadyA && |
wMultiplicationOutputReadyB; |
//wMultiplicationA_OutputReady |
//&& wMultiplicationB_OutputReady; |
|
`DOT: wAddSubA_InputReady = |
wMultiplicationOutputReadyA && |
wMultiplicationOutputReadyB; |
//wMultiplicationA_OutputReady |
//&& wMultiplicationB_OutputReady; |
|
`CROSS: wAddSubA_InputReady = |
wMultiplicationOutputReadyA && |
wMultiplicationOutputReadyB; |
// wMultiplicationA_OutputReady |
//&& wMultiplicationB_OutputReady; |
|
default: wAddSubA_InputReady = 1'b0; |
endcase |
case (iOperation) |
`ADD: wAddSubA_InputReady = iInputReady; |
`SUB: wAddSubA_InputReady = iInputReady; |
`INC,`INCX,`INCY,`INCZ: wAddSubA_InputReady = iInputReady; |
`DEC: wAddSubA_InputReady = iInputReady; |
`MOD: wAddSubA_InputReady = iInputReady; |
|
`MAG: wAddSubA_InputReady = wMultiplicationOutputReadyA && |
wMultiplicationOutputReadyB; |
//wMultiplicationA_OutputReady |
//&& wMultiplicationB_OutputReady; |
|
`DOT: wAddSubA_InputReady = |
wMultiplicationOutputReadyA && |
wMultiplicationOutputReadyB; |
//wMultiplicationA_OutputReady |
//&& wMultiplicationB_OutputReady; |
|
`CROSS: wAddSubA_InputReady = |
wMultiplicationOutputReadyA && |
wMultiplicationOutputReadyB; |
// wMultiplicationA_OutputReady |
//&& wMultiplicationB_OutputReady; |
|
default: wAddSubA_InputReady = 1'b0; |
endcase |
end |
//---------------------------- |
|
689,43 → 688,43
//wAddSubA_Bx 2:1 input Mux |
always @ ( * ) |
begin |
case (iOperation) |
|
`ADD: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`SUB: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`INC,`INCX,`INCY,`INCZ: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`DEC: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`MOD: wAddSubA_Ax = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx }; |
|
`MAG: wAddSubA_Ax = wMultiplicationA_Result; |
`DOT: wAddSubA_Ax = wMultiplicationA_Result; |
`CROSS: wAddSubA_Ax = wMultiplicationA_Result; |
default: wAddSubA_Ax = 64'b0; |
endcase |
case (iOperation) |
|
`ADD: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`SUB: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`INC,`INCX,`INCY,`INCZ: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`DEC: wAddSubA_Ax = ( iChannel_Ax[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ax } : { 32'b0, iChannel_Ax }; |
`MOD: wAddSubA_Ax = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx }; |
|
`MAG: wAddSubA_Ax = wMultiplicationA_Result; |
`DOT: wAddSubA_Ax = wMultiplicationA_Result; |
`CROSS: wAddSubA_Ax = wMultiplicationA_Result; |
default: wAddSubA_Ax = 64'b0; |
endcase |
end |
//---------------------------- |
//wAddSubA_Bx 2:1 input Mux |
always @ ( * ) |
begin |
case (iOperation) |
`ADD: wAddSubA_Bx = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx }; |
`SUB: wAddSubA_Bx = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx }; |
`INC,`INCX: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE); |
`INCY,`INCZ: wAddSubA_Bx = `LONG_WIDTH'd0; |
`DEC: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE); |
`MOD: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE); |
|
`MAG: wAddSubA_Bx = wMultiplicationB_Result; |
`DOT: wAddSubA_Bx = wMultiplicationB_Result; |
`CROSS: wAddSubA_Bx = wMultiplicationB_Result; |
default: wAddSubA_Bx = 64'b0; |
endcase |
case (iOperation) |
`ADD: wAddSubA_Bx = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx }; |
`SUB: wAddSubA_Bx = ( iChannel_Bx[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Bx } : { 32'b0, iChannel_Bx }; |
`INC,`INCX: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE); |
`INCY,`INCZ: wAddSubA_Bx = `LONG_WIDTH'd0; |
`DEC: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE); |
`MOD: wAddSubA_Bx = (`LONG_WIDTH'd1 << `SCALE); |
|
`MAG: wAddSubA_Bx = wMultiplicationB_Result; |
`DOT: wAddSubA_Bx = wMultiplicationB_Result; |
`CROSS: wAddSubA_Bx = wMultiplicationB_Result; |
default: wAddSubA_Bx = 64'b0; |
endcase |
end |
//-------------------------------------------------------------- |
/* |
Second addtion block instance goes here. |
Note that all inputs/outputs to the block |
are wires. It has two MUXES one for each entry. |
Second addtion block instance goes here. |
Note that all inputs/outputs to the block |
are wires. It has two MUXES one for each entry. |
*/ |
|
wire [`LONG_WIDTH-1:0] wAddSubB_Result; |
738,11 → 737,11
reg [`LONG_WIDTH-1:0] wAddSubB_Ay,wAddSubB_By; |
|
assign wAddSubB_Operation = |
( iOperation == `SUB |
|| iOperation == `CROSS |
|| iOperation == `DEC |
|| iOperation == `MOD |
) ? 1 : 0; |
( iOperation == `SUB |
|| iOperation == `CROSS |
|| iOperation == `DEC |
|| iOperation == `MOD |
) ? 1 : 0; |
|
FixedAddSub AddSubChannel_B |
( |
752,19 → 751,19
.B( wAddSubB_By ), |
.R( wAddSubB_Result ), |
.iOperation( wAddSubB_Operation ), |
.iInputReady( wAddSubB_InputReady ), |
.OutputReady( wAddSubB_OutputReady ) |
.iInputReady( wAddSubB_InputReady ), |
.OutputReady( wAddSubB_OutputReady ) |
); |
//---------------------------- |
wire wMultiplicationOutputReadyC_Dealy1; |
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFwMultiplicationOutputReadyC_Dealy1 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1 ), |
.D( wMultiplicationOutputReadyC ), |
.Q( wMultiplicationOutputReadyC_Dealy1 ) |
); |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1 ), |
.D( wMultiplicationOutputReadyC ), |
.Q( wMultiplicationOutputReadyC_Dealy1 ) |
); |
|
|
|
773,29 → 772,29
//InpuReady Mux B |
always @ ( * ) |
begin |
case (iOperation) |
`ADD: wAddSubB_InputReady = iInputReady; |
`SUB: wAddSubB_InputReady = iInputReady; |
`INC,`INCX,`INCY,`INCZ: wAddSubB_InputReady = iInputReady; |
`DEC: wAddSubB_InputReady = iInputReady; |
`MOD: wAddSubB_InputReady = iInputReady; |
|
`MAG: wAddSubB_InputReady = wAddSubAOutputReady |
&& wMultiplicationOutputReadyC_Dealy1; |
//&& wMultiplicationC_OutputReady; |
|
`DOT: wAddSubB_InputReady = wAddSubAOutputReady |
&& wMultiplicationOutputReadyC_Dealy1; |
//&& wMultiplicationC_OutputReady; |
|
`CROSS: wAddSubB_InputReady = wMultiplicationOutputReadyC && |
wMultiplicationOutputReadyD; |
// wMultiplicationC_OutputReady |
//&& wMultiplicationD_OutputReady; |
|
default: wAddSubB_InputReady = 1'b0; |
|
endcase |
case (iOperation) |
`ADD: wAddSubB_InputReady = iInputReady; |
`SUB: wAddSubB_InputReady = iInputReady; |
`INC,`INCX,`INCY,`INCZ: wAddSubB_InputReady = iInputReady; |
`DEC: wAddSubB_InputReady = iInputReady; |
`MOD: wAddSubB_InputReady = iInputReady; |
|
`MAG: wAddSubB_InputReady = wAddSubAOutputReady |
&& wMultiplicationOutputReadyC_Dealy1; |
//&& wMultiplicationC_OutputReady; |
|
`DOT: wAddSubB_InputReady = wAddSubAOutputReady |
&& wMultiplicationOutputReadyC_Dealy1; |
//&& wMultiplicationC_OutputReady; |
|
`CROSS: wAddSubB_InputReady = wMultiplicationOutputReadyC && |
wMultiplicationOutputReadyD; |
// wMultiplicationC_OutputReady |
//&& wMultiplicationD_OutputReady; |
|
default: wAddSubB_InputReady = 1'b0; |
|
endcase |
end |
//---------------------------- |
// wAddSubB_Ay 2:1 input Mux |
804,34 → 803,34
// previus ADDER_A, same for dot product. |
always @ ( * ) |
begin |
case (iOperation) |
`ADD: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`SUB: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`INC,`INCX,`INCY,`INCZ: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`DEC: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`MOD: wAddSubB_Ay = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_By} : {32'b0,iChannel_By}; //Ay |
`MAG: wAddSubB_Ay = wAddSubA_Result; //A^2+B^2 |
`DOT: wAddSubB_Ay = wAddSubA_Result; //Ax*Bx + Ay*By |
`CROSS: wAddSubB_Ay = wMultiplicationC_Result; |
default: wAddSubB_Ay = 64'b0; |
endcase |
case (iOperation) |
`ADD: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`SUB: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`INC,`INCX,`INCY,`INCZ: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`DEC: wAddSubB_Ay = (iChannel_Ay[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_Ay} : {32'b0,iChannel_Ay}; //Ay |
`MOD: wAddSubB_Ay = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF, iChannel_By} : {32'b0,iChannel_By}; //Ay |
`MAG: wAddSubB_Ay = wAddSubA_Result; //A^2+B^2 |
`DOT: wAddSubB_Ay = wAddSubA_Result; //Ax*Bx + Ay*By |
`CROSS: wAddSubB_Ay = wMultiplicationC_Result; |
default: wAddSubB_Ay = 64'b0; |
endcase |
end |
//---------------------------- |
//wAddSubB_By 2:1 input Mux |
always @ ( * ) |
begin |
case (iOperation) |
`ADD: wAddSubB_By = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_By } : {32'b0,iChannel_By}; //By |
`SUB: wAddSubB_By = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_By } : {32'b0,iChannel_By}; //{32'b0,iChannel_By}; //By |
`INC,`INCY: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE); |
`INCX,`INCZ: wAddSubB_By = `LONG_WIDTH'd0; |
`DEC: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE); |
`MOD: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE); |
`MAG: wAddSubB_By = wMultiplicationC_Result; //C^2 |
`DOT: wAddSubB_By = wMultiplicationC_Result; //Az * Bz |
`CROSS: wAddSubB_By = wMultiplicationD_Result; |
default: wAddSubB_By = 32'b0; |
endcase |
case (iOperation) |
`ADD: wAddSubB_By = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_By } : {32'b0,iChannel_By}; //By |
`SUB: wAddSubB_By = (iChannel_By[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_By } : {32'b0,iChannel_By}; //{32'b0,iChannel_By}; //By |
`INC,`INCY: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE); |
`INCX,`INCZ: wAddSubB_By = `LONG_WIDTH'd0; |
`DEC: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE); |
`MOD: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE); |
`MAG: wAddSubB_By = wMultiplicationC_Result; //C^2 |
`DOT: wAddSubB_By = wMultiplicationC_Result; //Az * Bz |
`CROSS: wAddSubB_By = wMultiplicationD_Result; |
default: wAddSubB_By = `LONG_WIDTH'b0; |
endcase |
end |
//-------------------------------------------------------------- |
wire [`LONG_WIDTH-1:0] wAddSubC_Result; |
845,34 → 844,34
|
//----------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wAddSubC_Az = wMultiplicationE_Result; |
`MOD: wAddSubC_Az = (iChannel_Bz[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Bz} : {32'b0,iChannel_Bz}; |
default: wAddSubC_Az = (iChannel_Az[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Az} : {32'b0,iChannel_Az}; |
endcase |
end |
begin |
case (iOperation) |
`CROSS: wAddSubC_Az = wMultiplicationE_Result; |
`MOD: wAddSubC_Az = (iChannel_Bz[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Bz} : {32'b0,iChannel_Bz}; |
default: wAddSubC_Az = (iChannel_Az[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Az} : {32'b0,iChannel_Az}; |
endcase |
end |
//----------------------------------------- |
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wAddSubC_Bz = wMultiplicationF_Result; |
`INC,`INCZ: wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE); |
`INCX,`INCY: wAddSubC_Bz = `LONG_WIDTH'd0; |
`DEC: wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE); |
`MOD: wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE); |
default: wAddSubC_Bz = (iChannel_Bz[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Bz} : {32'b0,iChannel_Bz}; |
endcase |
end |
begin |
case (iOperation) |
`CROSS: wAddSubC_Bz = wMultiplicationF_Result; |
`INC,`INCZ: wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE); |
`INCX,`INCY: wAddSubC_Bz = `LONG_WIDTH'd0; |
`DEC: wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE); |
`MOD: wAddSubC_Bz = (`LONG_WIDTH'd1 << `SCALE); |
default: wAddSubC_Bz = (iChannel_Bz[31] == 1'b1) ? {32'hFFFFFFFF,iChannel_Bz} : {32'b0,iChannel_Bz}; |
endcase |
end |
//----------------------------------------- |
|
assign wAddSubC_Operation |
= ( |
iOperation == `SUB |
|| iOperation == `CROSS |
|| iOperation == `DEC |
|| iOperation == `MOD |
) ? 1 : 0; |
= ( |
iOperation == `SUB |
|| iOperation == `CROSS |
|| iOperation == `DEC |
|| iOperation == `MOD |
) ? 1 : 0; |
|
FixedAddSub AddSubChannel_C |
( |
882,19 → 881,19
.B( wAddSubC_Bz ), |
.R( wAddSubC_Result ), |
.iOperation( wAddSubC_Operation ), |
.iInputReady( wAddSubC_InputReady ), |
.OutputReady( wAddSubC_OutputReady ) |
.iInputReady( wAddSubC_InputReady ), |
.OutputReady( wAddSubC_OutputReady ) |
); |
|
|
always @ ( * ) |
begin |
case (iOperation) |
`CROSS: wAddSubC_InputReady = wMultiplicationE_OutputReady && |
wMultiplicationF_OutputReady; |
|
default: wAddSubC_InputReady = iInputReady; |
endcase |
begin |
case (iOperation) |
`CROSS: wAddSubC_InputReady = wMultiplicationE_OutputReady && |
wMultiplicationF_OutputReady; |
|
default: wAddSubC_InputReady = iInputReady; |
endcase |
end |
|
//------------------------------------------------------ |
904,18 → 903,18
|
FixedPointSquareRoot SQROOT1 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Operand( wAddSubB_Result ), |
.iInputReady( wAddSubBOutputReady && iOperation == `MAG), |
.OutputReady( wSquareRoot_OutputReady ), |
.Result( wSquareRoot_Result ) |
.Clock( Clock ), |
.Reset( Reset ), |
.Operand( wAddSubB_Result ), |
.iInputReady( wAddSubBOutputReady && iOperation == `MAG), |
.OutputReady( wSquareRoot_OutputReady ), |
.Result( wSquareRoot_Result ) |
); |
//------------------------------------------------------ |
|
assign wModulus2N_ResultA = (iChannel_Ax & wAddSubA_Result ); |
assign wModulus2N_ResultB = (iChannel_Ay & wAddSubB_Result ); |
assign wModulus2N_ResultC = (iChannel_Az & wAddSubC_Result ); |
assign wModulus2N_ResultA = ({32'b0,iChannel_Ax} & wAddSubA_Result ); |
assign wModulus2N_ResultB = ({32'b0,iChannel_Ay} & wAddSubB_Result ); |
assign wModulus2N_ResultC = ({32'b0,iChannel_Az} & wAddSubC_Result ); |
|
|
|
929,134 → 928,134
|
always @ ( * ) |
begin |
case ( iOperation ) |
`RETURN: ResultA = iChannel_Ax; |
`ADD: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};// & 32'h7FFFFFFF; |
`SUB: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};//wAddSubA_Result[31:0]; |
`CROSS: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};//wAddSubA_Result[31:0]; |
`DIV: ResultA = wDivisionA_Result; |
`MUL: ResultA = wMultiplicationA_Result[31:0]; |
`IMUL: ResultA = wMultiplicationA_Result[31:0]; |
`DOT: ResultA = (wAddSubB_Result[63] == 1'b1) ? { 1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`MAG: ResultA = wSquareRoot_Result; |
`ZERO: ResultA = 32'b0; |
`COPY: ResultA = iChannel_Ax; |
`TMREAD: ResultA = iTMEMReadData[95:64]; |
`LEA: ResultA = {16'b0,iCurrentIP}; |
|
`SWIZZLE3D: ResultA = wSwizzleOutputX; |
|
//Set Operations |
`UNSCALE: ResultA = iChannel_Ax >> `SCALE; |
`SETX,`RET: ResultA = iChannel_Ax; |
`SETY: ResultA = iChannel_Bx; |
`SETZ: ResultA = iChannel_Bx; |
`INC,`INCX,`INCY,`INCZ: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]}; |
`DEC: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]}; |
`MOD: ResultA = wModulus2N_ResultA; |
`FRAC: ResultA = iChannel_Ax & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE)); |
`MULP: ResultA = iChannel_Ax; |
`NEG: ResultA = ~iChannel_Ax + 1'b1; |
`XCHANGEX: ResultA = iChannel_Bx; |
case ( iOperation ) |
`RETURN: ResultA = iChannel_Ax; |
`ADD: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};// & 32'h7FFFFFFF; |
`SUB: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};//wAddSubA_Result[31:0]; |
`CROSS: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};//wAddSubA_Result[31:0]; |
`DIV: ResultA = wDivisionA_Result; |
`MUL: ResultA = wMultiplicationA_Result[31:0]; |
`IMUL: ResultA = wMultiplicationA_Result[31:0]; |
`DOT: ResultA = (wAddSubB_Result[63] == 1'b1) ? { 1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`MAG: ResultA = wSquareRoot_Result; |
`ZERO: ResultA = 32'b0; |
`COPY: ResultA = iChannel_Ax; |
`TMREAD: ResultA = iTMEMReadData[95:64]; |
`LEA: ResultA = {16'b0,iCurrentIP}; |
|
`SWIZZLE3D: ResultA = wSwizzleOutputX; |
|
//Set Operations |
`UNSCALE: ResultA = iChannel_Ax >> `SCALE; |
`SETX,`RET: ResultA = iChannel_Ax; |
`SETY: ResultA = iChannel_Bx; |
`SETZ: ResultA = iChannel_Bx; |
`INC,`INCX,`INCY,`INCZ: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]}; |
`DEC: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]}; |
`MOD: ResultA = wModulus2N_ResultA[31:0]; |
`FRAC: ResultA = iChannel_Ax & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE)); |
`MULP: ResultA = iChannel_Ax; |
`NEG: ResultA = ~iChannel_Ax + 1'b1; |
`XCHANGEX: ResultA = iChannel_Bx; |
|
default: |
begin |
`ifdef DEBUG |
// $display("%dns ALU: Error Unknown Operation: %d",$time,iOperation); |
// $stop(); |
`endif |
ResultA = 32'b0; |
end |
endcase |
default: |
begin |
`ifdef DEBUG |
// $display("%dns ALU: Error Unknown Operation: %d",$time,iOperation); |
// $stop(); |
`endif |
ResultA = 32'b0; |
end |
endcase |
end |
//------------------------------------------------------ |
//****Mux for RB*** |
always @ ( * ) |
begin |
case ( iOperation ) |
`RETURN: ResultB = iChannel_Ax; |
`ADD: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF; |
`SUB: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; //wAddSubB_Result[31:0]; |
`CROSS: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`DIV: ResultB = wDivisionB_Result; |
`MUL: ResultB = wMultiplicationB_Result[31:0]; |
`IMUL: ResultB = wMultiplicationB_Result[31:0]; |
`DOT: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`MAG: ResultB = wSquareRoot_Result; |
`ZERO: ResultB = 32'b0; |
`COPY: ResultB = iChannel_Ay; |
`TMREAD: ResultB = iTMEMReadData[63:32]; |
`LEA: ResultB = {16'b0,iCurrentIP}; |
|
//Set Operations |
`UNSCALE: ResultB = iChannel_Ay >> `SCALE; |
`SETX,`RET: ResultB = iChannel_By; // {Source1[95:64],Source0[63:32],Source0[31:0]}; |
`SETY: ResultB = iChannel_Ax; // {Source0[95:64],Source1[95:64],Source0[31:0]}; |
`SETZ: ResultB = iChannel_By; // {Source0[95:64],Source0[63:32],Source1[95:64]}; |
|
`SWIZZLE3D: ResultB = wSwizzleOutputY; |
|
`INC,`INCX,`INCY,`INCZ: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF; |
`DEC: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF; |
`MOD: ResultB = wModulus2N_ResultB; |
`FRAC: ResultB = iChannel_Ay & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE)); |
`MULP: ResultB = iChannel_Ay; |
`NEG: ResultB = ~iChannel_Ay + 1'b1; |
`XCHANGEX: ResultB = iChannel_Ay; |
|
default: |
begin |
`ifdef DEBUG |
//$display("%dns ALU: Error Unknown Operation: %d",$time,iOperation); |
//$stop(); |
`endif |
ResultB = 32'b0; |
end |
endcase |
case ( iOperation ) |
`RETURN: ResultB = iChannel_Ax; |
`ADD: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF; |
`SUB: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; //wAddSubB_Result[31:0]; |
`CROSS: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`DIV: ResultB = wDivisionB_Result; |
`MUL: ResultB = wMultiplicationB_Result[31:0]; |
`IMUL: ResultB = wMultiplicationB_Result[31:0]; |
`DOT: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`MAG: ResultB = wSquareRoot_Result; |
`ZERO: ResultB = 32'b0; |
`COPY: ResultB = iChannel_Ay; |
`TMREAD: ResultB = iTMEMReadData[63:32]; |
`LEA: ResultB = {16'b0,iCurrentIP}; |
|
//Set Operations |
`UNSCALE: ResultB = iChannel_Ay >> `SCALE; |
`SETX,`RET: ResultB = iChannel_By; // {Source1[95:64],Source0[63:32],Source0[31:0]}; |
`SETY: ResultB = iChannel_Ax; // {Source0[95:64],Source1[95:64],Source0[31:0]}; |
`SETZ: ResultB = iChannel_By; // {Source0[95:64],Source0[63:32],Source1[95:64]}; |
|
`SWIZZLE3D: ResultB = wSwizzleOutputY; |
|
`INC,`INCX,`INCY,`INCZ: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF; |
`DEC: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF; |
`MOD: ResultB = wModulus2N_ResultB[31:0]; |
`FRAC: ResultB = iChannel_Ay & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE)); |
`MULP: ResultB = iChannel_Ay; |
`NEG: ResultB = ~iChannel_Ay + 1'b1; |
`XCHANGEX: ResultB = iChannel_Ay; |
|
default: |
begin |
`ifdef DEBUG |
//$display("%dns ALU: Error Unknown Operation: %d",$time,iOperation); |
//$stop(); |
`endif |
ResultB = 32'b0; |
end |
endcase |
end |
//------------------------------------------------------ |
//****Mux for RC*** |
always @ ( * ) |
begin |
case ( iOperation ) |
`RETURN: ResultC = iChannel_Ax; |
`ADD: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF; |
`SUB: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0]; |
`CROSS: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]};//wAddSubC_Result[31:0]; |
`DIV: ResultC = wDivisionC_Result; |
`MUL: ResultC = wMultiplicationC_Result[31:0]; |
`IMUL: ResultC = wMultiplicationC_Result[31:0]; |
`DOT: ResultC = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`MAG: ResultC = wSquareRoot_Result; |
`ZERO: ResultC = 32'b0; |
`COPY: ResultC = iChannel_Az; |
`TMREAD: ResultC = iTMEMReadData[31:0]; |
`LEA: ResultC = {16'b0,iCurrentIP}; |
|
`SWIZZLE3D: ResultC = wSwizzleOutputZ; |
|
//Set Operations |
`UNSCALE: ResultC = iChannel_Az >> `SCALE; |
`SETX,`RET: ResultC = iChannel_Bz; // {Source1[95:64],Source0[63:32],Source0[31:0]}; |
`SETY: ResultC = iChannel_Bz; // {Source0[95:64],Source1[95:64],Source0[31:0]}; |
`SETZ: ResultC = iChannel_Ax; // {Source0[95:64],Source0[63:32],Source1[95:64]}; |
|
`INC,`INCX,`INCY,`INCZ: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF; |
`DEC: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF; |
`MOD: ResultC = wModulus2N_ResultC; |
`FRAC: ResultC = iChannel_Az & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE)); |
`MULP: ResultC = wMultiplicationA_Result[31:0]; |
`NEG: ResultC = ~iChannel_Az + 1'b1; |
`XCHANGEX: ResultC = iChannel_Az; |
default: |
begin |
`ifdef DEBUG |
//$display("%dns ALU: Error Unknown Operation: %d",$time,iOperation); |
//$stop(); |
`endif |
ResultC = 32'b0; |
end |
endcase |
case ( iOperation ) |
`RETURN: ResultC = iChannel_Ax; |
`ADD: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF; |
`SUB: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0]; |
`CROSS: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]};//wAddSubC_Result[31:0]; |
`DIV: ResultC = wDivisionC_Result; |
`MUL: ResultC = wMultiplicationC_Result[31:0]; |
`IMUL: ResultC = wMultiplicationC_Result[31:0]; |
`DOT: ResultC = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0]; |
`MAG: ResultC = wSquareRoot_Result; |
`ZERO: ResultC = 32'b0; |
`COPY: ResultC = iChannel_Az; |
`TMREAD: ResultC = iTMEMReadData[31:0]; |
`LEA: ResultC = {16'b0,iCurrentIP}; |
|
`SWIZZLE3D: ResultC = wSwizzleOutputZ; |
|
//Set Operations |
`UNSCALE: ResultC = iChannel_Az >> `SCALE; |
`SETX,`RET: ResultC = iChannel_Bz; // {Source1[95:64],Source0[63:32],Source0[31:0]}; |
`SETY: ResultC = iChannel_Bz; // {Source0[95:64],Source1[95:64],Source0[31:0]}; |
`SETZ: ResultC = iChannel_Ax; // {Source0[95:64],Source0[63:32],Source1[95:64]}; |
|
`INC,`INCX,`INCY,`INCZ: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF; |
`DEC: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF; |
`MOD: ResultC = wModulus2N_ResultC[31:0]; |
`FRAC: ResultC = iChannel_Az & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE)); |
`MULP: ResultC = wMultiplicationA_Result[31:0]; |
`NEG: ResultC = ~iChannel_Az + 1'b1; |
`XCHANGEX: ResultC = iChannel_Az; |
default: |
begin |
`ifdef DEBUG |
//$display("%dns ALU: Error Unknown Operation: %d",$time,iOperation); |
//$stop(); |
`endif |
ResultC = 32'b0; |
end |
endcase |
end |
//------------------------------------------------------------------------ |
|
1063,64 → 1062,94
|
always @ ( * ) |
begin |
case (iOperation) |
`JMP,`CALL,`RET: oBranchTaken = OutputReady; |
`JGX: oBranchTaken = wArithmeticComparison_Result; |
`JGY: oBranchTaken = wArithmeticComparison_Result; |
`JGZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JLX: oBranchTaken = wArithmeticComparison_Result; |
`JLY: oBranchTaken = wArithmeticComparison_Result; |
`JLZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JEQX: oBranchTaken = wArithmeticComparison_Result; |
`JEQY: oBranchTaken = wArithmeticComparison_Result; |
`JEQZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JNEX: oBranchTaken = wArithmeticComparison_Result; |
`JNEY: oBranchTaken = wArithmeticComparison_Result; |
`JNEZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JGEX: oBranchTaken = wArithmeticComparison_Result; |
`JGEY: oBranchTaken = wArithmeticComparison_Result; |
`JGEZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JLEX: oBranchTaken = wArithmeticComparison_Result; |
`JLEY: oBranchTaken = wArithmeticComparison_Result; |
`JLEZ: oBranchTaken = wArithmeticComparison_Result; |
|
default: oBranchTaken = 0; |
endcase |
|
case (iOperation) |
`JMP,`CALL,`RET: oBranchTaken = OutputReady; |
`JGX: oBranchTaken = wArithmeticComparison_Result; |
`JGY: oBranchTaken = wArithmeticComparison_Result; |
`JGZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JLX: oBranchTaken = wArithmeticComparison_Result; |
`JLY: oBranchTaken = wArithmeticComparison_Result; |
`JLZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JEQX: oBranchTaken = wArithmeticComparison_Result; |
`JEQY: oBranchTaken = wArithmeticComparison_Result; |
`JEQZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JNEX: oBranchTaken = wArithmeticComparison_Result; |
`JNEY: oBranchTaken = wArithmeticComparison_Result; |
`JNEZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JGEX: oBranchTaken = wArithmeticComparison_Result; |
`JGEY: oBranchTaken = wArithmeticComparison_Result; |
`JGEZ: oBranchTaken = wArithmeticComparison_Result; |
|
`JLEX: oBranchTaken = wArithmeticComparison_Result; |
`JLEY: oBranchTaken = wArithmeticComparison_Result; |
`JLEZ: oBranchTaken = wArithmeticComparison_Result; |
|
default: oBranchTaken = 0; |
endcase |
|
end |
|
always @ ( * ) |
begin |
case (iOperation) |
|
`JMP,`CALL,`RET,`JGX,`JGY,`JGZ,`JLX,`JLY,`JLZ,`JEQX,`JEQY,`JEQZ, |
`JNEX,`JNEY,`JNEZ,`JGEX,`JGEY,`JGEZ: oBranchNotTaken = !oBranchTaken && OutputReady; |
`JLEX: oBranchNotTaken = !oBranchTaken && OutputReady; |
`JLEY: oBranchNotTaken = !oBranchTaken && OutputReady; |
`JLEZ: oBranchNotTaken = !oBranchTaken && OutputReady; |
default: |
oBranchNotTaken = 0; |
endcase |
case (iOperation) |
|
`JMP,`CALL,`RET,`JGX,`JGY,`JGZ,`JLX,`JLY,`JLZ,`JEQX,`JEQY,`JEQZ, |
`JNEX,`JNEY,`JNEZ,`JGEX,`JGEY,`JGEZ: oBranchNotTaken = !oBranchTaken && OutputReady; |
`JLEX: oBranchNotTaken = !oBranchTaken && OutputReady; |
`JLEY: oBranchNotTaken = !oBranchTaken && OutputReady; |
`JLEZ: oBranchNotTaken = !oBranchTaken && OutputReady; |
default: |
oBranchNotTaken = 0; |
endcase |
end |
//------------------------------------------------------------------------ |
//Output ready logic Stuff for Division... |
//Some FFT will hopefully do the trick |
/* verilator lint_off UNOPTFLAT*/ |
|
wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC ; |
wire wDivisionOutputReady; |
/* verilator lint_on UNOPTFLAT*/ |
|
|
|
assign wAddSubAOutputReady = wAddSubA_OutputReady; |
assign wAddSubBOutputReady = wAddSubB_OutputReady; |
assign wAddSubCOutputReady = wAddSubC_OutputReady; |
|
wire wDivA_tmp, wDivB_tmp, wDivC_tmp; |
UPCOUNTER_POSEDGE # (1) FFT_DivisionA |
( |
.Clock(Clock), |
.Reset(Reset | iInputReady), |
.Initial(1'b0), |
.Enable(wDivisionA_OutputReady), |
.Q(wDivA_tmp) |
); |
|
assign wDivisionOutputReadyA = ((wDivA_tmp | wDivisionA_OutputReady) & ~iInputReady); |
UPCOUNTER_POSEDGE # (1) FFT_DivisionB |
( |
.Clock(Clock), |
.Reset(Reset | iInputReady), |
.Initial(1'b0), |
.Enable(wDivisionB_OutputReady), |
.Q(wDivB_tmp) |
); |
assign wDivisionOutputReadyB = ((wDivB_tmp | wDivisionB_OutputReady) & ~iInputReady); |
|
UPCOUNTER_POSEDGE # (1) FFT_DivisionC |
( |
.Clock(Clock), |
.Reset(Reset | iInputReady), |
.Initial(1'b0), |
.Enable(wDivisionC_OutputReady), |
.Q(wDivC_tmp) |
); |
assign wDivisionOutputReadyC = ((wDivC_tmp | wDivisionC_OutputReady) & ~iInputReady); |
/* |
FFT1 FFT_DivisionA |
( |
.D(1'b1), |
1144,7 → 1173,7
.Reset( iInputReady ), |
.Q( wDivisionOutputReadyC ) |
); |
|
*/ |
assign wDivisionOutputReady = |
( wDivisionOutputReadyA && wDivisionOutputReadyB && wDivisionOutputReadyC ); |
|
1173,20 → 1202,20
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputReadyDelay2 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1), |
.D( iInputReady ), |
.Q( wOutputDelay1Cycle ) |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1), |
.D( iInputReady ), |
.Q( wOutputDelay1Cycle ) |
); |
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputReadyDelay22 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1), |
.D( wOutputDelay1Cycle ), |
.Q( wOutputDelay2Cycle ) |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1), |
.D( wOutputDelay1Cycle ), |
.Q( wOutputDelay2Cycle ) |
); |
wire wIsOMWRITE; |
assign wIsOMWRITE = (wOperation == `OMWRITE) ? 1'b1: 1'b0; |
1193,20 → 1222,20
|
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputReadyDelay222 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(wIsOMWRITE), |
.D( wOutputDelay2Cycle ), |
.Q( wOutputDelay3Cycle ) |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(wIsOMWRITE), |
.D( wOutputDelay2Cycle ), |
.Q( wOutputDelay3Cycle ) |
); |
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) SourceZ2 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable( iInputReady ), |
.D( iOperation ), |
.Q(wOperation) |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable( iInputReady ), |
.D( iOperation ), |
.Q(wOperation) |
); |
|
|
1213,76 → 1242,76
//Mux for output ready signal |
always @ ( * ) |
begin |
case ( wOperation ) |
`UNSCALE: OutputReady = wOutputDelay1Cycle; |
`RETURN: OutputReady = wOutputDelay1Cycle; |
|
`NOP: OutputReady = wOutputDelay1Cycle; |
`FRAC: OutputReady = wOutputDelay1Cycle; |
`NEG: OutputReady = wOutputDelay1Cycle; |
`OMWRITE: OutputReady = wOutputDelay3Cycle; |
`TMREAD: OutputReady = wTMReadOutputReady; //One cycle after TMEM data availale asserted |
|
`ifdef DEBUG |
//Debug Print behaves as a NOP in terms of ALU... |
`DEBUG_PRINT: OutputReady = wOutputDelay1Cycle; |
`endif |
|
`ADD,`INC,`INCX,`INCY,`INCZ: OutputReady = wAddSubAOutputReady && |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`SUB,`DEC: OutputReady = wAddSubAOutputReady && |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`DIV: OutputReady = wDivisionOutputReady; |
|
|
`MUL,`IMUL: OutputReady = wMultiplicationOutputReady; |
`MULP: OutputReady = wMultiplicationOutputReadyA; |
|
`DOT: OutputReady = wAddSubBOutputReady; |
|
`CROSS: OutputReady = wAddSubAOutputReady && |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`MAG: OutputReady = wSquareRootOutputReady; |
|
`ZERO: OutputReady = wOutputDelay1Cycle; |
|
`COPY: OutputReady = wOutputDelay1Cycle; |
|
`SWIZZLE3D: OutputReady = wOutputDelay1Cycle; |
|
`SETX,`SETY,`SETZ,`JMP,`LEA,`CALL,`RET: OutputReady = wOutputDelay1Cycle; |
|
case ( wOperation ) |
`UNSCALE: OutputReady = wOutputDelay1Cycle; |
`RETURN: OutputReady = wOutputDelay1Cycle; |
|
`NOP: OutputReady = wOutputDelay1Cycle; |
`FRAC: OutputReady = wOutputDelay1Cycle; |
`NEG: OutputReady = wOutputDelay1Cycle; |
`OMWRITE: OutputReady = wOutputDelay3Cycle; |
`TMREAD: OutputReady = wTMReadOutputReady; //One cycle after TMEM data availale asserted |
|
`ifdef DEBUG |
//Debug Print behaves as a NOP in terms of ALU... |
`DEBUG_PRINT: OutputReady = wOutputDelay1Cycle; |
`endif |
|
`ADD,`INC,`INCX,`INCY,`INCZ: OutputReady = wAddSubAOutputReady && |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`SUB,`DEC: OutputReady = wAddSubAOutputReady && |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`DIV: OutputReady = wDivisionOutputReady; |
|
|
`MUL,`IMUL: OutputReady = wMultiplicationOutputReady; |
`MULP: OutputReady = wMultiplicationOutputReadyA; |
|
`DOT: OutputReady = wAddSubBOutputReady; |
|
`CROSS: OutputReady = wAddSubAOutputReady && |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`MAG: OutputReady = wSquareRootOutputReady; |
|
`ZERO: OutputReady = wOutputDelay1Cycle; |
|
`COPY: OutputReady = wOutputDelay1Cycle; |
|
`SWIZZLE3D: OutputReady = wOutputDelay1Cycle; |
|
`SETX,`SETY,`SETZ,`JMP,`LEA,`CALL,`RET: OutputReady = wOutputDelay1Cycle; |
|
|
|
`JGX,`JGY,`JGZ: OutputReady = ArithmeticComparison_OutputReady; |
`JLX,`JLY,`JLZ: OutputReady = ArithmeticComparison_OutputReady; |
`JEQX,`JEQY,`JEQZ: OutputReady = ArithmeticComparison_OutputReady; |
`JNEX,`JNEY,`JNEZ: OutputReady = ArithmeticComparison_OutputReady; |
`JGEX,`JGEY,`JGEZ: OutputReady = ArithmeticComparison_OutputReady; |
`JLEX,`JLEY,`JLEZ: OutputReady = ArithmeticComparison_OutputReady; |
|
`MOD: OutputReady = wAddSubAOutputReady && //TODO: wait 1 more cycle |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`XCHANGEX: OutputReady = wOutputDelay1Cycle; |
|
|
default: |
begin |
OutputReady = 32'b0; |
//`ifdef DEBUG |
//$display("*** ALU ERROR: iOperation = %d ***",iOperation); |
//`endif |
end |
|
endcase |
|
`JGX,`JGY,`JGZ: OutputReady = ArithmeticComparison_OutputReady; |
`JLX,`JLY,`JLZ: OutputReady = ArithmeticComparison_OutputReady; |
`JEQX,`JEQY,`JEQZ: OutputReady = ArithmeticComparison_OutputReady; |
`JNEX,`JNEY,`JNEZ: OutputReady = ArithmeticComparison_OutputReady; |
`JGEX,`JGEY,`JGEZ: OutputReady = ArithmeticComparison_OutputReady; |
`JLEX,`JLEY,`JLEZ: OutputReady = ArithmeticComparison_OutputReady; |
|
`MOD: OutputReady = wAddSubAOutputReady && //TODO: wait 1 more cycle |
wAddSubBOutputReady && |
wAddSubCOutputReady; |
|
`XCHANGEX: OutputReady = wOutputDelay1Cycle; |
|
|
default: |
begin |
OutputReady = 1'b0; |
//`ifdef DEBUG |
//$display("*** ALU ERROR: iOperation = %d ***",iOperation); |
//`endif |
end |
|
endcase |
end |
|
endmodule |
/Unit_EXE.v
33,34 → 33,28
|
input wire Clock, |
input wire Reset, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iInitialCodeAddress, |
input wire [`INSTRUCTION_WIDTH-1:0] iInstruction1, |
input wire [`INSTRUCTION_WIDTH-1:0] iInstruction2, |
|
|
input wire [`DATA_ROW_WIDTH-1:0] iDataRead0, |
input wire [`DATA_ROW_WIDTH-1:0] iDataRead1, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iInitialCodeAddress, |
input wire [`INSTRUCTION_WIDTH-1:0] iInstruction1, |
input wire [`INSTRUCTION_WIDTH-1:0] iInstruction2, |
input wire [`DATA_ROW_WIDTH-1:0] iDataRead0, |
input wire [`DATA_ROW_WIDTH-1:0] iDataRead1, |
input wire iTrigger, |
|
|
output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionPointer1, |
output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionPointer2, |
output wire [`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress0, |
output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionPointer1, |
output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionPointer2, |
output wire [`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress0, |
output wire [`DATA_ADDRESS_WIDTH-1:0] oDataReadAddress1, |
output wire oDataWriteEnable, |
output wire [`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress, |
output wire [`DATA_ROW_WIDTH-1:0] oDataBus, |
output wire oDataWriteEnable, |
output wire [`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress, |
output wire [`DATA_ROW_WIDTH-1:0] oDataBus, |
output wire oReturnCode, |
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress, |
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData, |
output wire oOMEMWriteEnable, |
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress, |
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData, |
input wire iTMEMDataAvailable, |
output wire oTMEMDataRequest, |
|
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress, |
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData, |
output wire oOMEMWriteEnable, |
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress, |
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData, |
input wire iTMEMDataAvailable, |
output wire oTMEMDataRequest, |
|
`ifdef DEBUG |
input wire [`MAX_CORES-1:0] iDebug_CoreID, |
`endif |
73,44 → 67,40
|
|
`ifdef DEBUG |
wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer; |
wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer; |
`endif |
|
wire wEXE2__uCodeDone; |
wire wEXE2_IFU__EXEBusy; |
wire [`DATA_ADDRESS_WIDTH-1:0] wEXE2_IDU_DataFordward_LastDestination; |
wire wALU2_EXE__BranchTaken; |
wire wALU2_IFU_BranchNotTaken; |
wire [`INSTRUCTION_WIDTH-1:0] CurrentInstruction; |
//wire wIDU2_IFU__IDUBusy; |
|
/* verilator lint_off UNOPTFLAT*/ |
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation /* verilator isolate_assignments*/; |
/* verilator lint_on UNOPTFLAT*/ |
|
wire [`DATA_ROW_WIDTH-1:0] wSource0,wSource1; |
wire [`DATA_ADDRESS_WIDTH-1:0] wDestination; |
wire wEXE2__uCodeDone; |
wire wEXE2_IFU__EXEBusy; |
wire [`DATA_ADDRESS_WIDTH-1:0] wEXE2_IDU_DataFordward_LastDestination; |
wire wALU2_EXE__BranchTaken; |
wire wALU2_IFU_BranchNotTaken; |
wire [`INSTRUCTION_WIDTH-1:0] wCurrentInstruction; |
/* verilator lint_off UNOPTFLAT */ |
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation; |
/* verilator lint_on UNOPTFLAT */ |
wire [`DATA_ROW_WIDTH-1:0] wSource0,wSource1; |
wire [`DATA_ADDRESS_WIDTH-1:0] wDestination; |
wire wInstructionAvailable; |
|
//ALU wires |
wire [`INSTRUCTION_OP_LENGTH-1:0] ALU2Operation; |
wire [`WIDTH-1:0] ALU2ChannelA; |
wire [`WIDTH-1:0] ALU2ChannelB; |
wire [`WIDTH-1:0] ALU2ChannelC; |
wire [`WIDTH-1:0] ALU2ChannelD; |
wire [`WIDTH-1:0] ALU2ChannelE; |
wire [`WIDTH-1:0] ALU2ChannelF; |
wire [`WIDTH-1:0] ALU2ResultA; |
wire [`WIDTH-1:0] ALU2ResultB; |
wire [`WIDTH-1:0] ALU2ResultC; |
wire wEXE2_ALU__TriggerALU; |
wire ALU2OutputReady; |
wire w2FIU__BranchTaken; |
wire [`ROM_ADDRESS_WIDTH-1:0] JumpIp; |
wire [`INSTRUCTION_OP_LENGTH-1:0] ALU2Operation; |
wire [`WIDTH-1:0] ALU2ChannelA; |
wire [`WIDTH-1:0] ALU2ChannelB; |
wire [`WIDTH-1:0] ALU2ChannelC; |
wire [`WIDTH-1:0] ALU2ChannelD; |
wire [`WIDTH-1:0] ALU2ChannelE; |
wire [`WIDTH-1:0] ALU2ChannelF; |
wire [`WIDTH-1:0] ALU2ResultA; |
wire [`WIDTH-1:0] ALU2ResultB; |
wire [`WIDTH-1:0] ALU2ResultC; |
wire wEXE2_ALU__TriggerALU; |
wire ALU2OutputReady; |
wire w2FIU__BranchTaken; |
wire [`ROM_ADDRESS_WIDTH-1:0] JumpIp; |
wire [`ROM_ADDRESS_WIDTH-1:0] wIDU2_IFU_ReturnAddress; |
wire wALU2_IFU_ReturnFromSub; |
|
//wire wIDU2_IFU__InputsLatched; |
//wire wIDU2_IFU__InputsLatched; |
|
wire wEPU_Busy,wTriggerIFU; |
wire [`ROM_ADDRESS_WIDTH-1:0] wEPU_IP,wIFU_IP,wCodeEntryPoint; |
138,18 → 128,18
.Clock( Clock ), |
.Reset( Reset ), |
.iTrigger( wTriggerIFU ), |
.iInstruction1( iInstruction1 ), |
.iInstruction1( iInstruction1 ), |
.iInstruction2( iInstruction2 ), |
.iInitialCodeAddress( wCodeEntryPoint ), |
.iBranchTaken( w2FIU__BranchTaken ), |
.iSubroutineReturn( wALU2_IFU_ReturnFromSub ), |
//.iReturnAddress( wIDU2_IFU_ReturnAddress ), |
.oCurrentInstruction( CurrentInstruction ), |
.oCurrentInstruction( wCurrentInstruction ), |
.oInstructionAvalable( wInstructionAvailable ), |
.oIP( wIFU_IP ), |
.oIP2( oInstructionPointer2 ), |
.iEXEDone( ALU2OutputReady ), |
.oMicroCodeReturnValue( oReturnCode ), |
.oMicroCodeReturnValue( oReturnCode ), |
.oExecutionDone( oDone ) |
); |
|
159,83 → 149,83
|
InstructionDecode IDU |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.iEncodedInstruction( CurrentInstruction ), |
.iInstructionAvailable( wInstructionAvailable ), |
//.iIP( oInstructionPointer1 ), |
//.oReturnAddress( wIDU2_IFU_ReturnAddress ), |
|
.oRamAddress0( oDataReadAddress0 ), |
.oRamAddress1( oDataReadAddress1 ), |
.iRamValue0( iDataRead0 ), |
.iRamValue1( iDataRead1 ), |
|
.iLastDestination( wEXE2_IDU_DataFordward_LastDestination ), |
.iDataForward( {ALU2ResultA,ALU2ResultB,ALU2ResultC} ), |
|
//Outputs going to the ALU-FSM |
.oOperation( wOperation ), |
.oDestination( wDestination ), |
.oSource0( wSource0 ), |
.oSource1( wSource1 ), |
|
`ifdef DEBUG |
.iDebug_CurrentIP( oInstructionPointer1 ), |
.oDebug_CurrentIP( wDEBUG_IDU2_EXE_InstructionPointer ), |
`endif |
|
.oDataReadyForExe( wIDU2_EXE_DataReady ) |
|
|
|
|
|
.Clock( Clock ), |
.Reset( Reset ), |
.iEncodedInstruction( wCurrentInstruction ), |
.iInstructionAvailable( wInstructionAvailable ), |
//.iIP( oInstructionPointer1 ), |
//.oReturnAddress( wIDU2_IFU_ReturnAddress ), |
|
.oRamAddress0( oDataReadAddress0 ), |
.oRamAddress1( oDataReadAddress1 ), |
.iRamValue0( iDataRead0 ), |
.iRamValue1( iDataRead1 ), |
|
.iLastDestination( wEXE2_IDU_DataFordward_LastDestination ), |
.iDataForward( {ALU2ResultA,ALU2ResultB,ALU2ResultC} ), |
|
//Outputs going to the ALU-FSM |
.oOperation( wOperation ), |
.oDestination( wDestination ), |
.oSource0( wSource0 ), |
.oSource1( wSource1 ), |
|
`ifdef DEBUG |
.iDebug_CurrentIP( oInstructionPointer1 ), |
.oDebug_CurrentIP( wDEBUG_IDU2_EXE_InstructionPointer ), |
`endif |
|
.oDataReadyForExe( wIDU2_EXE_DataReady ) |
|
|
|
|
|
); |
|
|
ExecutionFSM EXE |
ExecutionFSM EXE |
( |
.Clock( Clock ), |
.Reset( Reset | iTrigger ), //New Sat Jun13 |
.iDecodeDone( wIDU2_EXE_DataReady ), |
.iOperation( wOperation ), |
.iDestination( wDestination ), |
.iSource0( wSource0 ), |
.iSource1( wSource1 ) , |
.Clock( Clock ), |
.Reset( Reset | iTrigger ), //New Sat Jun13 |
.iDecodeDone( wIDU2_EXE_DataReady ), |
.iOperation( wOperation ), |
.iDestination( wDestination ), |
.iSource0( wSource0 ), |
.iSource1( wSource1 ) , |
|
|
`ifdef DEBUG |
.iDebug_CurrentIP( wDEBUG_IDU2_EXE_InstructionPointer ), |
.iDebug_CoreID( iDebug_CoreID ), |
`endif |
|
//.iJumpResultFromALU( wALU2_EXE__BranchTaken ), |
.iBranchTaken( wALU2_EXE__BranchTaken ), |
.iBranchNotTaken( wALU2_IFU_BranchNotTaken ), |
.oJumpFlag( w2FIU__BranchTaken ), |
.oJumpIp( JumpIp ), |
.oRAMWriteEnable( oDataWriteEnable ), |
.oRAMWriteAddress( oDataWriteAddress ), |
.RAMBus( oDataBus ), |
.oBusy( wEXE2_IFU__EXEBusy ), |
|
`ifdef DEBUG |
.iDebug_CurrentIP( wDEBUG_IDU2_EXE_InstructionPointer ), |
.iDebug_CoreID( iDebug_CoreID ), |
`endif |
|
//.iJumpResultFromALU( wALU2_EXE__BranchTaken ), |
.iBranchTaken( wALU2_EXE__BranchTaken ), |
.iBranchNotTaken( wALU2_IFU_BranchNotTaken ), |
.oJumpFlag( w2FIU__BranchTaken ), |
.oJumpIp( JumpIp ), |
.oRAMWriteEnable( oDataWriteEnable ), |
.oRAMWriteAddress( oDataWriteAddress ), |
.RAMBus( oDataBus ), |
.oBusy( wEXE2_IFU__EXEBusy ), |
|
.oExeLatchedValues( wEXE2_IDU_ExeLatchedValues ), |
.oLastDestination( wEXE2_IDU_DataFordward_LastDestination ), |
.oExeLatchedValues( wEXE2_IDU_ExeLatchedValues ), |
.oLastDestination( wEXE2_IDU_DataFordward_LastDestination ), |
|
//ALU ports and control signals |
.oTriggerALU( wEXE2_ALU__TriggerALU ), |
.oALUOperation( ALU2Operation ), |
.oALUChannelX1( ALU2ChannelA ), |
.oALUChannelX2( ALU2ChannelB ), |
.oALUChannelY1( ALU2ChannelC ), |
.oALUChannelY2( ALU2ChannelD ), |
.oALUChannelZ1( ALU2ChannelE ), |
.oALUChannelZ2( ALU2ChannelF ), |
.iALUResultX( ALU2ResultA ), |
.iALUResultY( ALU2ResultB ), |
.iALUResultZ( ALU2ResultC ), |
.iALUOutputReady( ALU2OutputReady ) |
//ALU ports and control signals |
.oTriggerALU( wEXE2_ALU__TriggerALU ), |
.oALUOperation( ALU2Operation ), |
.oALUChannelX1( ALU2ChannelA ), |
.oALUChannelX2( ALU2ChannelB ), |
.oALUChannelY1( ALU2ChannelC ), |
.oALUChannelY2( ALU2ChannelD ), |
.oALUChannelZ1( ALU2ChannelE ), |
.oALUChannelZ2( ALU2ChannelF ), |
.iALUResultX( ALU2ResultA ), |
.iALUResultY( ALU2ResultB ), |
.iALUResultZ( ALU2ResultC ), |
.iALUOutputReady( ALU2OutputReady ) |
|
); |
|
244,38 → 234,38
|
VectorALU ALU |
( |
.Clock(Clock), |
.Reset(Reset), |
.iOperation( ALU2Operation ), |
.iChannel_Ax( ALU2ChannelA ), |
.iChannel_Bx( ALU2ChannelB ), |
.iChannel_Ay( ALU2ChannelC ), |
.iChannel_By( ALU2ChannelD ), |
.iChannel_Az( ALU2ChannelE ), |
.iChannel_Bz( ALU2ChannelF ), |
.oResultA( ALU2ResultA ), |
.oResultB( ALU2ResultB ), |
.oResultC( ALU2ResultC ), |
.oBranchTaken( wALU2_EXE__BranchTaken ), |
.oBranchNotTaken( wALU2_IFU_BranchNotTaken ), |
.oReturnFromSub( wALU2_IFU_ReturnFromSub ), |
.iInputReady( wEXE2_ALU__TriggerALU ), |
|
//*********** |
.oOMEMWriteAddress( oOMEMWriteAddress ), |
.oOMEMWriteData( oOMEMWriteData ), |
.oOMEM_WriteEnable( oOMEMWriteEnable ), |
|
.oTMEMReadAddress( oTMEMReadAddress ), |
.iTMEMReadData( iTMEMReadData ), |
.iTMEMDataAvailable( iTMEMDataAvailable ), |
.oTMEMDataRequest( oTMEMDataRequest ), |
//*********** |
.iCurrentIP( oInstructionPointer1 ), |
.OutputReady( ALU2OutputReady ) |
|
.Clock(Clock), |
.Reset(Reset), |
.iOperation( ALU2Operation ), |
.iChannel_Ax( ALU2ChannelA ), |
.iChannel_Bx( ALU2ChannelB ), |
.iChannel_Ay( ALU2ChannelC ), |
.iChannel_By( ALU2ChannelD ), |
.iChannel_Az( ALU2ChannelE ), |
.iChannel_Bz( ALU2ChannelF ), |
.oResultA( ALU2ResultA ), |
.oResultB( ALU2ResultB ), |
.oResultC( ALU2ResultC ), |
.oBranchTaken( wALU2_EXE__BranchTaken ), |
.oBranchNotTaken( wALU2_IFU_BranchNotTaken ), |
.oReturnFromSub( wALU2_IFU_ReturnFromSub ), |
.iInputReady( wEXE2_ALU__TriggerALU ), |
|
//*********** |
.oOMEMWriteAddress( oOMEMWriteAddress ), |
.oOMEMWriteData( oOMEMWriteData ), |
.oOMEM_WriteEnable( oOMEMWriteEnable ), |
|
.oTMEMReadAddress( oTMEMReadAddress ), |
.iTMEMReadData( iTMEMReadData ), |
.iTMEMDataAvailable( iTMEMDataAvailable ), |
.oTMEMDataRequest( oTMEMDataRequest ), |
//*********** |
.iCurrentIP( oInstructionPointer1 ), |
.OutputReady( ALU2OutputReady ) |
|
); |
|
|
|
|
endmodule |
/Module_FixedPointDivision.v
187,9 → 187,13
// divisor placed initially for a 1 bit overlap with dividend... |
// But adjust it back by S_PP, to account for bits that are known |
// to be leading zeros in the quotient. |
/* verilator lint_off WIDTH */ |
grand_divisor <= divisor_i << (N_PP+R_PP-S_PP-1); |
/* verilator lint_on WIDTH */ |
end |
/* verilator lint_off WIDTH */ |
else if (divide_count == M_PP+R_PP-S_PP-1) |
/* verilator lint_on WIDTH */ |
begin |
if (~done_o) quotient <= quotient_node; // final shift... |
if (~done_o) quotient_reg <= quotient_node; // final shift (held output) |
198,7 → 202,9
else // Division in progress |
begin |
// If the subtraction yields a positive result, then store that result |
/* verilator lint_off WIDTH */ |
if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node; |
/* verilator lint_on WIDTH */ |
// If the subtraction yields a positive result, then a 1 bit goes into |
// the quotient, via a shift register |
quotient <= quotient_node; |
210,7 → 216,9
end // End of else if clk_en_i |
end // End of always block |
|
/* verilator lint_off WIDTH */ |
assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor}; |
/* verilator lint_on WIDTH */ |
assign quotient_node = |
{quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]}; |
assign divisor_node = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]}; |
/Module_RAM.v
25,28 → 25,30
|
module RAM_DUAL_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 ) |
( |
input wire Clock, |
input wire iWriteEnable, |
input wire[ADDR_WIDTH-1:0] iReadAddress0, |
input wire[ADDR_WIDTH-1:0] iReadAddress1, |
input wire[ADDR_WIDTH-1:0] iWriteAddress, |
input wire[DATA_WIDTH-1:0] iDataIn, |
output reg [DATA_WIDTH-1:0] oDataOut0, |
output reg [DATA_WIDTH-1:0] oDataOut1 |
input wire Clock, |
input wire iWriteEnable, |
input wire[ADDR_WIDTH-1:0] iReadAddress0, |
input wire[ADDR_WIDTH-1:0] iReadAddress1, |
input wire[ADDR_WIDTH-1:0] iWriteAddress, |
input wire[DATA_WIDTH-1:0] iDataIn, |
output reg [DATA_WIDTH-1:0] oDataOut0, |
output reg [DATA_WIDTH-1:0] oDataOut1 |
); |
|
reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0]; |
reg [DATA_WIDTH-1:0] Ram [MEM_SIZE-1:0]; |
|
always @(posedge Clock) |
begin |
|
if (iWriteEnable) |
Ram[iWriteAddress] <= iDataIn; |
|
|
oDataOut0 <= Ram[iReadAddress0]; |
oDataOut1 <= Ram[iReadAddress1]; |
|
|
/* verilator lint_off WIDTH */ |
if (iWriteEnable) |
Ram[iWriteAddress] <= iDataIn; |
|
|
oDataOut0 <= Ram[iReadAddress0]; |
oDataOut1 <= Ram[iReadAddress1]; |
/* verilator lint_on WIDTH */ |
|
end |
endmodule |
//-------------------------------------------------------- |
53,27 → 55,27
|
module RAM_SINGLE_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 ) |
( |
input wire Clock, |
input wire iWriteEnable, |
input wire[ADDR_WIDTH-1:0] iReadAddress0, |
input wire[ADDR_WIDTH-1:0] iWriteAddress, |
input wire[DATA_WIDTH-1:0] iDataIn, |
output reg [DATA_WIDTH-1:0] oDataOut0 |
|
input wire Clock, |
input wire iWriteEnable, |
input wire[ADDR_WIDTH-1:0] iReadAddress0, |
input wire[ADDR_WIDTH-1:0] iWriteAddress, |
input wire[DATA_WIDTH-1:0] iDataIn, |
output reg [DATA_WIDTH-1:0] oDataOut0 |
|
); |
|
reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0]; |
reg [DATA_WIDTH-1:0] Ram [MEM_SIZE-1:0]; |
|
always @(posedge Clock) |
begin |
|
if (iWriteEnable) |
Ram[iWriteAddress] <= iDataIn; |
|
|
oDataOut0 <= Ram[iReadAddress0]; |
|
|
|
if (iWriteEnable) |
Ram[iWriteAddress] <= iDataIn; |
|
|
oDataOut0 <= Ram[iReadAddress0]; |
|
|
end |
endmodule |
|
/Module_InstructionDecode.v
22,31 → 22,30
|
module InstructionDecode |
( |
input wire Clock, |
input wire Reset, |
input wire iInstructionAvailable, |
input wire[`INSTRUCTION_WIDTH-1:0] iEncodedInstruction, |
input wire[`DATA_ROW_WIDTH-1:0] iRamValue0, |
input wire[`DATA_ROW_WIDTH-1:0] iRamValue1, |
output wire[`DATA_ADDRESS_WIDTH-1:0] oRamAddress0,oRamAddress1, |
output wire[`INSTRUCTION_OP_LENGTH-1:0] oOperation, |
output wire [`DATA_ROW_WIDTH-1:0] oSource0,oSource1, |
output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination, |
input wire Clock, |
input wire Reset, |
input wire iInstructionAvailable, |
input wire[`INSTRUCTION_WIDTH-1:0] iEncodedInstruction, |
input wire[`DATA_ROW_WIDTH-1:0] iRamValue0, |
input wire[`DATA_ROW_WIDTH-1:0] iRamValue1, |
output wire[`DATA_ADDRESS_WIDTH-1:0] oRamAddress0,oRamAddress1, |
output wire[`INSTRUCTION_OP_LENGTH-1:0] oOperation, |
output wire [`DATA_ROW_WIDTH-1:0] oSource0,oSource1, |
output wire [`DATA_ADDRESS_WIDTH-1:0] oDestination, |
input wire [`DATA_ROW_WIDTH-1:0] iDataForward, |
input wire [`DATA_ADDRESS_WIDTH-1:0] iLastDestination, |
|
`ifdef DEBUG |
input wire [`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP, |
output wire [`ROM_ADDRESS_WIDTH-1:0] oDebug_CurrentIP, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP, |
output wire [`ROM_ADDRESS_WIDTH-1:0] oDebug_CurrentIP, |
`endif |
|
//input wire [`ROM_ADDRESS_WIDTH-1:0] iIP, |
//output reg [`ROM_ADDRESS_WIDTH-1:0] oReturnAddress, |
|
output wire oDataReadyForExe |
|
); |
wire wInmediateOperand; |
wire [`DATA_ROW_WIDTH-1:0] wSource0,wSource1; |
wire [`DATA_ROW_WIDTH-1:0] wSource0,wSource1; |
wire wTriggerSource0DataForward,wTriggerSource1DataForward; |
wire wSource0AddrssEqualsLastDestination,wSource1AddrssEqualsLastDestination; |
|
88,48 → 87,31
//for execution |
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1 |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1), |
.D( iInstructionAvailable ), |
.Q( oDataReadyForExe ) |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable(1'b1), |
.D( iInstructionAvailable ), |
.Q( oDataReadyForExe ) |
); |
|
/* |
wire IsCall; |
assign IsCall = ( oOperation == `CALL ) ? 1'b1 : 1'b0; |
always @ (posedge IsCall) |
oReturnAddress <= iIP; |
*/ |
/* |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `ROM_ADDRESS_WIDTH ) FFRETURNADDR |
( |
.Clock( Clock ), |
.Reset( Reset ), |
.Enable( IsCall ), |
.D( iIP ), |
.Q( oReturnAddress ) |
); |
*/ |
|
|
//Latch the Operation |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFD3 |
( |
.Clock(Clock), |
.Reset(Reset), |
.Enable(iInstructionAvailable), |
.D(iEncodedInstruction[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]), |
.Q( oOperation ) |
.Clock(Clock), |
.Reset(Reset), |
.Enable(iInstructionAvailable), |
.D(iEncodedInstruction[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]), |
.Q( oOperation ) |
); |
//Latch the Destination |
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) FFD2 |
( |
.Clock(Clock), |
.Reset(Reset), |
.Enable(iInstructionAvailable), |
.D(iEncodedInstruction[47:32]), |
.Q(oDestination ) |
.Clock(Clock), |
.Reset(Reset), |
.Enable(iInstructionAvailable), |
.D(iEncodedInstruction[47:32]), |
.Q(oDestination ) |
); |
|
|
138,18 → 120,18
|
MUXFULLPARALELL_96bits_2SEL Source0_Mux |
( |
.Sel( wTriggerSource0DataForward ), |
.I1( wSource0 ), |
.I2( iDataForward ), |
.O1( oSource0 ) |
.Sel( wTriggerSource0DataForward ), |
.I1( wSource0 ), |
.I2( iDataForward ), |
.O1( oSource0 ) |
); |
|
MUXFULLPARALELL_96bits_2SEL Source1_Mux |
( |
.Sel( wTriggerSource1DataForward ), |
.I1( wSource1 ), |
.I2( iDataForward ), |
.O1( oSource1 ) |
.Sel( wTriggerSource1DataForward ), |
.I1( wSource1 ), |
.I2( iDataForward ), |
.O1( oSource1 ) |
); |
|
endmodule |
/Theia.v
27,26 → 27,26
module THEIA |
( |
|
input wire CLK_I, //Input clock |
input wire RST_I, //Input reset |
input wire CLK_I, //Input clock |
input wire RST_I, //Input reset |
//Theia Interfaces |
input wire MST_I, //Master signal, THEIA enters configuration mode |
input wire MST_I, //Master signal, THEIA enters configuration mode |
//when this gets asserted (see documentation) |
//Wish Bone Interface |
input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone) |
input wire ACK_I, //Input ack |
output wire ACK_O, //Output ack |
input wire [`WB_WIDTH-1:0] ADR_I, //Input address |
input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone) |
input wire ACK_I, //Input ack |
output wire ACK_O, //Output ack |
input wire [`WB_WIDTH-1:0] ADR_I, //Input address |
input wire WE_I, //Input write enable |
input wire STB_I, //Strobe signal, see wishbone documentation |
input wire STB_I, //Strobe signal, see wishbone documentation |
input wire CYC_I, //Bus cycle signal, see wishbone documentation |
input wire [1:0] TGA_I, //Input address tag, see THEAI documentation |
input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed) |
input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed) |
input wire [`MAX_CORES-1:0] RENDREN_I, |
|
input wire [`MAX_CORE_BITS-1:0] OMBSEL_I, //Output memory bank select |
input wire [`WB_WIDTH-1:0] OMADR_I, //Output adress (relative to current bank) |
output wire [`WB_WIDTH-1:0] OMEM_O, //Output data bus (Wishbone) |
output wire [`WB_WIDTH-1:0] OMEM_O, //Output data bus (Wishbone) |
|
input wire [`WB_WIDTH-1:0] TMDAT_I, |
input wire [`WB_WIDTH-1:0] TMADR_I, |
53,7 → 53,7
input wire TMWE_I, |
input wire [`MAX_TMEM_BANKS-1:0] TMSEL_I, |
//Control Register |
input wire [15:0] CREG_I, |
input wire [15:0] CREG_I, |
output wire HDL_O, |
input wire STDONE_I, |
input wire HDA_I, |
68,11 → 68,11
|
wire [`MAX_TMEM_BANKS-1:0] wTMemWriteEnable; |
SELECT_1_TO_N # ( `MAX_TMEM_BANKS, `MAX_TMEM_BANKS ) TMWE_SEL |
( |
.Sel(TMSEL_I), |
.En(TMWE_I), |
.O(wTMemWriteEnable) |
); |
( |
.Sel(TMSEL_I), |
.En(TMWE_I), |
.O(wTMemWriteEnable) |
); |
|
|
wire [`MAX_CORES-1:0] wDone; |
108,33 → 108,27
|
|
|
//CROSS-BAR cables |
//CROSS-BAR wires |
|
|
|
wire [`WB_WIDTH-1:0] wCrossBarDataRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank |
wire [`WB_WIDTH-1:0] wCrossBarDataCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. |
wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr). |
wire [`WB_WIDTH-1:0] wCrossBarAdressCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. (physical addr). |
wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank. |
|
wire wCORE_2_TMEM__Req[`MAX_CORES-1:0]; |
wire [`WB_WIDTH-1:0] wCrossBarDataRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank |
wire [`WB_WIDTH-1:0] wCrossBarDataCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. |
wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr). |
wire [`WB_WIDTH-1:0] wCrossBarAdressCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. (physical addr). |
wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank. |
wire wCORE_2_TMEM__Req[`MAX_CORES-1:0]; |
wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0]; |
|
|
wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0]; |
wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0]; |
wire wTMEM_2_Core__Grant[`MAX_CORES-1:0]; |
wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0]; |
wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0]; |
wire [`MAX_CORES-1:0] wHDL_O; |
wire [`MAX_CORES-1:0] wHostDataLatched; |
wire [`MAX_CORES-1:0] wRCOMMIT_O; |
wire [`MAX_CORES-1:0] wRCommited; |
|
wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0]; |
wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0]; |
wire [`MAX_CORES-1:0] wHDL_O; |
|
|
wire [`MAX_CORES-1:0] wHostDataLatched; |
wire [`MAX_CORES-1:0] wRCOMMIT_O; |
wire [`MAX_CORES-1:0] wRCommited; |
|
|
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3]; |
assign HDL_O = wHostDataLatched[0] & wHostDataLatched[1] & wHostDataLatched[2] & wHostDataLatched[3]; |
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3]; |
141,23 → 135,23
|
|
|
//---------------------------------------------------------------- |
//---------------------------------------------------------------- |
|
Module_BusArbitrer ARB1 |
( |
.Clock( CLK_I ), |
.Reset( RST_I ), |
.iRequest( wBusRequest ), |
.oGrant( wBusGranted ), |
.oBusSelect( wBusSelect ) |
|
); |
Module_BusArbitrer ARB1 |
( |
.Clock( CLK_I ), |
.Reset( RST_I ), |
.iRequest( wBusRequest ), |
.oGrant( wBusGranted ), |
.oBusSelect( wBusSelect ) |
|
); |
//---------------------------------------------------------------- |
|
wire wMaskedACK_O; |
assign wMaskedACK_O = (SEL_I & wACK_O) ? 1'b1 : 1'b0; |
assign ACK_O = ( MST_I ) ? wMaskedACK_O : wACK_O[ wBusSelect]; |
|
assign wMaskedACK_O = ( (SEL_I & wACK_O) != `MAX_CORES'b0) ? 1'b1 : 1'b0; |
assign ACK_O = ( MST_I ) ? wMaskedACK_O : wACK_O[ wBusSelect]; |
|
|
wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0]; |
assign OMEM_O = wDataOut[ OMBSEL_I ]; |
164,87 → 158,87
|
genvar i; |
generate |
for (i = 0; i < `MAX_CORES; i = i +1) |
begin : CORE |
assign wMST_I[i] = (SEL_I[i]) ? MST_I : 0; |
assign wSTB_I[i] = (SEL_I[i]) ? STB_I : 0; |
assign wCYC_I[i] = (SEL_I[i]) ? CYC_I : 0; |
assign wTGA_I[i] = (SEL_I[i]) ? TGA_I : 0; |
for (i = 0; i < `MAX_CORES; i = i +1) |
begin : CORE |
assign wMST_I[i] = (SEL_I[i]) ? MST_I : 0; |
assign wSTB_I[i] = (SEL_I[i]) ? STB_I : 0; |
assign wCYC_I[i] = (SEL_I[i]) ? CYC_I : 0; |
assign wTGA_I[i] = (SEL_I[i]) ? TGA_I : 0; |
|
|
THEIACORE CTHEIA |
( |
.CLK_I( CLK_I ), |
.RST_I( RST_I ), |
.RENDREN_I( RENDREN_I[i] ), |
|
//Slave signals |
.ADR_I( ADR_I ), |
.WE_I( WE_I ), |
.STB_I( wSTB_I[i] ), |
.ACK_I( ACK_I ), |
.CYC_I( wCYC_I[i] ), |
.MST_I( wMST_I[i] ), |
.TGA_I( wTGA_I[i] ), |
.CREG_I( CREG_I ), |
|
//Master Signals |
.ACK_O( wACK_O[i] ), |
.CYC_O( wBusRequest[i] ), |
.GNT_I( wBusGranted[i] ), |
`ifdef DEBUG |
.iDebug_CoreID( i ), |
`endif |
|
.OMEM_WE_O( wOMem_WE[i] ), |
.OMEM_ADR_O( wOMEM_Address[i] ), |
.OMEM_DAT_O( wOMEM_Dat[i] ), |
|
.TMEM_DAT_I( wCrossBarDataCollumn[i] ), |
.TMEM_ADR_O( wTMemReadAdr[i] ), |
.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ), |
.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ), |
|
.HDA_I( HDA_I ), //Host data available |
.HDL_O( wHDL_O[i] ), //Host data Latched |
.HDLACK_I( ~HDL_O ), //Host data Latched ACK |
.STDONE_I( STDONE_I ), |
.RCOMMIT_O( wRCOMMIT_O[i] ), |
|
|
//Other |
.DAT_I( DAT_I ), |
.DONE_O( wDone[i] ) |
|
THEIACORE CTHEIA |
( |
.CLK_I( CLK_I ), |
.RST_I( RST_I ), |
.RENDREN_I( RENDREN_I[i] ), |
|
//Slave signals |
.ADR_I( ADR_I ), |
.WE_I( WE_I ), |
.STB_I( wSTB_I[i] ), |
.ACK_I( ACK_I ), |
.CYC_I( wCYC_I[i] ), |
.MST_I( wMST_I[i] ), |
.TGA_I( wTGA_I[i] ), |
.CREG_I( CREG_I ), |
|
//Master Signals |
.ACK_O( wACK_O[i] ), |
.CYC_O( wBusRequest[i] ), |
.GNT_I( wBusGranted[i] ), |
`ifdef DEBUG |
.iDebug_CoreID( i ), |
`endif |
|
.OMEM_WE_O( wOMem_WE[i] ), |
.OMEM_ADR_O( wOMEM_Address[i] ), |
.OMEM_DAT_O( wOMEM_Dat[i] ), |
|
.TMEM_DAT_I( wCrossBarDataCollumn[i] ), |
.TMEM_ADR_O( wTMemReadAdr[i] ), |
.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ), |
.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ), |
|
.HDA_I( HDA_I ), //Host data available |
.HDL_O( wHDL_O[i] ), //Host data Latched |
.HDLACK_I( ~HDL_O ), //Host data Latched ACK |
.STDONE_I( STDONE_I ), |
.RCOMMIT_O( wRCOMMIT_O[i] ), |
|
|
//Other |
.DAT_I( DAT_I ), |
.DONE_O( wDone[i] ) |
|
); |
|
UPCOUNTER_POSEDGE # (1) UP_RCOMMIT |
( |
.Clock( CLK_I ), |
.Reset( RST_I | HDLACK_I ), |
.Initial( 1'b0 ), |
.Enable( wRCOMMIT_O[i] ), |
.Q(wRCommited[i]) |
); |
|
UPCOUNTER_POSEDGE # (1) UP_GREADY |
( |
.Clock( CLK_I ), |
.Reset( RST_I | HDLACK_I ), |
.Initial( 1'b0 ), |
.Enable( wHDL_O[i] ), |
.Q(wHostDataLatched[i]) |
); |
); |
|
UPCOUNTER_POSEDGE # (1) UP_RCOMMIT |
( |
.Clock( CLK_I ), |
.Reset( RST_I | HDLACK_I ), |
.Initial( 1'b0 ), |
.Enable( wRCOMMIT_O[i] ), |
.Q(wRCommited[i]) |
); |
|
UPCOUNTER_POSEDGE # (1) UP_GREADY |
( |
.Clock( CLK_I ), |
.Reset( RST_I | HDLACK_I ), |
.Initial( 1'b0 ), |
.Enable( wHDL_O[i] ), |
.Q(wHostDataLatched[i]) |
); |
|
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 250000 ) OMEM //500000 ) OMEM |
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 250000 ) OMEM //500000 ) OMEM |
( |
.Clock( CLK_I ), |
.iWriteEnable( wOMem_WE[i] ), |
.iWriteAddress( wOMEM_Address[i] ), |
.iDataIn( wOMEM_Dat[i] ), |
.iReadAddress0( OMADR_I ), |
.oDataOut0( wDataOut[i] ) |
|
.Clock( CLK_I ), |
.iWriteEnable( wOMem_WE[i] ), |
.iWriteAddress( wOMEM_Address[i] ), |
.iDataIn( wOMEM_Dat[i] ), |
.iReadAddress0( OMADR_I ), |
.oDataOut0( wDataOut[i] ) |
|
); |
|
|
257,11 → 251,11
//be 1 at any given point in time. All bits zero means, |
//we are not requesting to read from any memory bank. |
SELECT_1_TO_N # ( `WIDTH, `MAX_CORES ) READDRQ |
( |
.Sel(wCoreBankSelect[ i]), |
.En(wCORE_2_TMEM__Req[i]), |
.O(wBankReadRequest[i]) |
); |
( |
.Sel(wCoreBankSelect[ i]), |
.En(wCORE_2_TMEM__Req[i]), |
.O(wBankReadRequest[i]) |
); |
|
//The address coming from the core is virtual adress, meaning it assumes linear |
//address space, however, since memory is interleaved in a n-way memory we transform |
270,13 → 264,13
|
assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> `MAX_CORE_BITS); |
|
//Connect the granted signal to Arbiter of the Bank we want to read from |
//Connect the granted signal to Arbiter of the Bank we want to read from |
assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i]; |
|
//Connect the request signal to Arbiter of the Bank we want to read from |
//Connect the request signal to Arbiter of the Bank we want to read from |
//assign wBankReadRequest[wCoreBankSelect[i]][i] = wCORE_2_TMEM__Req[i]; |
|
end |
end |
endgenerate |
|
|
287,55 → 281,55
for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1) |
begin : BANK |
|
//The memory bank itself |
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM |
( |
.Clock( CLK_I ), |
.iWriteEnable( wTMemWriteEnable[Bank] ), |
.iWriteAddress( TMADR_I ), |
.iDataIn( TMDAT_I ), |
.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid |
.oDataOut0( wCrossBarDataRow[Bank] ) //Connect to the Row of the grid |
|
); |
|
//Arbiter will Round-Robin Cores attempting to read from the same Bank |
//at a given point in time |
//The memory bank itself |
RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM |
( |
.Clock( CLK_I ), |
.iWriteEnable( wTMemWriteEnable[Bank] ), |
.iWriteAddress( TMADR_I ), |
.iDataIn( TMDAT_I ), |
.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid |
.oDataOut0( wCrossBarDataRow[Bank] ) //Connect to the Row of the grid |
|
); |
|
//Arbiter will Round-Robin Cores attempting to read from the same Bank |
//at a given point in time |
wire [`MAX_CORES-1:0] wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0]; |
Module_BusArbitrer ARB_TMEM |
( |
.Clock( CLK_I ), |
.Reset( RST_I ), |
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}), |
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank |
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank |
|
); |
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_CORES ) FFD_GNT |
Module_BusArbitrer ARB_TMEM |
( |
.Clock( CLK_I ), |
.Reset( RST_I ), |
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}), |
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank |
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank |
|
); |
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_CORES ) FFD_GNT |
( |
.Clock(CLK_I), |
.Reset(RST_I), |
.Enable( 1'b1 ), |
.D(wBankReadGrantedDelay[Bank]), |
.Q(wBankReadGranted[Bank]) |
.Clock(CLK_I), |
.Reset(RST_I), |
.Enable( 1'b1 ), |
.D(wBankReadGrantedDelay[Bank]), |
.Q(wBankReadGranted[Bank]) |
); |
|
|
//Create the Cross-Bar interconnection grid now, rows are coonected to the memory banks, |
//while collumns are connected to the cores, 2 or more cores can not read from the same |
//bank at any given point in time |
for (Core = 0; Core < `MAX_CORES; Core = Core + 1) |
begin: CORE_CONNECT |
`ifndef VERILATOR |
//Connect the Data Collum of this core to the Data Row of current bank, only if the Core is looking for data stored in this bank |
assign wCrossBarDataCollumn[ Core ] = ( wCoreBankSelect[ Core ] == Bank ) ? wCrossBarDataRow[ Bank ] : `WB_WIDTH'bz; |
//Connect the Address Row of this Bank to the Address Column of the core, only if the Arbiter selected this core for reading |
assign wCrossBarAddressRow[ Bank ] = ( wCurrentCoreSelected[ Bank ] == Core ) ? wCrossBarAdressCollumn[Core]: `WB_WIDTH'bz; |
`endif |
|
end |
|
|
//Create the Cross-Bar interconnection grid now, rows are coonected to the memory banks, |
//while collumns are connected to the cores, 2 or more cores can not read from the same |
//bank at any given point in time |
for (Core = 0; Core < `MAX_CORES; Core = Core + 1) |
begin: CORE_CONNECT |
`ifndef VERILATOR |
//Connect the Data Collum of this core to the Data Row of current bank, only if the Core is looking for data stored in this bank |
assign wCrossBarDataCollumn[ Core ] = ( wCoreBankSelect[ Core ] == Bank ) ? wCrossBarDataRow[ Bank ] : `WB_WIDTH'bz; |
//Connect the Address Row of this Bank to the Address Column of the core, only if the Arbiter selected this core for reading |
assign wCrossBarAddressRow[ Bank ] = ( wCurrentCoreSelected[ Bank ] == Core ) ? wCrossBarAdressCollumn[Core]: `WB_WIDTH'bz; |
`endif |
|
end |
|
end |
endgenerate |
|
/Module_ROM.v
235,7 → 235,7
66: I = { `RETURN ,`RT_TRUE }; |
|
//LABEL_ALLDONE: |
67: I = { `NOP ,`VOID ,`VOID }; |
67: I = { `NOP ,`RT_FALSE }; |
68: I = { `RETURN ,`RT_FALSE }; |
|
//---------------------------------------------------------------------- |
/Collaterals.v
22,23 → 22,7
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
|
***********************************************************************************/ |
//------------------------------------------------ |
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH ) |
( |
input wire Clock, |
input wire Clear, |
input wire [SIZE-1:0] D, |
output reg [SIZE-1:0] Q |
); |
|
always @(posedge Clock or posedge Clear) |
begin |
if (Clear) |
Q = 0; |
else |
Q = D; |
end |
endmodule |
|
//---------------------------------------------------- |
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH ) |
( |
53,7 → 37,7
always @ (posedge Clock) |
begin |
if ( Reset ) |
Q <= `WIDTH'b0; |
Q <= {SIZE{1'b0}}; |
else |
begin |
if (Enable) |
133,7 → 117,7
2'b01: O1 = I2; |
2'b10: O1 = I3; |
2'b11: O1 = I4; |
default: O1 = SIZE-1'b0; |
default: O1 = SIZE; |
|
endcase |
|
192,8 → 176,8
|
3'b001: O1 = I1; |
3'b010: O1 = I2; |
3'b100: O1 = I3; |
default: O1 = SIZE-1'b0; |
3'b100: O1 = I3; |
default: O1 = SIZE; |
|
endcase |
|