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URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

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  • This comparison shows the changes necessary to convert path 
    /theia_gpu/branches/icarus_version
    from Rev 177 to Rev 178
    ↔ Reverse comparison
  •

Rev 177 → Rev 178

/rtl/Module_ExecutionFSM.v
93,10 → 93,10
 
//Don't allow me to write back back if the operation is a NOP
`ifdef DEBUG
assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
assign oRAMWriteEnable = iALUOutputReady && (!wOperationIsJump || oALUOperation == `RET ) &&
(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
`else
assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
assign oRAMWriteEnable = iALUOutputReady && (!wOperationIsJump || oALUOperation == `RET) && oALUOperation != `NOP;
`endif
 
 
359,7 → 359,8
`MULP: `LOGME"MULP");
`XCHANGEX: `LOGME"XCHANGEX");
`IMUL: `LOGME"IMUL");
`UNSCALE: `LOGME"UNSCALE");
`UNSCALE: `LOGME"UNSCALE");
`RESCALE: `LOGME"UNSCALE");
`INCX: `LOGME"INCX");
`INCY: `LOGME"INCY");
`INCZ: `LOGME"INCZ");
/rtl/Module_Host.v
61,6 → 61,9
`define HOST_GET_PRIMITIVE_COUNT 16
`define HOST_LAST_PRIMITIVE_REACHED 17
`define HOST_GPU_EXECUTION_DONE 18
`define HOST_PREPARE_BROADCAST_CREG_MAX_PRIMITIVES 19
`define HOST_BROADCAST_CREG_MAX_PRIMITIVES 20
`define HOST_WAIT_CREG_MAX_PRIMITIVES 21
 
//---------------------------------------------------------------
module Module_Host
93,9 → 96,10
output wire STDONE_O,
output reg oHostDataAvailable,
input wire iGPUDone,
`ifndef NO_DISPLAY_STATS
input wire [`WIDTH-1:0] iDebugWidth,
`endif
output reg oRenderDone,
input wire [`WIDTH-1:0] iWidth,iHeight,
 
input wire ACK_I
);
247,6 → 251,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if ( ~Reset & iEnable )
begin
281,7 → 286,8
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_WAIT_INSTRUCTION;
end
303,6 → 309,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if ( wWBMDone && ~wLastValidReadAddress )
rHostNextState = `HOST_WRITE_INSTRUCTION;
333,6 → 340,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
$display("-I- HOST: Configuring Core Mask %b\n",oCoreSelectMask);
`ifndef VERILATOR
362,6 → 370,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_WAIT_SCENE_PARAMS;
end
382,6 → 391,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if ( wWBMDone && ~wLastParameter )
rHostNextState = `HOST_WRITE_SCENE_PARAMS;
413,6 → 423,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
436,6 → 447,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_WAIT_CORE_CONFIG;
end
457,6 → 469,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if (wWBMDone && ((oReadAddress % 2) == `WB_WIDTH'b0))
488,13 → 501,83
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if (wLastCoreSelected)//wCoreSelect[`MAX_CORES-1] == 1)
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
if (wLastCoreSelected)
rHostNextState = `HOST_PREPARE_BROADCAST_CREG_MAX_PRIMITIVES;
else
rHostNextState = `HOST_UNICAST_CORE_CONFIG;
end
//----------------------------------------
`HOST_PREPARE_BROADCAST_CREG_MAX_PRIMITIVES:
begin
rWBMEnable = 0; //Do not enable until we are resquested
rInitiaReadAddr = 32'd6; //Start reading from here, it has the # of primites
rWBMReset = 1; //Tell WBM to start reading from the addr bellow
oMemSelect = `SELECT_GEO_MEM; //We are reading from the geometry memory
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
MST_O = 0; //Keep master signal in 0 for now
rInitialWriteAddress = {16'b0,`CREG_MAX_PRIMITIVES}; //The address from which to start wrting @ the cores
rSetWriteAddr = 1; //Set to use the initial write address bellow
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0; //Set to unicast to the next core
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_BROADCAST_CREG_MAX_PRIMITIVES;
end
//----------------------------------------
`HOST_BROADCAST_CREG_MAX_PRIMITIVES:
begin
rWBMEnable = 1;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_WAIT_CREG_MAX_PRIMITIVES;
end
//----------------------------------------
`HOST_WAIT_CREG_MAX_PRIMITIVES:
begin
rWBMEnable = ~wWBMDone;
rInitiaReadAddr = 0;
rWBMReset = 0;
oMemSelect = `SELECT_GEO_MEM;
TGA_O = `TAG_DATA_ADDRESS_TYPE;
MST_O = 1;
rInitialWriteAddress = 0;
rSetWriteAddr = 0;
oCoreSelectMask = `SELECT_ALL_CORES;
rIncCoreSelect = 0;
RENDREN_O = 0;
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if (wWBMDone )
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
else
rHostNextState = `HOST_WAIT_CREG_MAX_PRIMITIVES;
end
//----------------------------------------
/*
Prepare the write address for the next primitive.
515,8 → 598,9
rResetVertexCount = 1;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if (wGPUDone)
if (RenderedPixels >= (iWidth*iHeight))//(wGPUDone)
rHostNextState = `HOST_GPU_EXECUTION_DONE;
else
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
539,6 → 623,7
rResetVertexCount = 0;
GACK_O = 1;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
566,6 → 651,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_WAIT_FOR_VERTEX;
588,6 → 674,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
if (wWBMDone & ~wLastVertexInFrame )
615,6 → 702,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;//1;
oRenderDone = 0;
if (wVertexCount >= iPrimitiveCount)
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
644,6 → 732,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 1;
oRenderDone = 0;
if ( iHostDataReadConfirmed )
rHostNextState = `HOST_ACK_GEO_REQUEST;
667,6 → 756,7
rResetVertexCount = 0; //Reset the vertex count to zero
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
 
684,14 → 774,14
RenderedPixels = RenderedPixels + `MAX_CORES;
/* verilator lint_off WIDTH */
if ( RenderedPixels % iDebugWidth == 0)
if ( RenderedPixels % iWidth == 0)
begin
$write("]%d\n[",RenderedPixels / iDebugWidth);
$write("]%d\n[",RenderedPixels / iWidth);
`ifndef VERILATOR
$fflush;
`endif
`ifndef VERILATOR
$fflush;
`endif
end
/* verilator lint_on WIDTH */
706,7 → 796,7
//----------------------------------------
`HOST_GPU_EXECUTION_DONE:
begin
$display("THEIA Execution done in %xns\n",$time-StartTime);
$display("THEIA Execution done in %dns\n",$time-StartTime);
rWBMEnable = 0;
rInitiaReadAddr = 0;
rWBMReset = 0;
721,6 → 811,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 1;
rHostNextState = `HOST_GPU_EXECUTION_DONE;
end
742,6 → 833,7
rResetVertexCount = 0;
GACK_O = 0;
oHostDataAvailable = 0;
oRenderDone = 0;
rHostNextState = `HOST_IDLE;
end
/rtl/top.v
56,12 → 56,14
input wire [`WB_WIDTH-1:0] iOMEMReadAddress,
output wire [`WB_WIDTH-1:0] oOMEMData, //Output data bus (Wishbone)
`ifndef NO_DISPLAY_STATS
input wire [`WIDTH-1:0] iDebugWidth,
input wire [`WIDTH-1:0] iWidth,iHeight,
`endif
output wire oDone
 
 
);
wire wHost_2__RenderDone;
assign oDone = wHost_2__RenderDone;
 
assign oMemSelect = wMemSelect;
 
83,7 → 85,7
wire wHostDataAvailable;
wire wHost_2__CYC_O,wHost_2__GACK_O,TGC_O,wHost_2__STB_O;
 
assign oDone = wGPU_2_HOST_Done;
//assign oDone = wGPU_2_HOST_Done;
 
THEIA GPU
(
146,11 → 148,12
.iGPUCommitedResults( wGPUCommitedResults ),
.STDONE_O( wHost_2__STDONE ),
.iGPUDone( wGPU_2_HOST_Done ),
.oRenderDone( wHost_2__RenderDone ),
`ifndef NO_DISPLAY_STATS
.iDebugWidth(iDebugWidth),
`endif
 
.iWidth(iWidth),
.iHeight(iHeight),
 
//To Memory
.oReadAddress( oHostReadAddress ),
.iReadData( wHostReadData ),
/rtl/Module_VectorALU.v
947,6 → 947,7
//Set Operations
`UNSCALE: ResultA = iChannel_Ax >> `SCALE;
`RESCALE: ResultA = iChannel_Ax << `SCALE;
`SETX,`RET: ResultA = iChannel_Ax;
`SETY: ResultA = iChannel_Bx;
`SETZ: ResultA = iChannel_Bx;
989,6 → 990,7
//Set Operations
`UNSCALE: ResultB = iChannel_Ay >> `SCALE;
`RESCALE: ResultB = iChannel_Ay << `SCALE;
`SETX,`RET: ResultB = iChannel_By; // {Source1[95:64],Source0[63:32],Source0[31:0]};
`SETY: ResultB = iChannel_Ax; // {Source0[95:64],Source1[95:64],Source0[31:0]};
`SETZ: ResultB = iChannel_By; // {Source0[95:64],Source0[63:32],Source1[95:64]};
1036,6 → 1038,7
//Set Operations
`UNSCALE: ResultC = iChannel_Az >> `SCALE;
`RESCALE: ResultC = iChannel_Az << `SCALE;
`SETX,`RET: ResultC = iChannel_Bz; // {Source1[95:64],Source0[63:32],Source0[31:0]};
`SETY: ResultC = iChannel_Bz; // {Source0[95:64],Source1[95:64],Source0[31:0]};
`SETZ: ResultC = iChannel_Ax; // {Source0[95:64],Source0[63:32],Source1[95:64]};
1243,7 → 1246,7
always @ ( * )
begin
case ( wOperation )
`UNSCALE: OutputReady = wOutputDelay1Cycle;
`UNSCALE,`RESCALE: OutputReady = wOutputDelay1Cycle;
`RETURN: OutputReady = wOutputDelay1Cycle;
`NOP: OutputReady = wOutputDelay1Cycle;
/rtl/aDefinitions.v
1,372 → 1,374
/**********************************************************************************
Theaia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2009 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
 
/*******************************************************************************
Module Description:
 
This module defines constants that are going to be used
all over the code. By now you have may noticed that all
constants are pre-compilation define directives. This is
for simulation perfomance reasons mainly.
*******************************************************************************/
//`define VERILATOR 1
/**********************************************************************************
Theaia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2009 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
 
/*******************************************************************************
Module Description:
 
This module defines constants that are going to be used
all over the code. By now you have may noticed that all
constants are pre-compilation define directives. This is
for simulation perfomance reasons mainly.
*******************************************************************************/
//`define VERILATOR 1
`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
`define MAX_TMEM_BANKS 8 //The number of memory banks for TMEM
`define MAX_TMEM_BITS 3 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
//---------------------------------------------------------------------------------
//Verilog provides a `default_nettype none compiler directive. When
//this directive is set, implicit data types are disabled, which will make any
//undeclared signal name a syntax error.This is very usefull to avoid annoying
//automatic 1 bit long wire declaration where you don't want them to be!
`default_nettype none
 
//The clock cycle
`define CLOCK_CYCLE 5
`define CLOCK_PERIOD 10
//---------------------------------------------------------------------------------
//Defines the Scale. This very important because it sets the fixed point precision.
//The Scale defines the number bits that are used as the decimal part of the number.
//The code has been written in such a way that allows you to change the value of the
//Scale, so that it is possible to experiment with different scenarios. SCALE can be
//no smaller that 1 and no bigger that WIDTH.
`define SCALE 17
 
//The next section defines the length of the registers, buses and other structures,
//do not change this valued unless you really know what you are doing (seriously!)
`define WIDTH 32
`define WB_WIDTH 32 //width of wish-bone buses
`define LONG_WIDTH 64
 
`define WB_SIMPLE_READ_CYCLE 0
`define WB_SIMPLE_WRITE_CYCLE 1
//---------------------------------------------------------------------------------
//Next are the constants that define the size of the instructions.
//instructions are formed like this:
// Tupe I:
// Operand (of size INSTRUCTION_OP_LENGTH )
// DestinationAddr (of size DATA_ADDRESS_WIDTH )
// SourceAddrr1 (of size DATA_ADDRESS_WIDTH )
// SourceAddrr2 (of size DATA_ADDRESS_WIDTH )
//Type II:
// Operand (of size INSTRUCTION_OP_LENGTH )
// DestinationAddr (of size DATA_ADDRESS_WIDTH )
`define MAX_TMEM_BITS 3 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
//---------------------------------------------------------------------------------
//Verilog provides a `default_nettype none compiler directive. When
//this directive is set, implicit data types are disabled, which will make any
//undeclared signal name a syntax error.This is very usefull to avoid annoying
//automatic 1 bit long wire declaration where you don't want them to be!
`default_nettype none
 
//The clock cycle
`define CLOCK_CYCLE 5
`define CLOCK_PERIOD 10
//---------------------------------------------------------------------------------
//Defines the Scale. This very important because it sets the fixed point precision.
//The Scale defines the number bits that are used as the decimal part of the number.
//The code has been written in such a way that allows you to change the value of the
//Scale, so that it is possible to experiment with different scenarios. SCALE can be
//no smaller that 1 and no bigger that WIDTH.
`define SCALE 17
 
//The next section defines the length of the registers, buses and other structures,
//do not change this valued unless you really know what you are doing (seriously!)
`define WIDTH 32
`define WB_WIDTH 32 //width of wish-bone buses
`define LONG_WIDTH 64
 
`define WB_SIMPLE_READ_CYCLE 0
`define WB_SIMPLE_WRITE_CYCLE 1
//---------------------------------------------------------------------------------
//Next are the constants that define the size of the instructions.
//instructions are formed like this:
// Tupe I:
// Operand (of size INSTRUCTION_OP_LENGTH )
// DestinationAddr (of size DATA_ADDRESS_WIDTH )
// SourceAddrr1 (of size DATA_ADDRESS_WIDTH )
// SourceAddrr2 (of size DATA_ADDRESS_WIDTH )
//Type II:
// Operand (of size INSTRUCTION_OP_LENGTH )
// DestinationAddr (of size DATA_ADDRESS_WIDTH )
// InmeadiateValue (of size WIDTH = DATA_ADDRESS_WIDTH * 2 )
//
//You can play around with the size of instuctions, but keep
//in mind that Bits 3 and 4 of the Operand have a special meaning
//that is used for the jump familiy of instructions (see Documentation).
//Also the MSB of Operand is used by the decoder to distinguish
//between Type I and Type II instructions.
`define INSTRUCTION_WIDTH 64
`define INSTRUCTION_OP_LENGTH 16
`define INSTRUCTION_IMM_BITPOS 54
`define INSTRUCTION_IMM_BIT 6 //don't change this!
 
//Defines the Lenght of Memory blocks
`define DATA_ROW_WIDTH 96
`define DATA_ADDRESS_WIDTH 16
`define ROM_ADDRESS_WIDTH 16
`define ROM_ADDRESS_SEL_MASK `ROM_ADDRESS_WIDTH'h8000
 
//---------------------------------------------------------------------------------
//The next section defines the code memory entry point for the various code routines
//Please keep this syntax ENTRYPOINT_ADDR_* because the perl script that
//parses the user code expects this pattern in order to read in the tokens
 
//Internal Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd44
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd47
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd69
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd157
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd232
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd248
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd190
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd55
//User Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd276
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd278
`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd37
 
//Please keep this syntax ENTRYPOINT_INDEX_* because the perl script that
//parses the user code expects this pattern in order to read in the tokens
//Internal subroutines
`define ENTRYPOINT_INDEX_INITIAL `ROM_ADDRESS_WIDTH'h8000
`define ENTRYPOINT_INDEX_CPPU `ROM_ADDRESS_WIDTH'h8001
`define ENTRYPOINT_INDEX_RGU `ROM_ADDRESS_WIDTH'h8002
`define ENTRYPOINT_INDEX_AABBIU `ROM_ADDRESS_WIDTH'h8003
`define ENTRYPOINT_INDEX_BIU `ROM_ADDRESS_WIDTH'h8004
`define ENTRYPOINT_INDEX_PSU `ROM_ADDRESS_WIDTH'h8005
`define ENTRYPOINT_INDEX_PSU2 `ROM_ADDRESS_WIDTH'h8006
`define ENTRYPOINT_INDEX_TCC `ROM_ADDRESS_WIDTH'h8007
`define ENTRYPOINT_INDEX_NPG `ROM_ADDRESS_WIDTH'h8008
//User defined subroutines
`define ENTRYPOINT_INDEX_USERCONSTANTS `ROM_ADDRESS_WIDTH'h8009
//
//You can play around with the size of instuctions, but keep
//in mind that Bits 3 and 4 of the Operand have a special meaning
//that is used for the jump familiy of instructions (see Documentation).
//Also the MSB of Operand is used by the decoder to distinguish
//between Type I and Type II instructions.
`define INSTRUCTION_WIDTH 64
`define INSTRUCTION_OP_LENGTH 16
`define INSTRUCTION_IMM_BITPOS 54
`define INSTRUCTION_IMM_BIT 6 //don't change this!
 
//Defines the Lenght of Memory blocks
`define DATA_ROW_WIDTH 96
`define DATA_ADDRESS_WIDTH 16
`define ROM_ADDRESS_WIDTH 16
`define ROM_ADDRESS_SEL_MASK `ROM_ADDRESS_WIDTH'h8000
 
//---------------------------------------------------------------------------------
//The next section defines the code memory entry point for the various code routines
//Please keep this syntax ENTRYPOINT_ADDR_* because the perl script that
//parses the user code expects this pattern in order to read in the tokens
 
//Internal Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd70
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd74
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd98
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd186
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd264
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd280
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd222
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd82
//User Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd308
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd310
`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd37
 
//Please keep this syntax ENTRYPOINT_INDEX_* because the perl script that
//parses the user code expects this pattern in order to read in the tokens
//Internal subroutines
`define ENTRYPOINT_INDEX_INITIAL `ROM_ADDRESS_WIDTH'h8000
`define ENTRYPOINT_INDEX_CPPU `ROM_ADDRESS_WIDTH'h8001
`define ENTRYPOINT_INDEX_RGU `ROM_ADDRESS_WIDTH'h8002
`define ENTRYPOINT_INDEX_AABBIU `ROM_ADDRESS_WIDTH'h8003
`define ENTRYPOINT_INDEX_BIU `ROM_ADDRESS_WIDTH'h8004
`define ENTRYPOINT_INDEX_PSU `ROM_ADDRESS_WIDTH'h8005
`define ENTRYPOINT_INDEX_PSU2 `ROM_ADDRESS_WIDTH'h8006
`define ENTRYPOINT_INDEX_TCC `ROM_ADDRESS_WIDTH'h8007
`define ENTRYPOINT_INDEX_NPG `ROM_ADDRESS_WIDTH'h8008
//User defined subroutines
`define ENTRYPOINT_INDEX_USERCONSTANTS `ROM_ADDRESS_WIDTH'h8009
`define ENTRYPOINT_INDEX_PIXELSHADER `ROM_ADDRESS_WIDTH'h800A
`define ENTRYPOINT_INDEX_MAIN `ROM_ADDRESS_WIDTH'h800B
 
`define USER_AABBIU_UCODE_ADDRESS `ROM_ADDRESS_WIDTH'b1000000000000000
//---------------------------------------------------------------------------------
//This handy little macro allows me to print stuff either to STDOUT or a file.
//Notice that the compilation vairable DUMP_CODE must be set if you want to print
//to a file. In XILINX right click 'Simulate Beahvioral Model' -> Properties and
//under 'Specify `define macro name and value' type 'DEBUG=1|DUMP_CODE=1|DEBUG_CORE=<core you want to dump>'
`ifdef DUMP_CODE
`define LOGME $fwrite(ucode_file,
`else
`define LOGME $write(
`endif
`define ENTRYPOINT_INDEX_MAIN `ROM_ADDRESS_WIDTH'h800B
 
`define USER_AABBIU_UCODE_ADDRESS `ROM_ADDRESS_WIDTH'b1000000000000000
//---------------------------------------------------------------------------------
//This handy little macro allows me to print stuff either to STDOUT or a file.
//Notice that the compilation vairable DUMP_CODE must be set if you want to print
//to a file. In XILINX right click 'Simulate Beahvioral Model' -> Properties and
//under 'Specify `define macro name and value' type 'DEBUG=1|DUMP_CODE=1|DEBUG_CORE=<core you want to dump>'
`ifdef DUMP_CODE
`define LOGME $fwrite(ucode_file,
`else
`define LOGME $write(
`endif
//---------------------------------------------------------------------------------
`define TRUE 32'h1
`define FALSE 32'h0
`define RT_TRUE 48'b1
`define RT_FALSE 48'b0
//---------------------------------------------------------------------------------
 
`define GENERAL_PURPOSE_REG_ADDR_MASK `DATA_ADDRESS_WIDTH'h1F
`define VOID `DATA_ADDRESS_WIDTH'd0 //0000
//** Control register bits **//
`define CR_EN_LIGHTS 0
`define CR_EN_TEXTURE 1
`define CR_USER_AABBIU 2
/** Swapping registers **/
//** Configuration Registers **//
`define CREG_LIGHT_INFO `DATA_ADDRESS_WIDTH'd0
`define CREG_CAMERA_POSITION `DATA_ADDRESS_WIDTH'd1
`define CREG_PROJECTION_WINDOW_MIN `DATA_ADDRESS_WIDTH'd2
`define CREG_PROJECTION_WINDOW_MAX `DATA_ADDRESS_WIDTH'd3
`define CREG_RESOLUTION `DATA_ADDRESS_WIDTH'd4
`define CREG_TEXTURE_SIZE `DATA_ADDRESS_WIDTH'd5
`define CREG_PIXEL_2D_INITIAL_POSITION `DATA_ADDRESS_WIDTH'd6
`define CREG_PIXEL_2D_FINAL_POSITION `DATA_ADDRESS_WIDTH'd7
`define CREG_FIRST_LIGTH `DATA_ADDRESS_WIDTH'd8
`define CREG_FIRST_LIGTH_DIFFUSE `DATA_ADDRESS_WIDTH'd8
//OK, so from address 0x06 to 0x0F is where the lights are,watch out values are harcoded
//for now!! (look in ROM.v for hardcoded values!!!)
 
 
//Don't change the order of the registers. CREG_V* and CREG_UV* registers
//need to be in that specific order for the triangle fetcher to work
//correctly!
 
`define CREG_AABBMIN `DATA_ADDRESS_WIDTH'd42
`define CREG_AABBMAX `DATA_ADDRESS_WIDTH'd43
`define CREG_V0 `DATA_ADDRESS_WIDTH'd44
`define CREG_UV0 `DATA_ADDRESS_WIDTH'd45
`define CREG_V1 `DATA_ADDRESS_WIDTH'd46
`define CREG_UV1 `DATA_ADDRESS_WIDTH'd47
`define CREG_V2 `DATA_ADDRESS_WIDTH'd48
`define CREG_UV2 `DATA_ADDRESS_WIDTH'd49
`define CREG_TRI_DIFFUSE `DATA_ADDRESS_WIDTH'd50
`define CREG_TEX_COLOR1 `DATA_ADDRESS_WIDTH'd53
`define CREG_TEX_COLOR2 `DATA_ADDRESS_WIDTH'd54
`define CREG_TEX_COLOR3 `DATA_ADDRESS_WIDTH'd55
`define CREG_TEX_COLOR4 `DATA_ADDRESS_WIDTH'd56
`define CREG_TEX_COLOR5 `DATA_ADDRESS_WIDTH'd57
`define CREG_TEX_COLOR6 `DATA_ADDRESS_WIDTH'd58
`define CREG_TEX_COLOR7 `DATA_ADDRESS_WIDTH'd59
 
 
/** Non-Swapping registers **/
// ** User Registers **//
//General Purpose registers, the user may put what ever he/she
//wants in here...
`define C1 `DATA_ADDRESS_WIDTH'd64
`define C2 `DATA_ADDRESS_WIDTH'd65
`define C3 `DATA_ADDRESS_WIDTH'd66
`define C4 `DATA_ADDRESS_WIDTH'd67
`define C5 `DATA_ADDRESS_WIDTH'd68
`define C6 `DATA_ADDRESS_WIDTH'd69
`define C7 `DATA_ADDRESS_WIDTH'd70
`define R1 `DATA_ADDRESS_WIDTH'd71
`define R2 `DATA_ADDRESS_WIDTH'd72
`define R3 `DATA_ADDRESS_WIDTH'd73
`define R4 `DATA_ADDRESS_WIDTH'd74
`define R5 `DATA_ADDRESS_WIDTH'd75
`define R6 `DATA_ADDRESS_WIDTH'd76
`define R7 `DATA_ADDRESS_WIDTH'd77
`define R8 `DATA_ADDRESS_WIDTH'd78
`define R9 `DATA_ADDRESS_WIDTH'd79
`define R10 `DATA_ADDRESS_WIDTH'd80
`define R11 `DATA_ADDRESS_WIDTH'd81
`define R12 `DATA_ADDRESS_WIDTH'd82
 
//** Internal Registers **//
`define CREG_PROJECTION_WINDOW_SCALE `DATA_ADDRESS_WIDTH'd83
`define CREG_UNORMALIZED_DIRECTION `DATA_ADDRESS_WIDTH'd84
`define CREG_RAY_DIRECTION `DATA_ADDRESS_WIDTH'd85
`define CREG_E1_LAST `DATA_ADDRESS_WIDTH'd86
`define CREG_E2_LAST `DATA_ADDRESS_WIDTH'd87
`define CREG_T `DATA_ADDRESS_WIDTH'd88
`define CREG_P `DATA_ADDRESS_WIDTH'd89
`define CREG_Q `DATA_ADDRESS_WIDTH'd90
`define CREG_UV0_LAST `DATA_ADDRESS_WIDTH'd91
`define CREG_UV1_LAST `DATA_ADDRESS_WIDTH'd92
`define CREG_UV2_LAST `DATA_ADDRESS_WIDTH'd93
`define CREG_TRI_DIFFUSE_LAST `DATA_ADDRESS_WIDTH'd94
`define CREG_LAST_t `DATA_ADDRESS_WIDTH'd95
`define CREG_LAST_u `DATA_ADDRESS_WIDTH'd96
`define CREG_LAST_v `DATA_ADDRESS_WIDTH'd97
`define CREG_COLOR_ACC `DATA_ADDRESS_WIDTH'd98
`define CREG_t `DATA_ADDRESS_WIDTH'd99
`define CREG_E1 `DATA_ADDRESS_WIDTH'd100
`define CREG_E2 `DATA_ADDRESS_WIDTH'd101
`define CREG_DELTA `DATA_ADDRESS_WIDTH'd102
`define CREG_u `DATA_ADDRESS_WIDTH'd103
`define CREG_v `DATA_ADDRESS_WIDTH'd104
`define CREG_H1 `DATA_ADDRESS_WIDTH'd105
`define CREG_H2 `DATA_ADDRESS_WIDTH'd106
`define CREG_H3 `DATA_ADDRESS_WIDTH'd107
`define CREG_PIXEL_PITCH `DATA_ADDRESS_WIDTH'd108
 
`define CREG_LAST_COL `DATA_ADDRESS_WIDTH'd109 //the last valid column, simply CREG_RESOLUTIONX - 1
`define CREG_TEXTURE_COLOR `DATA_ADDRESS_WIDTH'd110
`define CREG_PIXEL_2D_POSITION `DATA_ADDRESS_WIDTH'd111
`define CREG_TEXWEIGHT1 `DATA_ADDRESS_WIDTH'd112
`define CREG_TEXWEIGHT2 `DATA_ADDRESS_WIDTH'd113
`define CREG_TEXWEIGHT3 `DATA_ADDRESS_WIDTH'd114
`define CREG_TEXWEIGHT4 `DATA_ADDRESS_WIDTH'd115
`define CREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd116
`define CREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd117
`define R99 `DATA_ADDRESS_WIDTH'd118
`define CREG_ZERO `DATA_ADDRESS_WIDTH'd119
`define CREG_CURRENT_OUTPUT_PIXEL `DATA_ADDRESS_WIDTH'd120
`define CREG_3 `DATA_ADDRESS_WIDTH'd121
`define CREG_012 `DATA_ADDRESS_WIDTH'd122
 
//** Ouput registers **//
 
`define OREG_PIXEL_COLOR `DATA_ADDRESS_WIDTH'd128
`define OREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd129
`define OREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd130
`define OREG_ADDR_O `DATA_ADDRESS_WIDTH'd131
//-------------------------------------------------------------
//*** Instruction Set ***
//The order of the instructions is important here!. Don't change
//it unless you know what you are doing. For example all the 'SET'
//family of instructions have the MSB bit in 1. This means that
//if you add an instruction and the MSB=1, this instruction will treated
//as type II (see manual) meaning the second 32bit argument is expected to be
//an inmediate value instead of a register address!
//Another example is that in the JUMP family Bits 3 and 4 have a special
//meaning: b4b3 = 01 => X jump type, b4b3 = 10 => Y jump type, finally
//b4b3 = 11 means Z jump type.
//All this is just to tell you: Don't play with these values!
 
// *** Type I Instructions (OP DST REG1 REG2) ***
`define NOP `INSTRUCTION_OP_LENGTH'b0_000000 //0
`define ADD `INSTRUCTION_OP_LENGTH'b0_000001 //1
`define SUB `INSTRUCTION_OP_LENGTH'b0_000010 //2
`define DIV `INSTRUCTION_OP_LENGTH'b0_000011 //3
`define MUL `INSTRUCTION_OP_LENGTH'b0_000100 //4
`define MAG `INSTRUCTION_OP_LENGTH'b0_000101 //5
`define COPY `INSTRUCTION_OP_LENGTH'b0_000111 //7
`define JGX `INSTRUCTION_OP_LENGTH'b0_001_000 //8
`define JLX `INSTRUCTION_OP_LENGTH'b0_001_001 //9
`define JEQX `INSTRUCTION_OP_LENGTH'b0_001_010 //10 - A
`define JNEX `INSTRUCTION_OP_LENGTH'b0_001_011 //11 - B
`define JGEX `INSTRUCTION_OP_LENGTH'b0_001_100 //12 - C
`define JLEX `INSTRUCTION_OP_LENGTH'b0_001_101 //13 - D
`define INC `INSTRUCTION_OP_LENGTH'b0_001_110 //14 - E
`define ZERO `INSTRUCTION_OP_LENGTH'b0_001_111 //15 - F
`define JGY `INSTRUCTION_OP_LENGTH'b0_010_000 //16
`define JLY `INSTRUCTION_OP_LENGTH'b0_010_001 //17
`define JEQY `INSTRUCTION_OP_LENGTH'b0_010_010 //18
`define JNEY `INSTRUCTION_OP_LENGTH'b0_010_011 //19
`define JGEY `INSTRUCTION_OP_LENGTH'b0_010_100 //20
`define JLEY `INSTRUCTION_OP_LENGTH'b0_010_101 //21
`define CROSS `INSTRUCTION_OP_LENGTH'b0_010_110 //22
`define DOT `INSTRUCTION_OP_LENGTH'b0_010_111 //23
`define JGZ `INSTRUCTION_OP_LENGTH'b0_011_000 //24
`define JLZ `INSTRUCTION_OP_LENGTH'b0_011_001 //25
`define JEQZ `INSTRUCTION_OP_LENGTH'b0_011_010 //26
`define JNEZ `INSTRUCTION_OP_LENGTH'b0_011_011 //27
`define JGEZ `INSTRUCTION_OP_LENGTH'b0_011_100 //28
`define JLEZ `INSTRUCTION_OP_LENGTH'b0_011_101 //29
 
//The next instruction is for simulation debug only
//not to be synthetized! Pretty much behaves the same
//as a NOP, only that prints the register value to
//a log file called 'Registers.log'
`ifdef DEBUG
`define DEBUG_PRINT `INSTRUCTION_OP_LENGTH'b0_011_110 //30
`endif
 
`define MULP `INSTRUCTION_OP_LENGTH'b0_011_111 //31 R1.z = S1.x * S1.y
`define MOD `INSTRUCTION_OP_LENGTH'b0_100_000 //32 R = MODULO( S1,S2 )
`define FRAC `INSTRUCTION_OP_LENGTH'b0_100_001 //33 R =FractionalPart( S1 )
`define INTP `INSTRUCTION_OP_LENGTH'b0_100_010 //34 R =IntergerPart( S1 )
`define NEG `INSTRUCTION_OP_LENGTH'b0_100_011 //35 R = -S1
`define DEC `INSTRUCTION_OP_LENGTH'b0_100_100 //36 R = S1--
`define XCHANGEX `INSTRUCTION_OP_LENGTH'b0_100_101 // R.x = S2.x, R.y = S1.y, R.z = S1.z
`define XCHANGEY `INSTRUCTION_OP_LENGTH'b0_100_110 // R.x = S1.x, R.y = S2.y, R.z = S1.z
`define XCHANGEZ `INSTRUCTION_OP_LENGTH'b0_100_111 // R.x = S1.x, R.y = S1.y, R.z = S2.z
`define IMUL `INSTRUCTION_OP_LENGTH'b0_101_000 // R = INTEGER( S1 * S2 )
`define UNSCALE `INSTRUCTION_OP_LENGTH'b0_101_001 // R = S1 >> SCALE
`define RESCALE `INSTRUCTION_OP_LENGTH'b0_101_010 // R = S1 << SCALE
`define INCX `INSTRUCTION_OP_LENGTH'b0_101_011 // R.X = S1.X + 1
`define INCY `INSTRUCTION_OP_LENGTH'b0_101_100 // R.Y = S1.Y + 1
`define FALSE 32'h0
`define RT_TRUE 48'b1
`define RT_FALSE 48'b0
//---------------------------------------------------------------------------------
 
`define GENERAL_PURPOSE_REG_ADDR_MASK `DATA_ADDRESS_WIDTH'h1F
`define VOID `DATA_ADDRESS_WIDTH'd0 //0000
//** Control register bits **//
`define CR_EN_LIGHTS 0
`define CR_EN_TEXTURE 1
`define CR_USER_AABBIU 2
/** Swapping registers **/
//** Configuration Registers **//
`define CREG_LIGHT_INFO `DATA_ADDRESS_WIDTH'd0
`define CREG_CAMERA_POSITION `DATA_ADDRESS_WIDTH'd1
`define CREG_PROJECTION_WINDOW_MIN `DATA_ADDRESS_WIDTH'd2
`define CREG_PROJECTION_WINDOW_MAX `DATA_ADDRESS_WIDTH'd3
`define CREG_RESOLUTION `DATA_ADDRESS_WIDTH'd4
`define CREG_TEXTURE_SIZE `DATA_ADDRESS_WIDTH'd5
`define CREG_PIXEL_2D_INITIAL_POSITION `DATA_ADDRESS_WIDTH'd6
`define CREG_PIXEL_2D_FINAL_POSITION `DATA_ADDRESS_WIDTH'd7
`define CREG_MAX_PRIMITIVES `DATA_ADDRESS_WIDTH'd8
`define CREG_FIRST_LIGTH `DATA_ADDRESS_WIDTH'd10
`define CREG_FIRST_LIGTH_DIFFUSE `DATA_ADDRESS_WIDTH'd10
//OK, so from address 0x06 to 0x0F is where the lights are,watch out values are harcoded
//for now!! (look in ROM.v for hardcoded values!!!)
 
 
//Don't change the order of the registers. CREG_V* and CREG_UV* registers
//need to be in that specific order for the triangle fetcher to work
//correctly!
 
`define CREG_AABBMIN `DATA_ADDRESS_WIDTH'd42
`define CREG_AABBMAX `DATA_ADDRESS_WIDTH'd43
`define CREG_V0 `DATA_ADDRESS_WIDTH'd44
`define CREG_UV0 `DATA_ADDRESS_WIDTH'd45
`define CREG_V1 `DATA_ADDRESS_WIDTH'd46
`define CREG_UV1 `DATA_ADDRESS_WIDTH'd47
`define CREG_V2 `DATA_ADDRESS_WIDTH'd48
`define CREG_UV2 `DATA_ADDRESS_WIDTH'd49
`define CREG_TRI_DIFFUSE `DATA_ADDRESS_WIDTH'd50
`define CREG_TEX_COLOR1 `DATA_ADDRESS_WIDTH'd53
`define CREG_TEX_COLOR2 `DATA_ADDRESS_WIDTH'd54
`define CREG_TEX_COLOR3 `DATA_ADDRESS_WIDTH'd55
`define CREG_TEX_COLOR4 `DATA_ADDRESS_WIDTH'd56
`define CREG_TEX_COLOR5 `DATA_ADDRESS_WIDTH'd57
`define CREG_TEX_COLOR6 `DATA_ADDRESS_WIDTH'd58
`define CREG_TEX_COLOR7 `DATA_ADDRESS_WIDTH'd59
 
 
/** Non-Swapping registers **/
// ** User Registers **//
//General Purpose registers, the user may put what ever he/she
//wants in here...
`define C1 `DATA_ADDRESS_WIDTH'd64
`define C2 `DATA_ADDRESS_WIDTH'd65
`define C3 `DATA_ADDRESS_WIDTH'd66
`define C4 `DATA_ADDRESS_WIDTH'd67
`define C5 `DATA_ADDRESS_WIDTH'd68
`define C6 `DATA_ADDRESS_WIDTH'd69
`define C7 `DATA_ADDRESS_WIDTH'd70
`define R1 `DATA_ADDRESS_WIDTH'd71
`define R2 `DATA_ADDRESS_WIDTH'd72
`define R3 `DATA_ADDRESS_WIDTH'd73
`define R4 `DATA_ADDRESS_WIDTH'd74
`define R5 `DATA_ADDRESS_WIDTH'd75
`define R6 `DATA_ADDRESS_WIDTH'd76
`define R7 `DATA_ADDRESS_WIDTH'd77
`define R8 `DATA_ADDRESS_WIDTH'd78
`define R9 `DATA_ADDRESS_WIDTH'd79
`define R10 `DATA_ADDRESS_WIDTH'd80
`define R11 `DATA_ADDRESS_WIDTH'd81
`define R12 `DATA_ADDRESS_WIDTH'd82
 
//** Internal Registers **//
`define CREG_PROJECTION_WINDOW_SCALE `DATA_ADDRESS_WIDTH'd83
`define CREG_UNORMALIZED_DIRECTION `DATA_ADDRESS_WIDTH'd84
`define CREG_RAY_DIRECTION `DATA_ADDRESS_WIDTH'd85
`define CREG_E1_LAST `DATA_ADDRESS_WIDTH'd86
`define CREG_E2_LAST `DATA_ADDRESS_WIDTH'd87
`define CREG_T `DATA_ADDRESS_WIDTH'd88
`define CREG_P `DATA_ADDRESS_WIDTH'd89
`define CREG_Q `DATA_ADDRESS_WIDTH'd90
`define CREG_UV0_LAST `DATA_ADDRESS_WIDTH'd91
`define CREG_UV1_LAST `DATA_ADDRESS_WIDTH'd92
`define CREG_UV2_LAST `DATA_ADDRESS_WIDTH'd93
`define CREG_TRI_DIFFUSE_LAST `DATA_ADDRESS_WIDTH'd94
`define CREG_LAST_t `DATA_ADDRESS_WIDTH'd95
`define CREG_LAST_u `DATA_ADDRESS_WIDTH'd96 //0
`define CREG_LAST_v `DATA_ADDRESS_WIDTH'd97 //1
`define CREG_COLOR_ACC `DATA_ADDRESS_WIDTH'd98 //2
`define CREG_t `DATA_ADDRESS_WIDTH'd99 //3
`define CREG_E1 `DATA_ADDRESS_WIDTH'd100 //4
`define CREG_E2 `DATA_ADDRESS_WIDTH'd101 //5
`define CREG_DELTA `DATA_ADDRESS_WIDTH'd102 //6
`define CREG_u `DATA_ADDRESS_WIDTH'd103 //7
`define CREG_v `DATA_ADDRESS_WIDTH'd104 //8
`define CREG_H1 `DATA_ADDRESS_WIDTH'd105 //9
`define CREG_H2 `DATA_ADDRESS_WIDTH'd106 //10
`define CREG_H3 `DATA_ADDRESS_WIDTH'd107 //11
`define CREG_PIXEL_PITCH `DATA_ADDRESS_WIDTH'd108 //12
 
`define CREG_LAST_COL `DATA_ADDRESS_WIDTH'd109 //the last valid column, simply CREG_RESOLUTIONX - 1
`define CREG_TEXTURE_COLOR `DATA_ADDRESS_WIDTH'd110 //14
`define CREG_PIXEL_2D_POSITION `DATA_ADDRESS_WIDTH'd111 //15
`define CREG_TEXWEIGHT1 `DATA_ADDRESS_WIDTH'd112 //16
`define CREG_TEXWEIGHT2 `DATA_ADDRESS_WIDTH'd113 //17
`define CREG_TEXWEIGHT3 `DATA_ADDRESS_WIDTH'd114 //18
`define CREG_TEXWEIGHT4 `DATA_ADDRESS_WIDTH'd115 //19
`define CREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd116 //20
`define CREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd117 //21
`define R99 `DATA_ADDRESS_WIDTH'd118 //22
`define CREG_ZERO `DATA_ADDRESS_WIDTH'd119 //23
`define CREG_CURRENT_OUTPUT_PIXEL `DATA_ADDRESS_WIDTH'd120 //24
`define CREG_3 `DATA_ADDRESS_WIDTH'd121 //25
`define CREG_012 `DATA_ADDRESS_WIDTH'd122 //26
`define CREG_PRIMITIVE_COUNT `DATA_ADDRESS_WIDTH'd123 //27
`define CREG_HIT `DATA_ADDRESS_WIDTH'd124 //28
 
//** Ouput registers **//
 
`define OREG_PIXEL_COLOR `DATA_ADDRESS_WIDTH'd128
`define OREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd129
`define OREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd130
`define OREG_ADDR_O `DATA_ADDRESS_WIDTH'd131
//-------------------------------------------------------------
//*** Instruction Set ***
//The order of the instructions is important here!. Don't change
//it unless you know what you are doing. For example all the 'SET'
//family of instructions have the MSB bit in 1. This means that
//if you add an instruction and the MSB=1, this instruction will treated
//as type II (see manual) meaning the second 32bit argument is expected to be
//an inmediate value instead of a register address!
//Another example is that in the JUMP family Bits 3 and 4 have a special
//meaning: b4b3 = 01 => X jump type, b4b3 = 10 => Y jump type, finally
//b4b3 = 11 means Z jump type.
//All this is just to tell you: Don't play with these values!
 
// *** Type I Instructions (OP DST REG1 REG2) ***
`define NOP `INSTRUCTION_OP_LENGTH'b0_000000 //0
`define ADD `INSTRUCTION_OP_LENGTH'b0_000001 //1
`define SUB `INSTRUCTION_OP_LENGTH'b0_000010 //2
`define DIV `INSTRUCTION_OP_LENGTH'b0_000011 //3
`define MUL `INSTRUCTION_OP_LENGTH'b0_000100 //4
`define MAG `INSTRUCTION_OP_LENGTH'b0_000101 //5
`define COPY `INSTRUCTION_OP_LENGTH'b0_000111 //7
`define JGX `INSTRUCTION_OP_LENGTH'b0_001_000 //8
`define JLX `INSTRUCTION_OP_LENGTH'b0_001_001 //9
`define JEQX `INSTRUCTION_OP_LENGTH'b0_001_010 //10 - A
`define JNEX `INSTRUCTION_OP_LENGTH'b0_001_011 //11 - B
`define JGEX `INSTRUCTION_OP_LENGTH'b0_001_100 //12 - C
`define JLEX `INSTRUCTION_OP_LENGTH'b0_001_101 //13 - D
`define INC `INSTRUCTION_OP_LENGTH'b0_001_110 //14 - E
`define ZERO `INSTRUCTION_OP_LENGTH'b0_001_111 //15 - F
`define JGY `INSTRUCTION_OP_LENGTH'b0_010_000 //16
`define JLY `INSTRUCTION_OP_LENGTH'b0_010_001 //17
`define JEQY `INSTRUCTION_OP_LENGTH'b0_010_010 //18
`define JNEY `INSTRUCTION_OP_LENGTH'b0_010_011 //19
`define JGEY `INSTRUCTION_OP_LENGTH'b0_010_100 //20
`define JLEY `INSTRUCTION_OP_LENGTH'b0_010_101 //21
`define CROSS `INSTRUCTION_OP_LENGTH'b0_010_110 //22
`define DOT `INSTRUCTION_OP_LENGTH'b0_010_111 //23
`define JGZ `INSTRUCTION_OP_LENGTH'b0_011_000 //24
`define JLZ `INSTRUCTION_OP_LENGTH'b0_011_001 //25
`define JEQZ `INSTRUCTION_OP_LENGTH'b0_011_010 //26
`define JNEZ `INSTRUCTION_OP_LENGTH'b0_011_011 //27
`define JGEZ `INSTRUCTION_OP_LENGTH'b0_011_100 //28
`define JLEZ `INSTRUCTION_OP_LENGTH'b0_011_101 //29
 
//The next instruction is for simulation debug only
//not to be synthetized! Pretty much behaves the same
//as a NOP, only that prints the register value to
//a log file called 'Registers.log'
`ifdef DEBUG
`define DEBUG_PRINT `INSTRUCTION_OP_LENGTH'b0_011_110 //30
`endif
 
`define MULP `INSTRUCTION_OP_LENGTH'b0_011_111 //31 R1.z = S1.x * S1.y
`define MOD `INSTRUCTION_OP_LENGTH'b0_100_000 //32 R = MODULO( S1,S2 )
`define FRAC `INSTRUCTION_OP_LENGTH'b0_100_001 //33 R =FractionalPart( S1 )
`define INTP `INSTRUCTION_OP_LENGTH'b0_100_010 //34 R =IntergerPart( S1 )
`define NEG `INSTRUCTION_OP_LENGTH'b0_100_011 //35 R = -S1
`define DEC `INSTRUCTION_OP_LENGTH'b0_100_100 //36 R = S1--
`define XCHANGEX `INSTRUCTION_OP_LENGTH'b0_100_101 // R.x = S2.x, R.y = S1.y, R.z = S1.z
`define XCHANGEY `INSTRUCTION_OP_LENGTH'b0_100_110 // R.x = S1.x, R.y = S2.y, R.z = S1.z
`define XCHANGEZ `INSTRUCTION_OP_LENGTH'b0_100_111 // R.x = S1.x, R.y = S1.y, R.z = S2.z
`define IMUL `INSTRUCTION_OP_LENGTH'b0_101_000 // R = INTEGER( S1 * S2 )
`define UNSCALE `INSTRUCTION_OP_LENGTH'b0_101_001 // R = S1 >> SCALE
`define RESCALE `INSTRUCTION_OP_LENGTH'b0_101_010 // R = S1 << SCALE
`define INCX `INSTRUCTION_OP_LENGTH'b0_101_011 // R.X = S1.X + 1
`define INCY `INSTRUCTION_OP_LENGTH'b0_101_100 // R.Y = S1.Y + 1
`define INCZ `INSTRUCTION_OP_LENGTH'b0_101_101 // R.Z = S1.Z + 1
`define OMWRITE `INSTRUCTION_OP_LENGTH'b0_101_111 //47 IO write to O memory
`define OMWRITE `INSTRUCTION_OP_LENGTH'b0_101_111 //47 IO write to O memory
`define TMREAD `INSTRUCTION_OP_LENGTH'b0_110_000 //48 IO read from T memory
`define LEA `INSTRUCTION_OP_LENGTH'b0_110_001 //49 Load effective address
 
//*** Type II Instructions (OP DST REG1 IMM) ***
`define RETURN `INSTRUCTION_OP_LENGTH'b1_000000 //64 0x40
`define SETX `INSTRUCTION_OP_LENGTH'b1_000001 //65 0x41
`define SETY `INSTRUCTION_OP_LENGTH'b1_000010 //66
`define SETZ `INSTRUCTION_OP_LENGTH'b1_000011 //67
`define SWIZZLE3D `INSTRUCTION_OP_LENGTH'b1_000100 //68
`define LEA `INSTRUCTION_OP_LENGTH'b0_110_001 //49 Load effective address
 
//*** Type II Instructions (OP DST REG1 IMM) ***
`define RETURN `INSTRUCTION_OP_LENGTH'b1_000000 //64 0x40
`define SETX `INSTRUCTION_OP_LENGTH'b1_000001 //65 0x41
`define SETY `INSTRUCTION_OP_LENGTH'b1_000010 //66
`define SETZ `INSTRUCTION_OP_LENGTH'b1_000011 //67
`define SWIZZLE3D `INSTRUCTION_OP_LENGTH'b1_000100 //68
`define JMP `INSTRUCTION_OP_LENGTH'b1_011000 //56
`define CALL `INSTRUCTION_OP_LENGTH'b1_011001 //57
`define RET `INSTRUCTION_OP_LENGTH'b1_011010 //58
 
//-------------------------------------------------------------
 
//All the posible values for the SWIZZLE3D instruction are defined next
`define SWIZZLE_XXX 32'd0
`define SWIZZLE_YYY 32'd1
`define SWIZZLE_ZZZ 32'd2
`define SWIZZLE_XYY 32'd3
`define SWIZZLE_XXY 32'd4
`define SWIZZLE_XZZ 32'd5
`define SWIZZLE_XXZ 32'd6
`define SWIZZLE_YXX 32'd7
`define SWIZZLE_YYX 32'd8
`define SWIZZLE_YZZ 32'd9
`define SWIZZLE_YYZ 32'd10
`define SWIZZLE_ZXX 32'd11
`define SWIZZLE_ZZX 32'd12
`define SWIZZLE_ZYY 32'd13
`define SWIZZLE_ZZY 32'd14
`define SWIZZLE_XZX 32'd15
`define SWIZZLE_XYX 32'd16
`define SWIZZLE_YXY 32'd17
`define SWIZZLE_YZY 32'd18
`define SWIZZLE_ZXZ 32'd19
`define SWIZZLE_ZYZ 32'd20
`define SWIZZLE_YXZ 32'd21
 
 
`define RET `INSTRUCTION_OP_LENGTH'b1_011010 //58
 
//-------------------------------------------------------------
 
//All the posible values for the SWIZZLE3D instruction are defined next
`define SWIZZLE_XXX 32'd0
`define SWIZZLE_YYY 32'd1
`define SWIZZLE_ZZZ 32'd2
`define SWIZZLE_XYY 32'd3
`define SWIZZLE_XXY 32'd4
`define SWIZZLE_XZZ 32'd5
`define SWIZZLE_XXZ 32'd6
`define SWIZZLE_YXX 32'd7
`define SWIZZLE_YYX 32'd8
`define SWIZZLE_YZZ 32'd9
`define SWIZZLE_YYZ 32'd10
`define SWIZZLE_ZXX 32'd11
`define SWIZZLE_ZZX 32'd12
`define SWIZZLE_ZYY 32'd13
`define SWIZZLE_ZZY 32'd14
`define SWIZZLE_XZX 32'd15
`define SWIZZLE_XYX 32'd16
`define SWIZZLE_YXY 32'd17
`define SWIZZLE_YZY 32'd18
`define SWIZZLE_ZXZ 32'd19
`define SWIZZLE_ZYZ 32'd20
`define SWIZZLE_YXZ 32'd21
 
 
/rtl/Module_WishBoneSlave.v
28,32 → 28,32
module WishBoneSlaveUnit
(
//WB Input signals
input wire CLK_I,
input wire RST_I,
input wire STB_I,
input wire WE_I,
input wire[`WB_WIDTH-1:0] DAT_I,
input wire[`WB_WIDTH-1:0] ADR_I,
input wire [1:0] TGA_I,
output wire ACK_O,
input wire MST_I, //Master In!
input wire CYC_I,
output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
input wire CLK_I,
input wire RST_I,
input wire STB_I,
input wire WE_I,
input wire[`WB_WIDTH-1:0] DAT_I,
input wire[`WB_WIDTH-1:0] ADR_I,
input wire [1:0] TGA_I,
output wire ACK_O,
input wire MST_I, //Master In!
input wire CYC_I,
output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
output wire [`DATA_ROW_WIDTH-1:0] oDataBus,
output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
output wire oDataWriteEnable,
output wire oInstructionWriteEnable
output wire [`INSTRUCTION_WIDTH-1:0] oInstructionBus,
output wire oDataWriteEnable,
output wire oInstructionWriteEnable
 
);
 
FFD_POSEDGE_SYNCRONOUS_RESET # (16) FFADR
(
.Clock( CYC_I ),
.Reset( RST_I ),
.Enable(1'b1),
.D( ADR_I[15:0] ),
.Q( oInstructionWriteAddress )
.Clock( CYC_I ),
.Reset( RST_I ),
.Enable(1'b1),
.D( ADR_I[15:0] ),
.Q( oInstructionWriteAddress )
);
 
assign oDataWriteAddress = oInstructionWriteAddress;
62,11 → 62,11
 
FFD_POSEDGE_SYNCRONOUS_RESET # (2) FFADDRTYPE
(
.Clock( CYC_I ),
.Reset( RST_I ),
.Enable(1'b1),
.D( TGA_I ),
.Q( wTGA_Latched )
.Clock( CYC_I ),
.Reset( RST_I ),
.Enable(1'b1),
.D( TGA_I ),
.Q( wTGA_Latched )
);
 
 
84,11 → 84,11
wire wDelay;
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFOutputDelay
(
.Clock( Clock ),
.Enable( 1'b1 ),
.Reset( Reset ),
.D( wLatchNow ),
.Q( wDelay )
.Clock( Clock ),
.Enable( 1'b1 ),
.Reset( Reset ),
.D( wLatchNow ),
.Q( wDelay )
);
 
assign ACK_O = wDelay & STB_I; //make sure we set ACK_O back to zero when STB_I is zero
111,12 → 111,12
wire [`WIDTH-1:0] wVx;
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vx
(
.Clock( Clock ),
.Reset( Reset ),
.Enable( wXYZSel[0] & STB_I ),
.D( DAT_I ),
.Q( wVx )
.Clock( Clock ),
.Reset( Reset ),
.Enable( wXYZSel[0] & STB_I ),
.D( DAT_I ),
.Q( wVx )
);
 
 
124,12 → 124,12
wire [`WIDTH-1:0] wVy;
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vy
(
.Clock( Clock ),
.Reset( Reset ),
.Enable( wXYZSel[1] & STB_I ),
.D( DAT_I ),
.Q( wVy )
.Clock( Clock ),
.Reset( Reset ),
.Enable( wXYZSel[1] & STB_I ),
.D( DAT_I ),
.Q( wVy )
);
 
//Flip Flop to Store Vz
137,14 → 137,14
 
FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBS2MEM_Vz
(
.Clock( Clock ),
.Reset( Reset ),
.Enable( wXYZSel[2] & STB_I ),
.D( DAT_I ),
.Q( wVz )
.Clock( Clock ),
.Reset( Reset ),
.Enable( wXYZSel[2] & STB_I ),
.D( DAT_I ),
.Q( wVz )
);
 
assign oDataBus = {wVx,wVy,wVz};
assign oDataBus = {wVx,wVy,wVz};
assign oInstructionBus = {wVx,wVy};
wire wIsInstructionAddress,wIsDataAddress;
assign wIsInstructionAddress = (wTGA_Latched == `TAG_WBS_INSTRUCTION_ADDRESS_TYPE) ? 1'b1 : 1'b0;
/rtl/Unit_Control.v
85,7 → 85,8
`define CU_WAIT_FOR_RENDER_ENABLE 49
`define CU_ACK_TCC 50
`define CU_WAIT_FOR_HOST_DATA_AVAILABLE 51
`define CU_WAIT_FOR_HOST_DATA_ACK 52
`define CU_WAIT_FOR_HOST_DATA_ACK 52
`define CU_COMMIT_PIXEL_RESULT 53
//--------------------------------------------------------------
module ControlUnit
(
570,11 → 571,12
//oIncCurrentPitch = 0;
if ( iRenderEnable)
NextState = `CU_TRIGGER_RGU;
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;//`CU_TRIGGER_RGU;
else
NextState = `CU_WAIT_FOR_RENDER_ENABLE;
end
//-----------------------------------------
/*
`CU_TRIGGER_RGU:
begin
586,7 → 588,7
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_RGU;
oGFUEnable = 0;
oUCodeEnable = 1; //*
oUCodeEnable = 1;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
638,7 → 640,7
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = 0;
oGFUEnable = 0;
oUCodeEnable = 0; //*
oUCodeEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
655,7 → 657,8
else
NextState = `CU_ACK_RGU;
end
end
*/
//-----------------------------------------
`CU_TRIGGER_TCC:
begin
939,7 → 942,7
//oIncCurrentPitch = 0;
// $stop();
/*
if ( iUCodeDone == 1'b0 & iSceneTraverseComplete == 1'b1)
NextState = `CU_CHECK_HIT;
else if ( iUCodeDone == 1'b0 & iSceneTraverseComplete == 1'b0) //ERROR!!! What if iSceneTraverseComplete will become 1 a cycle after this??
946,11 → 949,36
NextState = `CU_WAIT_FOR_HOST_DATA_ACK;//`CU_WAIT_FOR_HOST_DATA_AVAILABLE;
else
NextState = `CU_ACK_MAIN;
*/
if (iUCodeDone == 1'b0 && iUCodeReturnValue == 0)
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;
else if (iUCodeDone == 1'b0 && iUCodeReturnValue == 1)
NextState = `CU_COMMIT_PIXEL_RESULT;
else
NextState = `CU_ACK_MAIN;
end
//-----------------------------------------
//-----------------------------------------
`CU_COMMIT_PIXEL_RESULT:
begin
oCodeInstructioPointer = 0;
oUCodeEnable = 0;
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 0;
oFlipMem = 0;
oDone = 0;
oResultCommited = 1;
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;
end
//-----------------------------------------
`CU_WAIT_FOR_PSU:
begin
1087,7 → 1115,7
//oIncCurrentPitch = 0;
if ( iUCodeDone == 0 && iUCodeReturnValue == 1)
NextState = `CU_TRIGGER_RGU;
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;//`CU_TRIGGER_RGU;
else if (iUCodeDone == 0 && iUCodeReturnValue == 0)
NextState = `CU_DONE;
else
/rtl/Theia.v
130,9 → 130,9
wire [`MAX_CORES-1:0] wRCommited;
 
 
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
assign HDL_O = wHostDataLatched[0] & wHostDataLatched[1] & wHostDataLatched[2] & wHostDataLatched[3];
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
assign HDL_O = wHostDataLatched[0] & wHostDataLatched[1] & wHostDataLatched[2] & wHostDataLatched[3];
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
 
 
 
309,7 → 309,7
(
.Clock( CLK_I ),
.Reset( RST_I ),
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
/rtl/Module_ROM.v
1,703 → 1,756
 
 
`define ONE (32'h1 << `SCALE)
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
/*
I can't synthesize roms, the rom needs to be adapted depending on the
final target silicon.
*/
 
 
//--------------------------------------------------------
module ROM
(
input wire[`ROM_ADDRESS_WIDTH-1:0] Address,
`ifdef DEBUG
input wire [`MAX_CORES-1:0] iDebug_CoreID,
`endif
output reg [`INSTRUCTION_WIDTH-1:0] I
);
 
 
always @( Address )
begin
case (Address)
//Hardcoded stuff :(
`define RAY_INSIDE_BOX `R3
`define CURRENT_LIGHT_POS `CREG_FIRST_LIGTH //TODO: CAHNEG T
`define CURRENT_LIGHT_DIFFUSE 16'h6
 
//-----------------------------------------------------------------
`define TAG_PIXELSHADER 16'd278
`define TAG_USERCONSTANTS 16'd276
`define TAG_PSU_UCODE_ADRESS2 16'd248
`define TAG_PSU_UCODE_ADRESS 16'd232
`define LABEL_TCC_EXIT 16'd231
`define TAG_TCC_UCODE_ADDRESS 16'd190
`define LABEL_BIU4 16'd189
`define LABEL_BIU3 16'd179
`define LABEL_BIU2 16'd176
`define LABEL_BIU1 16'd174
`define TAG_BIU_UCODE_ADDRESS 16'd157
`define LABEL_HIT 16'd155
`define LABEL15 16'd153
`define LABEL14 16'd151
`define LABEL13 16'd149
`define LABEL_TEST_XY_PLANE 16'd144
`define LABEL12 16'd142
`define LABEL11 16'd140
`define LABEL10 16'd138
`define LABEL_TEST_XZ_PLANE 16'd132
`define LABEL9 16'd130
`define LABEL8 16'd128
`define LABEL7 16'd126
`define LABEL_TEST_YZ_PLANE 16'd120
`define LABEL_RAY_INSIDE_BOX 16'd117
`define LABEL_ELSEZ 16'd116
`define LABEL6 16'd113
`define LABEL_ELESE_IFZ 16'd109
`define LABEL5 16'd106
`define LABEL_TEST_RAY_Z_ORIGEN 16'd102
`define LABEL_ELSEY 16'd101
`define LABEL4 16'd98
`define LABEL_ELESE_IFY 16'd94
`define LABEL3 16'd91
`define LABEL_TEST_RAY_Y_ORIGEN 16'd87
`define LABEL_ELSEX 16'd86
`define LABEL2 16'd83
`define LABEL_ELSE_IFX 16'd79
`define LABEL1 16'd76
`define LABEL_TEST_RAY_X_ORIGEN 16'd72
`define TAG_AABBIU_UCODE_ADDRESS 16'd69
`define LABEL_ALLDONE 16'd67
`define LABEL_NPG_NEXT_ROW 16'd63
`define TAG_NPG_UCODE_ADDRESS 16'd55
`define TAG_RGU_UCODE_ADDRESS 16'd47
`define TAG_CPPU_UCODE_ADDRESS 16'd44
`define LABEL_IS_NO_HIT 16'd43
`define LABEL_IS_HIT 16'd39
`define TAG_ADRR_MAIN 16'd37
 
 
//-------------------------------------------------------------------------
//Default values for some registers after reset
//-------------------------------------------------------------------------
//This is the first code that gets executed after the machine is
//externally configured ie after the MST_I goes from 1 to zero.
//It sets initial values for some of the internal registers
 
0: I = { `ZERO ,`CREG_LAST_t ,`VOID ,`VOID };
//Set the last 't' to very positive value(500)
1: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
2: I = { `ZERO ,`OREG_PIXEL_COLOR ,`VOID ,`VOID };
3: I = { `COPY ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_INITIAL_POSITION ,`VOID };
 
 
//Calculate the initial linear address for ADR_O
//this is: (X_initial + RESOLUTION_Y*Y_intial) * 3.
//Notice that we need to use 'unscaled' ie. integer
//values because the resuts of the multiplication by
//the resoluction is to large to fit a fixed point
//representation.
 
4: I = { `COPY ,`R1 ,`CREG_RESOLUTION ,`VOID };
5: I = { `UNSCALE ,`R1 ,`R1 ,`VOID };
6: I = { `SETX ,`R1 ,32'h1 };
7: I = { `SETZ ,`R1 ,32'h0 };
8: I = { `COPY ,`R2 ,`CREG_PIXEL_2D_INITIAL_POSITION ,`VOID };
9: I = { `UNSCALE ,`R2 ,`R2 ,`VOID };
 
//Ok lets start by calculating RESOLUTION_Y*Y_intial
10: I = { `IMUL ,`R1 ,`R1 ,`R2 };
11: I = { `COPY ,`R2 ,`R1 ,`VOID };
12: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YYY };
 
//now X_initial + RESOLUTION_Y*Y_intial
13: I = { `ADD ,`R3 ,`R1 ,`R2 };
14: I = { `COPY ,`R2 ,`R1 ,`VOID };
15: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_ZZZ };
16: I = { `ADD ,`R3 ,`R3 ,`R2 };
17: I = { `SWIZZLE3D ,`R3 ,`SWIZZLE_XXX };
 
//finally multiply by 3 to get:
//(X_initial + RESOLUTION_Y*Y_intial) * 3 voila!
18: I = { `SETX ,`R2 ,32'h3 };
19: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_XXX };
20: I = { `IMUL ,`CREG_PIXEL_PITCH ,`R3 ,`R2 };
 
//By this point you should be wondering why not
//just do DOT R1 [1 Resolution_Y 0] [X_intial Y_intial 0 ]?
//well because DOT uses fixed point and the result may not
//fit :(
 
//Transform from fixed point to integer
//UNSCALE CREG_PIXEL_PITCH CREG_PIXEL_PITCH VOID
21: I = { `COPY ,`OREG_ADDR_O ,`CREG_PIXEL_PITCH ,`VOID };
 
22: I = { `SETX ,`CREG_3 ,32'h3 };
23: I = { `SWIZZLE3D ,`CREG_3 ,`SWIZZLE_XXX };
 
24: I = { `SETX ,`CREG_012 ,32'h0 };
25: I = { `SETY ,`CREG_012 ,32'h1 };
26: I = { `SETZ ,`CREG_012 ,32'h2 };
27: I = { `COPY ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_012 ,`VOID };
28: I = { `ZERO ,`CREG_TEXTURE_COLOR ,`VOID ,`VOID };
29: I = { `ZERO ,`CREG_ZERO ,`VOID ,`VOID };
 
30: I = { `ZERO ,`R1 ,`VOID ,`VOID };
31: I = { `ZERO ,`R2 ,`VOID ,`VOID };
32: I = { `ZERO ,`R3 ,`VOID ,`VOID };
33: I = { `ZERO ,`R4 ,`VOID ,`VOID };
34: I = { `ZERO ,`R5 ,`VOID ,`VOID };
35: I = { `ZERO ,`R99 ,`VOID ,`VOID };
36: I = { `RETURN ,`RT_TRUE };
 
//----------------------------------------------
//TAG_ADRR_MAIN:
 
37: I = { `CALL ,`ENTRYPOINT_ADRR_BIU ,`VOID ,`VOID };
38: I = { `JEQX ,`LABEL_IS_NO_HIT ,`R99 ,`CREG_ZERO };
 
//LABEL_IS_HIT:
39: I = { `CALL ,`ENTRYPOINT_ADRR_TCC ,`VOID ,`VOID };
40: I = { `NOP ,`RT_FALSE };
41: I = { `RETURN ,`RT_TRUE };
42: I = { `NOP ,`RT_FALSE };
 
//LABEL_IS_NO_HIT:
43: I = { `RETURN ,`RT_FALSE };
 
 
//----------------------------------------------------------------------
//Micro code for CPPU
//TAG_CPPU_UCODE_ADDRESS:
 
 
44: I = { `SUB ,`R1 ,`CREG_PROJECTION_WINDOW_MAX ,`CREG_PROJECTION_WINDOW_MIN };
45: I = { `DIV ,`CREG_PROJECTION_WINDOW_SCALE ,`R1 ,`CREG_RESOLUTION };
46: I = { `RETURN ,`RT_FALSE };
 
//----------------------------------------------------------------------
//Micro code for RGU
//TAG_RGU_UCODE_ADDRESS:
 
 
47: I = { `MUL ,`R1 ,`CREG_PIXEL_2D_POSITION ,`CREG_PROJECTION_WINDOW_SCALE };
48: I = { `ADD ,`R1 ,`R1 ,`CREG_PROJECTION_WINDOW_MIN };
49: I = { `SUB ,`CREG_UNORMALIZED_DIRECTION ,`R1 ,`CREG_CAMERA_POSITION };
50: I = { `MAG ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`VOID };
51: I = { `DIV ,`CREG_RAY_DIRECTION ,`CREG_UNORMALIZED_DIRECTION ,`R2 };
52: I = { `DEC ,`CREG_LAST_COL ,`CREG_PIXEL_2D_FINAL_POSITION ,`VOID };
53: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
54: I = { `RETURN ,`RT_FALSE };
//----------------------------------------------------------------------
//Next Pixel generation Code (NPG)
//TAG_NPG_UCODE_ADDRESS:
 
55: I = { `ZERO ,`CREG_TEXTURE_COLOR ,`VOID ,`VOID };
56: I = { `SETX ,`CREG_TEXTURE_COLOR ,32'h60000 };
57: I = { `ADD ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_3 };
 
58: I = { `ADD ,`CREG_PIXEL_PITCH ,`CREG_PIXEL_PITCH ,`CREG_3 };
59: I = { `COPY ,`OREG_ADDR_O ,`CREG_PIXEL_PITCH ,`VOID };
60: I = { `JGEX ,`LABEL_NPG_NEXT_ROW ,`CREG_PIXEL_2D_POSITION ,`CREG_LAST_COL };
61: I = { `INCX ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
62: I = { `RETURN ,`RT_TRUE };
 
//LABEL_NPG_NEXT_ROW:
63: I = { `SETX ,`CREG_PIXEL_2D_POSITION ,32'h0 };
64: I = { `INCY ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
65: I = { `JGEY ,`LABEL_ALLDONE ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_FINAL_POSITION };
66: I = { `RETURN ,`RT_TRUE };
 
//LABEL_ALLDONE:
67: I = { `NOP ,`RT_FALSE };
68: I = { `RETURN ,`RT_FALSE };
 
//----------------------------------------------------------------------
//Micro code for AABBIU
//TAG_AABBIU_UCODE_ADDRESS:
69: I = { `ZERO ,`R3 ,`VOID ,`VOID };
70: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
71: I = { `RETURN ,`RT_TRUE };
 
//LABEL_TEST_RAY_X_ORIGEN:
72: I = { `JGEX ,`LABEL_ELSE_IFX ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
73: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
74: I = { `JLEX ,`LABEL1 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
75: I = { `RETURN ,`RT_FALSE };
 
//LABEL1:
76: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
77: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
78: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELSE_IFX:
79: I = { `JLEX ,`LABEL_ELSEX ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
80: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
81: I = { `JGEX ,`LABEL2 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
82: I = { `RETURN ,`RT_FALSE };
//LABEL2:
83: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
84: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
85: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
//LABEL_ELSEX:
86: I = { `SETX ,`R5 ,32'b1 };
 
//LABEL_TEST_RAY_Y_ORIGEN:
87: I = { `JGEY ,`LABEL_ELESE_IFY ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
88: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
89: I = { `JLEY ,`LABEL3 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
90: I = { `RETURN ,`RT_FALSE };
 
//LABEL3:
91: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
92: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
93: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELESE_IFY:
94: I = { `JLEY ,`LABEL_ELSEY ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
95: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
96: I = { `JGEY ,`LABEL4 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
97: I = { `RETURN ,`RT_FALSE };
 
//LABEL4:
98: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
99: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
100: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELSEY:
101: I = { `SETY ,`R5 ,32'b1 };
 
//LABEL_TEST_RAY_Z_ORIGEN:
102: I = { `JGEZ ,`LABEL_ELESE_IFZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
103: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
104: I = { `JLEZ ,`LABEL5 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
105: I = { `RETURN ,`RT_FALSE };
 
//LABEL5:
106: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
107: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
108: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
 
//LABEL_ELESE_IFZ:
109: I = { `JLEZ ,`LABEL_ELSEZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
110: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
111: I = { `JGEZ ,`LABEL6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
112: I = { `RETURN ,`RT_FALSE };
 
//LABEL6:
113: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
114: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
115: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
 
//LABEL_ELSEZ:
116: I = { `SETZ ,`R5 ,32'b1 };
 
//LABEL_RAY_INSIDE_BOX:
117: I = { `ZERO ,`R1 ,`VOID ,`VOID };
118: I = { `JEQX ,`LABEL_TEST_YZ_PLANE ,`R1 ,`RAY_INSIDE_BOX };
//BUG need a NOP here else pipeline gets confused
119: I = { `RETURN ,`RT_TRUE };
 
//LABEL_TEST_YZ_PLANE:
120: I = { `JNEX ,`LABEL_TEST_XZ_PLANE ,`R5 ,`R1 };
121: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_XXX };
122: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
123: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
124: I = { `JGEY ,`LABEL7 ,`R2 ,`CREG_AABBMIN };
125: I = { `RETURN ,`RT_FALSE };
 
//LABEL7:
126: I = { `JLEY ,`LABEL8 ,`R2 ,`CREG_AABBMAX };
127: I = { `RETURN ,`RT_FALSE };
 
//LABEL8:
128: I = { `JGEZ ,`LABEL9 ,`R2 ,`CREG_AABBMIN };
129: I = { `RETURN ,`RT_FALSE };
 
//LABEL9:
130: I = { `JLEZ ,`LABEL_TEST_XZ_PLANE ,`R2 ,`CREG_AABBMAX };
131: I = { `RETURN ,`RT_FALSE };
 
//LABEL_TEST_XZ_PLANE:
132: I = { `JNEY ,`LABEL_TEST_XY_PLANE ,`R5 ,`R1 };
133: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_YYY };
134: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
135: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
136: I = { `JGEX ,`LABEL10 ,`R2 ,`CREG_AABBMIN };
137: I = { `RETURN ,`RT_FALSE };
 
//LABEL10:
138: I = { `JLEX ,`LABEL11 ,`R2 ,`CREG_AABBMAX };
139: I = { `RETURN ,`RT_FALSE };
 
//LABEL11:
140: I = { `JGEZ ,`LABEL12 ,`R2 ,`CREG_AABBMIN };
141: I = { `RETURN ,`RT_FALSE };
 
//LABEL12:
142: I = { `JLEZ ,`LABEL_TEST_XY_PLANE ,`R2 ,`CREG_AABBMAX };
143: I = { `RETURN ,`RT_FALSE };
 
//LABEL_TEST_XY_PLANE:
144: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_ZZZ };
145: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
146: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
147: I = { `JGEX ,`LABEL13 ,`R2 ,`CREG_AABBMIN };
148: I = { `RETURN ,`RT_FALSE };
 
//LABEL13:
149: I = { `JLEX ,`LABEL14 ,`R2 ,`CREG_AABBMAX };
150: I = { `RETURN ,`RT_FALSE };
 
//LABEL14:
151: I = { `JGEY ,`LABEL15 ,`R2 ,`CREG_AABBMIN };
152: I = { `RETURN ,`RT_FALSE };
 
//LABEL15:
153: I = { `JLEY ,`LABEL_HIT ,`R2 ,`CREG_AABBMAX };
154: I = { `RETURN ,`RT_FALSE };
 
//LABEL_HIT:
155: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
156: I = { `RETURN ,`RT_TRUE };
 
//------------------------------------------------------------------------
//BIU Micro code
//TAG_BIU_UCODE_ADDRESS:
157: I = { `ZERO ,`OREG_PIXEL_COLOR ,`VOID ,`VOID };
158: I = { `SETX ,`R3 ,`ONE };
159: I = { `SETX ,`R1 ,32'h00000 };
160: I = { `SUB ,`CREG_E1 ,`CREG_V1 ,`CREG_V0 };
161: I = { `SUB ,`CREG_E2 ,`CREG_V2 ,`CREG_V0 };
162: I = { `SUB ,`CREG_T ,`CREG_CAMERA_POSITION ,`CREG_V0 };
163: I = { `CROSS ,`CREG_P ,`CREG_RAY_DIRECTION ,`CREG_E2 };
164: I = { `CROSS ,`CREG_Q ,`CREG_T ,`CREG_E1 };
165: I = { `DOT ,`CREG_H1 ,`CREG_Q ,`CREG_E2 };
166: I = { `DOT ,`CREG_H2 ,`CREG_P ,`CREG_T };
167: I = { `DOT ,`CREG_H3 ,`CREG_Q ,`CREG_RAY_DIRECTION };
168: I = { `DOT ,`CREG_DELTA ,`CREG_P ,`CREG_E1 };
169: I = { `DIV ,`CREG_t ,`CREG_H1 ,`CREG_DELTA };
170: I = { `DIV ,`CREG_u ,`CREG_H2 ,`CREG_DELTA };
171: I = { `DIV ,`CREG_v ,`CREG_H3 ,`CREG_DELTA };
172: I = { `JGEX ,`LABEL_BIU1 ,`CREG_u ,`R1 };
173: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU1:
174: I = { `JGEX ,`LABEL_BIU2 ,`CREG_v ,`R1 };
175: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU2:
176: I = { `ADD ,`R2 ,`CREG_u ,`CREG_v };
177: I = { `JLEX ,`LABEL_BIU3 ,`R2 ,`R3 };
178: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU3:
179: I = { `JGEX ,`LABEL_BIU4 ,`CREG_t ,`CREG_LAST_t };
180: I = { `COPY ,`CREG_LAST_t ,`CREG_t ,`VOID };
181: I = { `COPY ,`CREG_LAST_u ,`CREG_u ,`VOID };
182: I = { `COPY ,`CREG_LAST_v ,`CREG_v ,`VOID };
183: I = { `COPY ,`CREG_E1_LAST ,`CREG_E1 ,`VOID };
184: I = { `COPY ,`CREG_E2_LAST ,`CREG_E2 ,`VOID };
185: I = { `COPY ,`CREG_UV0_LAST ,`CREG_UV0 ,`VOID };
186: I = { `COPY ,`CREG_UV1_LAST ,`CREG_UV1 ,`VOID };
187: I = { `COPY ,`CREG_UV2_LAST ,`CREG_UV2 ,`VOID };
188: I = { `COPY ,`CREG_TRI_DIFFUSE_LAST ,`CREG_TRI_DIFFUSE ,`VOID };
//LABEL_BIU4:
189: I = { `RET ,`R99 ,`TRUE };
 
 
//-------------------------------------------------------------------------
//Calculate the adress of the texure coordiantes.
 
//TAG_TCC_UCODE_ADDRESS:
//Do this calculation only if this triangle is the one closest to the camera
190: I = { `JGX ,`LABEL_TCC_EXIT ,`CREG_t ,`CREG_LAST_t };
 
//First get the UV coodrinates and store in R1
//R1x: u_coordinate = U0 + last_u * (U1 - U0) + last_v * (U2 - U0)
//R1y: v_coordinate = V0 + last_u * (V1 - V0) + last_v * (V2 - V0)
//R1z: 0
 
191: I = { `SUB ,`R1 ,`CREG_UV1_LAST ,`CREG_UV0_LAST };
192: I = { `SUB ,`R2 ,`CREG_UV2_LAST ,`CREG_UV0_LAST };
193: I = { `MUL ,`R1 ,`CREG_LAST_u ,`R1 };
194: I = { `MUL ,`R2 ,`CREG_LAST_v ,`R2 };
195: I = { `ADD ,`R1 ,`R1 ,`R2 };
196: I = { `ADD ,`R1 ,`R1 ,`CREG_UV0_LAST };
 
//R7x : fu = (u_coordinate) * gTexture.mWidth
//R7y : fv = (v_coordinate) * gTexture.mWidth
//R7z : 0
197: I = { `MUL ,`R7 ,`R1 ,`CREG_TEXTURE_SIZE };
 
//R1x: u1 = ((int)fu) % gTexture.mWidth
//R1y: v1 = ((int)fv) % gTexture.mHeight
//R1z: 0
//R2x: u2 = (u1 + 1 ) % gTexture.mWidth
//R2y: v2 = (v2 + 1 ) % gTexture.mHeight
//R2z: 0
// Notice MOD2 only operates over
// numbers that are power of 2 also notice that the
// textures are assumed to be squares!
//x % 2^n == x & (2^n - 1).
 
198: I = { `MOD ,`R1 ,`R7 ,`CREG_TEXTURE_SIZE };
199: I = { `INC ,`R2 ,`R1 ,`VOID };
200: I = { `MOD ,`R2 ,`R2 ,`CREG_TEXTURE_SIZE };
 
//Cool now we should store the values in the appropiate registers
//OREG_TEX_COORD1.x = u1 + v1 * gTexture.mWidth
//OREG_TEX_COORD1.y = u2 + v1 * gTexture.mWidth
//OREG_TEX_COORD1.z = 0
//OREG_TEX_COORD2.x = u1 + v2 * gTexture.mWidth
//OREG_TEX_COORD2.y = u2 + v2 * gTexture.mWidth
//OREG_TEX_COORD1.z = 0
 
//R1= [u1 v1 0]
//R2= [u2 v2 0]
 
//R2 = [v2 u2 0]
201: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YXZ };
 
//R3 = [v2 v1 0]
202: I = { `XCHANGEX ,`R3 ,`R1 ,`R2 };
 
 
//R4 = [u1 u2 0]
203: I = { `XCHANGEX ,`R4 ,`R2 ,`R1 };
 
//R2 = [v2*H v1*H 0]
204: I = { `UNSCALE ,`R9 ,`R3 ,`VOID };
205: I = { `UNSCALE ,`R8 ,`CREG_TEXTURE_SIZE ,`VOID };
206: I = { `IMUL ,`R2 ,`R9 ,`R8 };
 
//OREG_TEX_COORD1 = [u1 + v2*H u2 + v1*H 0]
//R4 = FixedToIinteger(R4)
207: I = { `UNSCALE ,`R4 ,`R4 ,`VOID };
208: I = { `ADD ,`R12 ,`R2 ,`R4 };
209: I = { `SETX ,`R5 ,32'h3 };
210: I = { `SETY ,`R5 ,32'h3 };
211: I = { `SETZ ,`R5 ,32'h3 };
//Multiply by 3 (the pitch)
//IMUL OREG_TEX_COORD1 R12 R5
212: I = { `IMUL ,`CREG_TEX_COORD1 ,`R12 ,`R5 };
 
//R4 = [u2 u1 0]
213: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YXZ };
 
 
//OREG_TEX_COORD2 [u2 + v2*H u1 + v1*H 0]
214: I = { `ADD ,`R12 ,`R2 ,`R4 };
//Multiply by 3 (the pitch)
//IMUL OREG_TEX_COORD2 R12 R5
215: I = { `IMUL ,`CREG_TEX_COORD2 ,`R12 ,`R5 };
 
 
//Cool now get the weights
 
//w1 = (1 - fracu) * (1 - fracv)
//w2 = fracu * (1 - fracv)
//w3 = (1 - fracu) * fracv
//w4 = fracu * fracv
 
//R4x: fracu
//R4y: fracv
//R4z: 0
216: I = { `FRAC ,`R4 ,`R7 ,`VOID };
 
//R5x: fracv
//R5y: fracu
//R5z: 0
217: I = { `COPY ,`R5 ,`R4 ,`VOID };
218: I = { `SWIZZLE3D ,`R5 ,`SWIZZLE_YXZ };
 
 
//R5x: 1 - fracv
//R5y: 1 - fracu
//R5y: 1
219: I = { `NEG ,`R5 ,`R5 ,`VOID };
220: I = { `INC ,`R5 ,`R5 ,`VOID };
 
//R5x: 1 - fracv
//R5y: 1 - fracu
//R5y: (1 - fracv)(1 - fracu)
221: I = { `MULP ,`CREG_TEXWEIGHT1 ,`R5 ,`VOID };
 
//CREG_TEXWEIGHT1.x = (1 - fracv)(1 - fracu)
//CREG_TEXWEIGHT1.y = (1 - fracv)(1 - fracu)
//CREG_TEXWEIGHT1.z = (1 - fracv)(1 - fracu)
222: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT1 ,`SWIZZLE_ZZZ };
 
 
//R6x: w2: fracu * (1 - fracv )
//R6y: w3: fracv * (1 - fracu )
//R6z: 0
223: I = { `MUL ,`R6 ,`R4 ,`R5 };
 
//CREG_TEXWEIGHT2.x = fracu * (1 - fracv )
//CREG_TEXWEIGHT2.y = fracu * (1 - fracv )
//CREG_TEXWEIGHT2.z = fracu * (1 - fracv )
224: I = { `COPY ,`CREG_TEXWEIGHT2 ,`R6 ,`VOID };
225: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT2 ,`SWIZZLE_XXX };
 
//CREG_TEXWEIGHT3.x = fracv * (1 - fracu )
//CREG_TEXWEIGHT3.y = fracv * (1 - fracu )
//CREG_TEXWEIGHT3.z = fracv * (1 - fracu )
226: I = { `COPY ,`CREG_TEXWEIGHT3 ,`R6 ,`VOID };
227: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT3 ,`SWIZZLE_YYY };
 
 
//R4x: fracu
//R4y: fracv
//R4z: fracu * fracv
228: I = { `MULP ,`R4 ,`R4 ,`VOID };
 
//CREG_TEXWEIGHT4.x = fracv * fracu
//CREG_TEXWEIGHT4.y = fracv * fracu
//CREG_TEXWEIGHT4.z = fracv * fracu
229: I = { `COPY ,`CREG_TEXWEIGHT4 ,`R4 ,`VOID };
230: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT4 ,`SWIZZLE_ZZZ };
 
 
//LABEL_TCC_EXIT:
231: I = { `RET ,`R99 ,32'h0 };
 
 
//-------------------------------------------------------------------------
//TAG_PSU_UCODE_ADRESS:
//Pixel Shader #1
//This pixel shader has diffuse light but no textures
 
232: I = { `CROSS ,`R1 ,`CREG_E1_LAST ,`CREG_E2_LAST };
233: I = { `MAG ,`R2 ,`R1 ,`VOID };
234: I = { `DIV ,`R1 ,`R1 ,`R2 };
235: I = { `MUL ,`R2 ,`CREG_RAY_DIRECTION ,`CREG_LAST_t };
236: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
237: I = { `SUB ,`R2 ,`CURRENT_LIGHT_POS ,`R2 };
238: I = { `MAG ,`R3 ,`R2 ,`VOID };
239: I = { `DIV ,`R2 ,`R2 ,`R3 };
240: I = { `DOT ,`R3 ,`R2 ,`R1 };
241: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_TRI_DIFFUSE_LAST ,`CURRENT_LIGHT_DIFFUSE };
242: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_COLOR_ACC ,`R3 };
243: I = { `COPY ,`CREG_TEXTURE_COLOR ,`CREG_COLOR_ACC ,`VOID };
244: I = { `NOP ,`RT_FALSE };
245: I = { `NOP ,`RT_FALSE };
246: I = { `NOP ,`RT_FALSE };
247: I = { `RETURN ,`RT_TRUE };
 
//-------------------------------------------------------------------------
//Pixel Shader #2
//TAG_PSU_UCODE_ADRESS2:
//This Pixel Shader has no light but it does texturinng
//with bi-linear interpolation
 
 
 
248: I = { `COPY ,`R1 ,`CREG_TEX_COORD1 ,`VOID };
249: I = { `COPY ,`R2 ,`CREG_TEX_COORD1 ,`VOID };
250: I = { `COPY ,`R3 ,`CREG_TEX_COORD2 ,`VOID };
251: I = { `COPY ,`R4 ,`CREG_TEX_COORD2 ,`VOID };
 
 
252: I = { `SWIZZLE3D ,`R1 ,`SWIZZLE_XXX };
253: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YYY };
254: I = { `SWIZZLE3D ,`R3 ,`SWIZZLE_XXX };
255: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YYY };
256: I = { `ADD ,`R1 ,`R1 ,`CREG_012 };
257: I = { `ADD ,`R2 ,`R2 ,`CREG_012 };
258: I = { `ADD ,`R3 ,`R3 ,`CREG_012 };
259: I = { `ADD ,`R4 ,`R4 ,`CREG_012 };
 
 
260: I = { `TMREAD ,`CREG_TEX_COLOR1 ,`R1 ,`VOID };
261: I = { `NOP ,`RT_FALSE };
262: I = { `TMREAD ,`CREG_TEX_COLOR2 ,`R2 ,`VOID };
263: I = { `NOP ,`RT_FALSE };
264: I = { `TMREAD ,`CREG_TEX_COLOR3 ,`R3 ,`VOID };
265: I = { `NOP ,`RT_FALSE };
266: I = { `TMREAD ,`CREG_TEX_COLOR4 ,`R4 ,`VOID };
267: I = { `NOP ,`RT_FALSE };
 
 
 
 
//TextureColor.R = c1.R * w1 + c2.R * w2 + c3.R * w3 + c4.R * w4
//TextureColor.G = c1.G * w1 + c2.G * w2 + c3.G * w3 + c4.G * w4
//TextureColor.B = c1.B * w1 + c2.B * w2 + c3.B * w3 + c4.B * w4
 
 
//MUL R1 CREG_TEX_COLOR4 CREG_TEXWEIGHT1
//MUL R2 CREG_TEX_COLOR2 CREG_TEXWEIGHT2
//MUL R3 CREG_TEX_COLOR1 CREG_TEXWEIGHT3
//MUL R4 CREG_TEX_COLOR3 CREG_TEXWEIGHT4
 
268: I = { `MUL ,`R1 ,`CREG_TEX_COLOR3 ,`CREG_TEXWEIGHT1 };
269: I = { `MUL ,`R2 ,`CREG_TEX_COLOR2 ,`CREG_TEXWEIGHT2 };
270: I = { `MUL ,`R3 ,`CREG_TEX_COLOR1 ,`CREG_TEXWEIGHT3 };
271: I = { `MUL ,`R4 ,`CREG_TEX_COLOR4 ,`CREG_TEXWEIGHT4 };
 
272: I = { `ADD ,`CREG_TEXTURE_COLOR ,`R1 ,`R2 };
273: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R3 };
274: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R4 };
275: I = { `RETURN ,`RT_TRUE };
 
 
//-------------------------------------------------------------------------
//Default User constants
//TAG_USERCONSTANTS:
 
276: I = { `NOP ,`RT_FALSE };
277: I = { `RETURN ,`RT_TRUE };
 
//TAG_PIXELSHADER:
//Default Pixel Shader (just outputs texture)
278: I = { `OMWRITE ,`OREG_PIXEL_COLOR ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_TEXTURE_COLOR };
279: I = { `RETURN ,`RT_TRUE };
 
 
//-------------------------------------------------------------------------
 
default:
begin
`ifdef DEBUG
$display("%dns CORE %d Error: Reached undefined address in instruction Memory: %d!!!!",$time,iDebug_CoreID,Address);
// $stop();
`endif
I = {`INSTRUCTION_OP_LENGTH'hFF,16'hFFFF,32'hFFFFFFFF};
end
endcase
end
endmodule
 
 
`define ONE (32'h1 << `SCALE)
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
/*
I can't synthesize roms, the rom needs to be adapted depending on the
final target silicon.
*/
 
 
//--------------------------------------------------------
module ROM
(
input wire[`ROM_ADDRESS_WIDTH-1:0] Address,
`ifdef DEBUG
input wire [`MAX_CORES-1:0] iDebug_CoreID,
`endif
output reg [`INSTRUCTION_WIDTH-1:0] I
);
 
 
always @( Address )
begin
case (Address)
//Hardcoded stuff :(
`define RAY_INSIDE_BOX `R3
`define CURRENT_LIGHT_POS `CREG_FIRST_LIGTH //TODO: CAHNEG T
`define CURRENT_LIGHT_DIFFUSE 16'h6
 
//-----------------------------------------------------------------
`define TAG_PIXELSHADER 16'd310
`define TAG_USERCONSTANTS 16'd308
`define TAG_PSU_UCODE_ADRESS2 16'd280
`define TAG_PSU_UCODE_ADRESS 16'd264
`define LABEL_TCC_EXIT 16'd263
`define TAG_TCC_UCODE_ADDRESS 16'd222
`define LABEL_BIU4 16'd221
`define LABEL_BIU3 16'd211
`define LABEL_BIU2 16'd207
`define LABEL_BIU1 16'd204
`define TAG_BIU_UCODE_ADDRESS 16'd186
`define LABEL_HIT 16'd184
`define LABEL15 16'd182
`define LABEL14 16'd180
`define LABEL13 16'd178
`define LABEL_TEST_XY_PLANE 16'd173
`define LABEL12 16'd171
`define LABEL11 16'd169
`define LABEL10 16'd167
`define LABEL_TEST_XZ_PLANE 16'd161
`define LABEL9 16'd159
`define LABEL8 16'd157
`define LABEL7 16'd155
`define LABEL_TEST_YZ_PLANE 16'd149
`define LABEL_RAY_INSIDE_BOX 16'd146
`define LABEL_ELSEZ 16'd145
`define LABEL6 16'd142
`define LABEL_ELESE_IFZ 16'd138
`define LABEL5 16'd135
`define LABEL_TEST_RAY_Z_ORIGEN 16'd131
`define LABEL_ELSEY 16'd130
`define LABEL4 16'd127
`define LABEL_ELESE_IFY 16'd123
`define LABEL3 16'd120
`define LABEL_TEST_RAY_Y_ORIGEN 16'd116
`define LABEL_ELSEX 16'd115
`define LABEL2 16'd112
`define LABEL_ELSE_IFX 16'd108
`define LABEL1 16'd105
`define LABEL_TEST_RAY_X_ORIGEN 16'd101
`define TAG_AABBIU_UCODE_ADDRESS 16'd98
`define LABEL_ALLDONE 16'd96
`define LABEL_NPG_NEXT_ROW 16'd91
`define TAG_NPG_UCODE_ADDRESS 16'd82
`define TAG_RGU_UCODE_ADDRESS 16'd74
`define TAG_CPPU_UCODE_ADDRESS 16'd70
`define LABEL_MAIN_RENDER_DONE 16'd69
`define LABEL_MAIN_IS_NO_HIT 16'd62
`define LABEL_MAIN_IS_HIT 16'd51
`define LABEL_MAIN_CHECK_HIT 16'd50
`define LABEL_DEC_PRIM_COUNT 16'd47
`define LABEL_MAIN_TEST_INTERSECTION 16'd42
`define TAG_ADRR_MAIN 16'd37
 
 
//-------------------------------------------------------------------------
//Default values for some registers after reset
//-------------------------------------------------------------------------
//This is the first code that gets executed after the machine is
//externally configured ie after the MST_I goes from 1 to zero.
//It sets initial values for some of the internal registers
 
0: I = { `ZERO ,`CREG_LAST_t ,`VOID ,`VOID };
//Set the last 't' to very positive value(500)
1: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
2: I = { `ZERO ,`OREG_PIXEL_COLOR ,`VOID ,`VOID };
3: I = { `COPY ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_INITIAL_POSITION ,`VOID };
 
 
//Calculate the initial linear address for ADR_O
//this is: (X_initial + RESOLUTION_Y*Y_intial) * 3.
//Notice that we need to use 'unscaled' ie. integer
//values because the resuts of the multiplication by
//the resoluction is to large to fit a fixed point
//representation.
 
4: I = { `COPY ,`R1 ,`CREG_RESOLUTION ,`VOID };
5: I = { `UNSCALE ,`R1 ,`R1 ,`VOID };
6: I = { `SETX ,`R1 ,32'h1 };
7: I = { `SETZ ,`R1 ,32'h0 };
8: I = { `COPY ,`R2 ,`CREG_PIXEL_2D_INITIAL_POSITION ,`VOID };
9: I = { `UNSCALE ,`R2 ,`R2 ,`VOID };
 
//Ok lets start by calculating RESOLUTION_Y*Y_intial
10: I = { `IMUL ,`R1 ,`R1 ,`R2 };
11: I = { `COPY ,`R2 ,`R1 ,`VOID };
12: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YYY };
 
//now X_initial + RESOLUTION_Y*Y_intial
13: I = { `ADD ,`R3 ,`R1 ,`R2 };
14: I = { `COPY ,`R2 ,`R1 ,`VOID };
15: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_ZZZ };
16: I = { `ADD ,`R3 ,`R3 ,`R2 };
17: I = { `SWIZZLE3D ,`R3 ,`SWIZZLE_XXX };
 
//finally multiply by 3 to get:
//(X_initial + RESOLUTION_Y*Y_intial) * 3 voila!
18: I = { `SETX ,`R2 ,32'h3 };
19: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_XXX };
20: I = { `IMUL ,`CREG_PIXEL_PITCH ,`R3 ,`R2 };
 
//By this point you should be wondering why not
//just do DOT R1 [1 Resolution_Y 0] [X_intial Y_intial 0 ]?
//well because DOT uses fixed point and the result may not
//fit :(
 
//Transform from fixed point to integer
//UNSCALE CREG_PIXEL_PITCH CREG_PIXEL_PITCH VOID
21: I = { `COPY ,`OREG_ADDR_O ,`CREG_PIXEL_PITCH ,`VOID };
 
22: I = { `SETX ,`CREG_3 ,32'h3 };
23: I = { `SWIZZLE3D ,`CREG_3 ,`SWIZZLE_XXX };
 
24: I = { `SETX ,`CREG_012 ,32'h0 };
25: I = { `SETY ,`CREG_012 ,32'h1 };
26: I = { `SETZ ,`CREG_012 ,32'h2 };
27: I = { `COPY ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_012 ,`VOID };
28: I = { `ZERO ,`CREG_TEXTURE_COLOR ,`VOID ,`VOID };
29: I = { `ZERO ,`CREG_ZERO ,`VOID ,`VOID };
 
30: I = { `ZERO ,`R1 ,`VOID ,`VOID };
31: I = { `ZERO ,`R2 ,`VOID ,`VOID };
32: I = { `ZERO ,`R3 ,`VOID ,`VOID };
33: I = { `ZERO ,`R4 ,`VOID ,`VOID };
34: I = { `ZERO ,`R5 ,`VOID ,`VOID };
35: I = { `ZERO ,`R99 ,`VOID ,`VOID };
 
36: I = { `RETURN ,`RT_TRUE };
 
//---------------------------------------------------------------------
//This is the main sub-routine
//TAG_ADRR_MAIN:
37: I = { `NOP ,`RT_FALSE }; //{ `ZERO ,`CREG_HIT ,`VOID ,`VOID };
//Generate the ray, but this is wrong, it has to generate only once for all the triangles..
38: I = { `JNEX ,`LABEL_MAIN_TEST_INTERSECTION ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES };
39: I = { `CALL ,`ENTRYPOINT_ADRR_RGU ,`VOID ,`VOID };
40: I = { `ZERO ,`CREG_HIT ,`VOID ,`VOID };//{ `NOP ,`RT_FALSE };
41: I = { `RESCALE ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
//LABEL_MAIN_TEST_INTERSECTION:
//Check ofr triangle intersection
42: I = { `NOP ,`RT_FALSE };
43: I = { `CALL ,`ENTRYPOINT_ADRR_BIU ,`VOID ,`VOID };
44: I = { `NOP ,`RT_FALSE };
45: I = { `JEQX ,`LABEL_DEC_PRIM_COUNT ,`R99 ,`CREG_ZERO };
46: I = { `COPY ,`CREG_HIT ,`R99 ,`VOID };
//LABEL_DEC_PRIM_COUNT:
47: I = { `DEC ,`CREG_PRIMITIVE_COUNT ,`CREG_PRIMITIVE_COUNT ,`VOID };
48: I = { `JEQX ,`LABEL_MAIN_CHECK_HIT ,`CREG_PRIMITIVE_COUNT ,`CREG_ZERO };
49: I = { `RETURN ,`RT_FALSE };
//LABEL_MAIN_CHECK_HIT:
50: I = { `JEQX ,`LABEL_MAIN_IS_NO_HIT ,`CREG_HIT ,`CREG_ZERO };
//LABEL_MAIN_IS_HIT:
51: I = { `NOP ,`RT_FALSE };
52: I = { `CALL ,`ENTRYPOINT_ADRR_TCC ,`VOID ,`VOID };
53: I = { `NOP ,`RT_FALSE };
54: I = { `CALL ,`ENTRYPOINT_ADRR_PSU2 ,`VOID ,`VOID };
55: I = { `NOP ,`RT_FALSE };
56: I = { `CALL ,`ENTRYPOINT_ADRR_PIXELSHADER ,`VOID ,`VOID };
57: I = { `NOP ,`RT_FALSE };
58: I = { `CALL ,`ENTRYPOINT_ADRR_NPG ,`VOID ,`VOID };
59: I = { `NOP ,`RT_FALSE };
60: I = { `JEQX ,`LABEL_MAIN_RENDER_DONE ,`R99 ,`CREG_ZERO };
61: I = { `RETURN ,`RT_TRUE };
 
//LABEL_MAIN_IS_NO_HIT:
62: I = { `NOP ,`RT_FALSE };
63: I = { `CALL ,`ENTRYPOINT_ADRR_PIXELSHADER ,`VOID ,`VOID };
64: I = { `NOP ,`RT_FALSE };
65: I = { `CALL ,`ENTRYPOINT_ADRR_NPG ,`VOID ,`VOID };
66: I = { `NOP ,`RT_FALSE };
67: I = { `JNEX ,`LABEL_MAIN_RENDER_DONE ,`R99 ,`CREG_ZERO };
68: I = { `RETURN ,`RT_TRUE };
//LABEL_MAIN_RENDER_DONE:
69: I = { `RETURN ,`RT_TRUE };
 
 
//----------------------------------------------------------------------
//Micro code for CPPU
//TAG_CPPU_UCODE_ADDRESS:
 
 
70: I = { `SUB ,`R1 ,`CREG_PROJECTION_WINDOW_MAX ,`CREG_PROJECTION_WINDOW_MIN };
71: I = { `DIV ,`CREG_PROJECTION_WINDOW_SCALE ,`R1 ,`CREG_RESOLUTION };
72: I = { `COPY ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
73: I = { `RETURN ,`RT_FALSE };
 
//----------------------------------------------------------------------
//Micro code for RGU
//TAG_RGU_UCODE_ADDRESS:
 
 
74: I = { `MUL ,`R1 ,`CREG_PIXEL_2D_POSITION ,`CREG_PROJECTION_WINDOW_SCALE };
75: I = { `ADD ,`R1 ,`R1 ,`CREG_PROJECTION_WINDOW_MIN };
76: I = { `SUB ,`CREG_UNORMALIZED_DIRECTION ,`R1 ,`CREG_CAMERA_POSITION };
77: I = { `MAG ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`VOID };
78: I = { `DIV ,`CREG_RAY_DIRECTION ,`CREG_UNORMALIZED_DIRECTION ,`R2 };
79: I = { `DEC ,`CREG_LAST_COL ,`CREG_PIXEL_2D_FINAL_POSITION ,`VOID };
80: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
81: I = { `RET ,`R99 ,`TRUE };
//----------------------------------------------------------------------
//Next Pixel generation Code (NPG)
//TAG_NPG_UCODE_ADDRESS:
 
82: I = { `COPY ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
 
83: I = { `ZERO ,`CREG_TEXTURE_COLOR ,`VOID ,`VOID };
84: I = { `SETX ,`CREG_TEXTURE_COLOR ,32'h60000 };
85: I = { `ADD ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_3 };
 
86: I = { `ADD ,`CREG_PIXEL_PITCH ,`CREG_PIXEL_PITCH ,`CREG_3 };
87: I = { `COPY ,`OREG_ADDR_O ,`CREG_PIXEL_PITCH ,`VOID };
88: I = { `JGEX ,`LABEL_NPG_NEXT_ROW ,`CREG_PIXEL_2D_POSITION ,`CREG_LAST_COL };
89: I = { `INCX ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
90: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_NPG_NEXT_ROW:
91: I = { `SETX ,`CREG_PIXEL_2D_POSITION ,32'h0 };
92: I = { `INCY ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
93: I = { `JGEY ,`LABEL_ALLDONE ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_FINAL_POSITION };
94: I = { `NOP ,`RT_FALSE };
95: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_ALLDONE:
96: I = { `NOP ,`RT_FALSE };
97: I = { `RET ,`R99 ,`TRUE };
 
//----------------------------------------------------------------------
//Micro code for AABBIU
//TAG_AABBIU_UCODE_ADDRESS:
98: I = { `ZERO ,`R3 ,`VOID ,`VOID };
99: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
100: I = { `RETURN ,`RT_TRUE };
 
//LABEL_TEST_RAY_X_ORIGEN:
101: I = { `JGEX ,`LABEL_ELSE_IFX ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
102: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
103: I = { `JLEX ,`LABEL1 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
104: I = { `RETURN ,`RT_FALSE };
 
//LABEL1:
105: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
106: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
107: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELSE_IFX:
108: I = { `JLEX ,`LABEL_ELSEX ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
109: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
110: I = { `JGEX ,`LABEL2 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
111: I = { `RETURN ,`RT_FALSE };
//LABEL2:
112: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
113: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
114: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
//LABEL_ELSEX:
115: I = { `SETX ,`R5 ,32'b1 };
 
//LABEL_TEST_RAY_Y_ORIGEN:
116: I = { `JGEY ,`LABEL_ELESE_IFY ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
117: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
118: I = { `JLEY ,`LABEL3 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
119: I = { `RETURN ,`RT_FALSE };
 
//LABEL3:
120: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
121: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
122: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELESE_IFY:
123: I = { `JLEY ,`LABEL_ELSEY ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
124: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
125: I = { `JGEY ,`LABEL4 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
126: I = { `RETURN ,`RT_FALSE };
 
//LABEL4:
127: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
128: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
129: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELSEY:
130: I = { `SETY ,`R5 ,32'b1 };
 
//LABEL_TEST_RAY_Z_ORIGEN:
131: I = { `JGEZ ,`LABEL_ELESE_IFZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
132: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
133: I = { `JLEZ ,`LABEL5 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
134: I = { `RETURN ,`RT_FALSE };
 
//LABEL5:
135: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
136: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
137: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
 
//LABEL_ELESE_IFZ:
138: I = { `JLEZ ,`LABEL_ELSEZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
139: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
140: I = { `JGEZ ,`LABEL6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
141: I = { `RETURN ,`RT_FALSE };
 
//LABEL6:
142: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
143: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
144: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
 
//LABEL_ELSEZ:
145: I = { `SETZ ,`R5 ,32'b1 };
 
//LABEL_RAY_INSIDE_BOX:
146: I = { `ZERO ,`R1 ,`VOID ,`VOID };
147: I = { `JEQX ,`LABEL_TEST_YZ_PLANE ,`R1 ,`RAY_INSIDE_BOX };
//BUG need a NOP here else pipeline gets confused
148: I = { `RETURN ,`RT_TRUE };
 
//LABEL_TEST_YZ_PLANE:
149: I = { `JNEX ,`LABEL_TEST_XZ_PLANE ,`R5 ,`R1 };
150: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_XXX };
151: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
152: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
153: I = { `JGEY ,`LABEL7 ,`R2 ,`CREG_AABBMIN };
154: I = { `RETURN ,`RT_FALSE };
 
//LABEL7:
155: I = { `JLEY ,`LABEL8 ,`R2 ,`CREG_AABBMAX };
156: I = { `RETURN ,`RT_FALSE };
 
//LABEL8:
157: I = { `JGEZ ,`LABEL9 ,`R2 ,`CREG_AABBMIN };
158: I = { `RETURN ,`RT_FALSE };
 
//LABEL9:
159: I = { `JLEZ ,`LABEL_TEST_XZ_PLANE ,`R2 ,`CREG_AABBMAX };
160: I = { `RETURN ,`RT_FALSE };
 
//LABEL_TEST_XZ_PLANE:
161: I = { `JNEY ,`LABEL_TEST_XY_PLANE ,`R5 ,`R1 };
162: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_YYY };
163: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
164: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
165: I = { `JGEX ,`LABEL10 ,`R2 ,`CREG_AABBMIN };
166: I = { `RETURN ,`RT_FALSE };
 
//LABEL10:
167: I = { `JLEX ,`LABEL11 ,`R2 ,`CREG_AABBMAX };
168: I = { `RETURN ,`RT_FALSE };
 
//LABEL11:
169: I = { `JGEZ ,`LABEL12 ,`R2 ,`CREG_AABBMIN };
170: I = { `RETURN ,`RT_FALSE };
 
//LABEL12:
171: I = { `JLEZ ,`LABEL_TEST_XY_PLANE ,`R2 ,`CREG_AABBMAX };
172: I = { `RETURN ,`RT_FALSE };
 
//LABEL_TEST_XY_PLANE:
173: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_ZZZ };
174: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
175: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
176: I = { `JGEX ,`LABEL13 ,`R2 ,`CREG_AABBMIN };
177: I = { `RETURN ,`RT_FALSE };
 
//LABEL13:
178: I = { `JLEX ,`LABEL14 ,`R2 ,`CREG_AABBMAX };
179: I = { `RETURN ,`RT_FALSE };
 
//LABEL14:
180: I = { `JGEY ,`LABEL15 ,`R2 ,`CREG_AABBMIN };
181: I = { `RETURN ,`RT_FALSE };
 
//LABEL15:
182: I = { `JLEY ,`LABEL_HIT ,`R2 ,`CREG_AABBMAX };
183: I = { `RETURN ,`RT_FALSE };
 
//LABEL_HIT:
184: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
185: I = { `RETURN ,`RT_TRUE };
 
//------------------------------------------------------------------------
//BIU Micro code
//TAG_BIU_UCODE_ADDRESS:
186: I = { `ZERO ,`OREG_PIXEL_COLOR ,`VOID ,`VOID };
187: I = { `SETX ,`R3 ,`ONE };
188: I = { `SETX ,`R1 ,32'h00000 };
189: I = { `SUB ,`CREG_E1 ,`CREG_V1 ,`CREG_V0 };
190: I = { `SUB ,`CREG_E2 ,`CREG_V2 ,`CREG_V0 };
191: I = { `SUB ,`CREG_T ,`CREG_CAMERA_POSITION ,`CREG_V0 };
192: I = { `CROSS ,`CREG_P ,`CREG_RAY_DIRECTION ,`CREG_E2 };
193: I = { `CROSS ,`CREG_Q ,`CREG_T ,`CREG_E1 };
194: I = { `DOT ,`CREG_H1 ,`CREG_Q ,`CREG_E2 };
195: I = { `DOT ,`CREG_H2 ,`CREG_P ,`CREG_T };
196: I = { `DOT ,`CREG_H3 ,`CREG_Q ,`CREG_RAY_DIRECTION };
197: I = { `DOT ,`CREG_DELTA ,`CREG_P ,`CREG_E1 };
198: I = { `DIV ,`CREG_t ,`CREG_H1 ,`CREG_DELTA };
199: I = { `DIV ,`CREG_u ,`CREG_H2 ,`CREG_DELTA };
200: I = { `DIV ,`CREG_v ,`CREG_H3 ,`CREG_DELTA };
201: I = { `JGEX ,`LABEL_BIU1 ,`CREG_u ,`R1 };
202: I = { `NOP ,`RT_FALSE };
203: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU1:
204: I = { `JGEX ,`LABEL_BIU2 ,`CREG_v ,`R1 };
205: I = { `NOP ,`RT_FALSE };
206: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU2:
207: I = { `ADD ,`R2 ,`CREG_u ,`CREG_v };
208: I = { `JLEX ,`LABEL_BIU3 ,`R2 ,`R3 };
209: I = { `NOP ,`RT_FALSE };
210: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU3:
211: I = { `JGEX ,`LABEL_BIU4 ,`CREG_t ,`CREG_LAST_t };
212: I = { `COPY ,`CREG_LAST_t ,`CREG_t ,`VOID };
213: I = { `COPY ,`CREG_LAST_u ,`CREG_u ,`VOID };
214: I = { `COPY ,`CREG_LAST_v ,`CREG_v ,`VOID };
215: I = { `COPY ,`CREG_E1_LAST ,`CREG_E1 ,`VOID };
216: I = { `COPY ,`CREG_E2_LAST ,`CREG_E2 ,`VOID };
217: I = { `COPY ,`CREG_UV0_LAST ,`CREG_UV0 ,`VOID };
218: I = { `COPY ,`CREG_UV1_LAST ,`CREG_UV1 ,`VOID };
219: I = { `COPY ,`CREG_UV2_LAST ,`CREG_UV2 ,`VOID };
220: I = { `COPY ,`CREG_TRI_DIFFUSE_LAST ,`CREG_TRI_DIFFUSE ,`VOID };
//LABEL_BIU4:
221: I = { `RET ,`R99 ,`TRUE };
 
 
//-------------------------------------------------------------------------
//Calculate the adress of the texure coordiantes.
 
//TAG_TCC_UCODE_ADDRESS:
//Do this calculation only if this triangle is the one closest to the camera
222: I = { `JGX ,`LABEL_TCC_EXIT ,`CREG_t ,`CREG_LAST_t };
 
//First get the UV coodrinates and store in R1
//R1x: u_coordinate = U0 + last_u * (U1 - U0) + last_v * (U2 - U0)
//R1y: v_coordinate = V0 + last_u * (V1 - V0) + last_v * (V2 - V0)
//R1z: 0
 
223: I = { `SUB ,`R1 ,`CREG_UV1_LAST ,`CREG_UV0_LAST };
224: I = { `SUB ,`R2 ,`CREG_UV2_LAST ,`CREG_UV0_LAST };
225: I = { `MUL ,`R1 ,`CREG_LAST_u ,`R1 };
226: I = { `MUL ,`R2 ,`CREG_LAST_v ,`R2 };
227: I = { `ADD ,`R1 ,`R1 ,`R2 };
228: I = { `ADD ,`R1 ,`R1 ,`CREG_UV0_LAST };
 
//R7x : fu = (u_coordinate) * gTexture.mWidth
//R7y : fv = (v_coordinate) * gTexture.mWidth
//R7z : 0
229: I = { `MUL ,`R7 ,`R1 ,`CREG_TEXTURE_SIZE };
 
//R1x: u1 = ((int)fu) % gTexture.mWidth
//R1y: v1 = ((int)fv) % gTexture.mHeight
//R1z: 0
//R2x: u2 = (u1 + 1 ) % gTexture.mWidth
//R2y: v2 = (v2 + 1 ) % gTexture.mHeight
//R2z: 0
// Notice MOD2 only operates over
// numbers that are power of 2 also notice that the
// textures are assumed to be squares!
//x % 2^n == x & (2^n - 1).
 
230: I = { `MOD ,`R1 ,`R7 ,`CREG_TEXTURE_SIZE };
231: I = { `INC ,`R2 ,`R1 ,`VOID };
232: I = { `MOD ,`R2 ,`R2 ,`CREG_TEXTURE_SIZE };
 
//Cool now we should store the values in the appropiate registers
//OREG_TEX_COORD1.x = u1 + v1 * gTexture.mWidth
//OREG_TEX_COORD1.y = u2 + v1 * gTexture.mWidth
//OREG_TEX_COORD1.z = 0
//OREG_TEX_COORD2.x = u1 + v2 * gTexture.mWidth
//OREG_TEX_COORD2.y = u2 + v2 * gTexture.mWidth
//OREG_TEX_COORD1.z = 0
 
//R1= [u1 v1 0]
//R2= [u2 v2 0]
 
//R2 = [v2 u2 0]
233: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YXZ };
 
//R3 = [v2 v1 0]
234: I = { `XCHANGEX ,`R3 ,`R1 ,`R2 };
 
 
//R4 = [u1 u2 0]
235: I = { `XCHANGEX ,`R4 ,`R2 ,`R1 };
 
//R2 = [v2*H v1*H 0]
236: I = { `UNSCALE ,`R9 ,`R3 ,`VOID };
237: I = { `UNSCALE ,`R8 ,`CREG_TEXTURE_SIZE ,`VOID };
238: I = { `IMUL ,`R2 ,`R9 ,`R8 };
 
//OREG_TEX_COORD1 = [u1 + v2*H u2 + v1*H 0]
//R4 = FixedToIinteger(R4)
239: I = { `UNSCALE ,`R4 ,`R4 ,`VOID };
240: I = { `ADD ,`R12 ,`R2 ,`R4 };
241: I = { `SETX ,`R5 ,32'h3 };
242: I = { `SETY ,`R5 ,32'h3 };
243: I = { `SETZ ,`R5 ,32'h3 };
//Multiply by 3 (the pitch)
//IMUL OREG_TEX_COORD1 R12 R5
244: I = { `IMUL ,`CREG_TEX_COORD1 ,`R12 ,`R5 };
 
//R4 = [u2 u1 0]
245: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YXZ };
 
 
//OREG_TEX_COORD2 [u2 + v2*H u1 + v1*H 0]
246: I = { `ADD ,`R12 ,`R2 ,`R4 };
//Multiply by 3 (the pitch)
//IMUL OREG_TEX_COORD2 R12 R5
247: I = { `IMUL ,`CREG_TEX_COORD2 ,`R12 ,`R5 };
 
 
//Cool now get the weights
 
//w1 = (1 - fracu) * (1 - fracv)
//w2 = fracu * (1 - fracv)
//w3 = (1 - fracu) * fracv
//w4 = fracu * fracv
 
//R4x: fracu
//R4y: fracv
//R4z: 0
248: I = { `FRAC ,`R4 ,`R7 ,`VOID };
 
//R5x: fracv
//R5y: fracu
//R5z: 0
249: I = { `COPY ,`R5 ,`R4 ,`VOID };
250: I = { `SWIZZLE3D ,`R5 ,`SWIZZLE_YXZ };
 
 
//R5x: 1 - fracv
//R5y: 1 - fracu
//R5y: 1
251: I = { `NEG ,`R5 ,`R5 ,`VOID };
252: I = { `INC ,`R5 ,`R5 ,`VOID };
 
//R5x: 1 - fracv
//R5y: 1 - fracu
//R5y: (1 - fracv)(1 - fracu)
253: I = { `MULP ,`CREG_TEXWEIGHT1 ,`R5 ,`VOID };
 
//CREG_TEXWEIGHT1.x = (1 - fracv)(1 - fracu)
//CREG_TEXWEIGHT1.y = (1 - fracv)(1 - fracu)
//CREG_TEXWEIGHT1.z = (1 - fracv)(1 - fracu)
254: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT1 ,`SWIZZLE_ZZZ };
 
 
//R6x: w2: fracu * (1 - fracv )
//R6y: w3: fracv * (1 - fracu )
//R6z: 0
255: I = { `MUL ,`R6 ,`R4 ,`R5 };
 
//CREG_TEXWEIGHT2.x = fracu * (1 - fracv )
//CREG_TEXWEIGHT2.y = fracu * (1 - fracv )
//CREG_TEXWEIGHT2.z = fracu * (1 - fracv )
256: I = { `COPY ,`CREG_TEXWEIGHT2 ,`R6 ,`VOID };
257: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT2 ,`SWIZZLE_XXX };
 
//CREG_TEXWEIGHT3.x = fracv * (1 - fracu )
//CREG_TEXWEIGHT3.y = fracv * (1 - fracu )
//CREG_TEXWEIGHT3.z = fracv * (1 - fracu )
258: I = { `COPY ,`CREG_TEXWEIGHT3 ,`R6 ,`VOID };
259: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT3 ,`SWIZZLE_YYY };
 
 
//R4x: fracu
//R4y: fracv
//R4z: fracu * fracv
260: I = { `MULP ,`R4 ,`R4 ,`VOID };
 
//CREG_TEXWEIGHT4.x = fracv * fracu
//CREG_TEXWEIGHT4.y = fracv * fracu
//CREG_TEXWEIGHT4.z = fracv * fracu
261: I = { `COPY ,`CREG_TEXWEIGHT4 ,`R4 ,`VOID };
262: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT4 ,`SWIZZLE_ZZZ };
 
 
//LABEL_TCC_EXIT:
263: I = { `RET ,`R99 ,32'h0 };
 
 
//-------------------------------------------------------------------------
//TAG_PSU_UCODE_ADRESS:
//Pixel Shader #1
//This pixel shader has diffuse light but no textures
 
264: I = { `CROSS ,`R1 ,`CREG_E1_LAST ,`CREG_E2_LAST };
265: I = { `MAG ,`R2 ,`R1 ,`VOID };
266: I = { `DIV ,`R1 ,`R1 ,`R2 };
267: I = { `MUL ,`R2 ,`CREG_RAY_DIRECTION ,`CREG_LAST_t };
268: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
269: I = { `SUB ,`R2 ,`CURRENT_LIGHT_POS ,`R2 };
270: I = { `MAG ,`R3 ,`R2 ,`VOID };
271: I = { `DIV ,`R2 ,`R2 ,`R3 };
272: I = { `DOT ,`R3 ,`R2 ,`R1 };
273: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_TRI_DIFFUSE_LAST ,`CURRENT_LIGHT_DIFFUSE };
274: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_COLOR_ACC ,`R3 };
275: I = { `COPY ,`CREG_TEXTURE_COLOR ,`CREG_COLOR_ACC ,`VOID };
276: I = { `NOP ,`RT_FALSE };
277: I = { `NOP ,`RT_FALSE };
278: I = { `NOP ,`RT_FALSE };
279: I = { `RET ,`R99 ,`TRUE };
 
//-------------------------------------------------------------------------
//Pixel Shader #2
//TAG_PSU_UCODE_ADRESS2:
//This Pixel Shader has no light but it does texturinng
//with bi-linear interpolation
 
 
 
280: I = { `COPY ,`R1 ,`CREG_TEX_COORD1 ,`VOID };
281: I = { `COPY ,`R2 ,`CREG_TEX_COORD1 ,`VOID };
282: I = { `COPY ,`R3 ,`CREG_TEX_COORD2 ,`VOID };
283: I = { `COPY ,`R4 ,`CREG_TEX_COORD2 ,`VOID };
 
 
284: I = { `SWIZZLE3D ,`R1 ,`SWIZZLE_XXX };
285: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YYY };
286: I = { `SWIZZLE3D ,`R3 ,`SWIZZLE_XXX };
287: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YYY };
288: I = { `ADD ,`R1 ,`R1 ,`CREG_012 };
289: I = { `ADD ,`R2 ,`R2 ,`CREG_012 };
290: I = { `ADD ,`R3 ,`R3 ,`CREG_012 };
291: I = { `ADD ,`R4 ,`R4 ,`CREG_012 };
 
 
292: I = { `TMREAD ,`CREG_TEX_COLOR1 ,`R1 ,`VOID };
293: I = { `NOP ,`RT_FALSE };
294: I = { `TMREAD ,`CREG_TEX_COLOR2 ,`R2 ,`VOID };
295: I = { `NOP ,`RT_FALSE };
296: I = { `TMREAD ,`CREG_TEX_COLOR3 ,`R3 ,`VOID };
297: I = { `NOP ,`RT_FALSE };
298: I = { `TMREAD ,`CREG_TEX_COLOR4 ,`R4 ,`VOID };
299: I = { `NOP ,`RT_FALSE };
 
 
 
 
//TextureColor.R = c1.R * w1 + c2.R * w2 + c3.R * w3 + c4.R * w4
//TextureColor.G = c1.G * w1 + c2.G * w2 + c3.G * w3 + c4.G * w4
//TextureColor.B = c1.B * w1 + c2.B * w2 + c3.B * w3 + c4.B * w4
 
 
//MUL R1 CREG_TEX_COLOR4 CREG_TEXWEIGHT1
//MUL R2 CREG_TEX_COLOR2 CREG_TEXWEIGHT2
//MUL R3 CREG_TEX_COLOR1 CREG_TEXWEIGHT3
//MUL R4 CREG_TEX_COLOR3 CREG_TEXWEIGHT4
 
300: I = { `MUL ,`R1 ,`CREG_TEX_COLOR3 ,`CREG_TEXWEIGHT1 };
301: I = { `MUL ,`R2 ,`CREG_TEX_COLOR2 ,`CREG_TEXWEIGHT2 };
302: I = { `MUL ,`R3 ,`CREG_TEX_COLOR1 ,`CREG_TEXWEIGHT3 };
303: I = { `MUL ,`R4 ,`CREG_TEX_COLOR4 ,`CREG_TEXWEIGHT4 };
 
304: I = { `ADD ,`CREG_TEXTURE_COLOR ,`R1 ,`R2 };
305: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R3 };
306: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R4 };
307: I = { `RET ,`R99 ,`TRUE };
 
 
//-------------------------------------------------------------------------
//Default User constants
//TAG_USERCONSTANTS:
 
308: I = { `NOP ,`RT_FALSE };
309: I = { `RETURN ,`RT_FALSE };
 
//TAG_PIXELSHADER:
//Default Pixel Shader (just outputs texture)
310: I = { `OMWRITE ,`OREG_PIXEL_COLOR ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_TEXTURE_COLOR };
311: I = { `NOP ,`RT_FALSE };
312: I = { `RET ,`R99 ,`TRUE };
313: I = { `NOP ,`RT_FALSE };
 
 
//-------------------------------------------------------------------------
 
default:
begin
`ifdef DEBUG
$display("%dns CORE %d Error: Reached undefined address in instruction Memory: %d!!!!",$time,iDebug_CoreID,Address);
// $stop();
`endif
I = {`INSTRUCTION_OP_LENGTH'hFF,16'hFFFF,32'hFFFFFFFF};
end
endcase
end
endmodule
//--------------------------------------------------------
/examples/scenes/example1/Instructions.mem
2,15 → 2,15
//--------------------------------------
//Subroutine Entry Point Table
00000000 00000000 //ENTRYPOINT_ADRR_INITIAL
00000000 0000002C //ENTRYPOINT_ADRR_CPPU
00000000 0000002F //ENTRYPOINT_ADRR_RGU
00000000 00000045 //ENTRYPOINT_ADRR_AABBIU
00000000 0000009D //ENTRYPOINT_ADRR_BIU
00000000 000000E8 //ENTRYPOINT_ADRR_PSU
00000000 000000F8 //ENTRYPOINT_ADRR_PSU2
00000000 000000BE //ENTRYPOINT_ADRR_TCC
00000000 00000037 //ENTRYPOINT_ADRR_NPG
00000000 00000114 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 00000046 //ENTRYPOINT_ADRR_CPPU
00000000 0000004A //ENTRYPOINT_ADRR_RGU
00000000 00000062 //ENTRYPOINT_ADRR_AABBIU
00000000 000000BA //ENTRYPOINT_ADRR_BIU
00000000 00000108 //ENTRYPOINT_ADRR_PSU
00000000 00000118 //ENTRYPOINT_ADRR_PSU2
00000000 000000DE //ENTRYPOINT_ADRR_TCC
00000000 00000052 //ENTRYPOINT_ADRR_NPG
00000000 00000134 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 0000800C //ENTRYPOINT_ADRR_PIXELSHADER
00000000 00000025 //ENTRYPOINT_ADRR_MAIN
//--------------------------------------
/examples/scenes/example2/Instructions.mem
2,15 → 2,15
//--------------------------------------
//Subroutine Entry Point Table
00000000 00000000 //ENTRYPOINT_ADRR_INITIAL
00000000 0000002C //ENTRYPOINT_ADRR_CPPU
00000000 0000002F //ENTRYPOINT_ADRR_RGU
00000000 00000045 //ENTRYPOINT_ADRR_AABBIU
00000000 0000009D //ENTRYPOINT_ADRR_BIU
00000000 000000E8 //ENTRYPOINT_ADRR_PSU
00000000 000000F8 //ENTRYPOINT_ADRR_PSU2
00000000 000000BE //ENTRYPOINT_ADRR_TCC
00000000 00000037 //ENTRYPOINT_ADRR_NPG
00000000 00000114 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 00000046 //ENTRYPOINT_ADRR_CPPU
00000000 0000004A //ENTRYPOINT_ADRR_RGU
00000000 00000062 //ENTRYPOINT_ADRR_AABBIU
00000000 000000BA //ENTRYPOINT_ADRR_BIU
00000000 00000108 //ENTRYPOINT_ADRR_PSU
00000000 00000118 //ENTRYPOINT_ADRR_PSU2
00000000 000000DE //ENTRYPOINT_ADRR_TCC
00000000 00000052 //ENTRYPOINT_ADRR_NPG
00000000 00000134 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 0000800C //ENTRYPOINT_ADRR_PIXELSHADER
00000000 00000025 //ENTRYPOINT_ADRR_MAIN
//--------------------------------------
/examples/scenes/example3/Instructions.mem
2,15 → 2,15
//--------------------------------------
//Subroutine Entry Point Table
00000000 00000000 //ENTRYPOINT_ADRR_INITIAL
00000000 0000002C //ENTRYPOINT_ADRR_CPPU
00000000 0000002F //ENTRYPOINT_ADRR_RGU
00000000 00000045 //ENTRYPOINT_ADRR_AABBIU
00000000 0000009D //ENTRYPOINT_ADRR_BIU
00000000 000000E8 //ENTRYPOINT_ADRR_PSU
00000000 000000F8 //ENTRYPOINT_ADRR_PSU2
00000000 000000BE //ENTRYPOINT_ADRR_TCC
00000000 00000037 //ENTRYPOINT_ADRR_NPG
00000000 00000114 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 00000046 //ENTRYPOINT_ADRR_CPPU
00000000 0000004A //ENTRYPOINT_ADRR_RGU
00000000 00000062 //ENTRYPOINT_ADRR_AABBIU
00000000 000000BA //ENTRYPOINT_ADRR_BIU
00000000 00000108 //ENTRYPOINT_ADRR_PSU
00000000 00000118 //ENTRYPOINT_ADRR_PSU2
00000000 000000DE //ENTRYPOINT_ADRR_TCC
00000000 00000052 //ENTRYPOINT_ADRR_NPG
00000000 00000134 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 0000800C //ENTRYPOINT_ADRR_PIXELSHADER
00000000 00000025 //ENTRYPOINT_ADRR_MAIN
//--------------------------------------

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