URL
https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
Subversion Repositories theia_gpu
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- This comparison shows the changes necessary to convert path
/theia_gpu/trunk
- from Rev 114 to Rev 115
- ↔ Reverse comparison
Rev 114 → Rev 115
/rtl/Collaterals/aDefinitions.v
92,18 → 92,18
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//Internal Entry points (default ROM Address) |
`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero |
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd29 //E |
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd32 //11 |
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd53 //21 |
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd141 //79 |
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd216 //C4 |
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd232 //D4 |
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd174 //9A |
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd39 //18 |
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd44 //E |
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd47 //11 |
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd69 //21 |
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd157 //79 |
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd232 //C4 |
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd248 //D4 |
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd190 //9A |
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd55 //18 |
//User Entry points (default ROM Address) |
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd241 //DD |
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd243 //DF |
`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd245 //E1 |
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd276 //DD |
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd278 //DF |
`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd37 //E1 |
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//Please keep this syntax ENTRYPOINT_INDEX_* because the perl script that |
//parses the user code expects this pattern in order to read in the tokens |
248,8 → 248,10
`define CREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd117 |
`define R99 `DATA_ADDRESS_WIDTH'd118 |
`define CREG_ZERO `DATA_ADDRESS_WIDTH'd119 |
`define CREG_CURRENT_OUTPUT_PIXEL `DATA_ADDRESS_WIDTH'd120 |
`define CREG_3 `DATA_ADDRESS_WIDTH'd121 |
`define CREG_012 `DATA_ADDRESS_WIDTH'd122 |
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//** Ouput registers **// |
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`define OREG_PIXEL_COLOR `DATA_ADDRESS_WIDTH'd128 |