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URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

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  • This comparison shows the changes necessary to convert path
    /theia_gpu/trunk
    from Rev 117 to Rev 118
    Reverse comparison

Rev 117 → Rev 118

/rtl/Collaterals/aDefinitions.v
91,32 → 91,32
//parses the user code expects this pattern in order to read in the tokens
 
//Internal Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd44 //E
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd47 //11
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd69 //21
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd157 //79
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd232 //C4
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd248 //D4
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd190 //9A
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd55 //18
`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd44
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd47
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd69
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd157
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd232
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd248
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd190
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd55
//User Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd276 //DD
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd278 //DF
`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd37 //E1
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd276
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd278
`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd37
 
//Please keep this syntax ENTRYPOINT_INDEX_* because the perl script that
//parses the user code expects this pattern in order to read in the tokens
//Internal subroutines
`define ENTRYPOINT_INDEX_INITIAL `ROM_ADDRESS_WIDTH'h8000
`define ENTRYPOINT_INDEX_CPPU `ROM_ADDRESS_WIDTH'h8001
`define ENTRYPOINT_INDEX_RGU `ROM_ADDRESS_WIDTH'h8002
`define ENTRYPOINT_INDEX_AABBIU `ROM_ADDRESS_WIDTH'h8003
`define ENTRYPOINT_INDEX_BIU `ROM_ADDRESS_WIDTH'h8004
`define ENTRYPOINT_INDEX_PSU `ROM_ADDRESS_WIDTH'h8005
`define ENTRYPOINT_INDEX_PSU2 `ROM_ADDRESS_WIDTH'h8006
`define ENTRYPOINT_INDEX_TCC `ROM_ADDRESS_WIDTH'h8007
`define ENTRYPOINT_INDEX_NPG `ROM_ADDRESS_WIDTH'h8008
`define ENTRYPOINT_INDEX_INITIAL `ROM_ADDRESS_WIDTH'h8000
`define ENTRYPOINT_INDEX_CPPU `ROM_ADDRESS_WIDTH'h8001
`define ENTRYPOINT_INDEX_RGU `ROM_ADDRESS_WIDTH'h8002
`define ENTRYPOINT_INDEX_AABBIU `ROM_ADDRESS_WIDTH'h8003
`define ENTRYPOINT_INDEX_BIU `ROM_ADDRESS_WIDTH'h8004
`define ENTRYPOINT_INDEX_PSU `ROM_ADDRESS_WIDTH'h8005
`define ENTRYPOINT_INDEX_PSU2 `ROM_ADDRESS_WIDTH'h8006
`define ENTRYPOINT_INDEX_TCC `ROM_ADDRESS_WIDTH'h8007
`define ENTRYPOINT_INDEX_NPG `ROM_ADDRESS_WIDTH'h8008
//User defined subroutines
`define ENTRYPOINT_INDEX_USERCONSTANTS `ROM_ADDRESS_WIDTH'h8009
`define ENTRYPOINT_INDEX_PIXELSHADER `ROM_ADDRESS_WIDTH'h800A
367,29 → 367,3
`define SWIZZLE_YXZ 32'd21
 
 
 
 
//`define REG_BUS_OWNED_BY_BCU 0 //0000
`define REG_BUS_OWNED_BY_NULL 0 //0010
`define REG_BUS_OWNED_BY_GFU 1 //0001
`define REG_BUS_OWNED_BY_UCODE 2 //0011
 
/*
`define OP_WIDTH `INSTRUCTION_OP_LENGTH
`define INST_WIDTH 5
*/
/*
`define MULTIPLICATION 0
`define DIVISION 1
*/
 
//Division State Machine Constants
`define INITIAL_DIVISION_STATE 6'd1
`define DIVISION_REVERSE_LAST_ITERATION 6'd2
`define PRE_CALCULATE_REMAINDER 6'd3
`define CALCULATE_REMAINDER 6'd4
`define WRITE_DIVISION_RESULT 6'd5
 
//------------------------------------
 
//endmodule
/rtl/Collaterals/Module_FixedPointDivision.v
2,7 → 2,17
Fixed point Multiplication Module Qm.n
C = (A << n) / B
*/
*/
 
 
//Division State Machine Constants
`define INITIAL_DIVISION_STATE 6'd1
`define DIVISION_REVERSE_LAST_ITERATION 6'd2
`define PRE_CALCULATE_REMAINDER 6'd3
`define CALCULATE_REMAINDER 6'd4
`define WRITE_DIVISION_RESULT 6'd5
 
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
`define FPS_AFTER_RESET_STATE 0

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