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URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

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    /theia_gpu/trunk
    from Rev 62 to Rev 63
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Rev 62 → Rev 63

/rtl/CONTROL/Unit_Control.v
72,6 → 72,12
`define CU_ACK_NPU 39
`define CU_PERFORM_INTIAL_CONFIGURATION 40
`define CU_SET_PICTH 41
`define CU_TRIGGER_USERCONSTANTS 42
`define CU_WAIT_USERCONSTANTS 43
`define CU_ACK_USERCONSTANTS 44
`define CU_TRIGGER_USERPIXELSHADER 45
`define CU_WAIT_FOR_USERPIXELSHADER 46
`define CU_ACK_USERPIXELSHADER 47
 
//--------------------------------------------------------------
module ControlUnit
118,12 → 124,7
end
 
`endif
 
 
//wire[`ROM_ADDRESS_WIDTH-1:0] wAABBIUAddress;
//assign wAABBIUAddress = (iControlRegister[`CR_USER_AABBIU] == 1'b1) ? `USER_AABBIU_UCODE_ADDRESS : `ENTRYPOINT_INDEX_AABBIU;
//--------------------------------------------------------------
FFToggleOnce_1Bit FFTO1
(
385,10 → 386,79
oSetCurrentPitch <= 0;
//oIncCurrentPitch <= 0;
NextState <= `CU_TRIGGER_RGU;//CU_WAIT_FOR_TASK;
NextState <= `CU_TRIGGER_USERCONSTANTS;//CU_WAIT_FOR_TASK;
end
//-----------------------------------------
//TODO:
`CU_TRIGGER_USERCONSTANTS:
begin
`ifdef DEBUG
`LOGME"%d Control: CU_TRIGGER_RGU\n",$time);
`endif
oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer <= `ENTRYPOINT_INDEX_USERCONSTANTS;
oGFUEnable <= 0;
oUCodeEnable <= 1; //*
oIOWritePixel <= 0;
rResetHitFlop <= 0;
rHitFlopEnable <= 0;
oTriggerTFF <= 0;
oSetCurrentPitch <= 0;
//oIncCurrentPitch <= 0;
NextState <= `CU_WAIT_USERCONSTANTS;
end
//-----------------------------------------
`CU_WAIT_USERCONSTANTS:
begin
 
// `ifdef DEBUG
// `LOGME"%d Control: CU_WAIT_FOR_RGU\n",$time);
// `endif
oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer <= `ENTRYPOINT_INDEX_USERCONSTANTS;
oGFUEnable <= 0;
oUCodeEnable <= 0;
oIOWritePixel <= 0;
rResetHitFlop <= 0;
rHitFlopEnable <= 0;
oTriggerTFF <= 0;
oSetCurrentPitch <= 0;
//oIncCurrentPitch <= 0;
if ( iUCodeDone )
NextState <= `CU_ACK_USERCONSTANTS;
else
NextState <= `CU_WAIT_USERCONSTANTS;
end
//-----------------------------------------
`CU_ACK_USERCONSTANTS:
begin
`ifdef DEBUG
`LOGME"%d Control: CU_ACK_RGU\n",$time);
`endif
oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer <= 0;
oGFUEnable <= 0;
oUCodeEnable <= 0; //*
oIOWritePixel <= 0;
rResetHitFlop <= 0;
rHitFlopEnable <= 0;
oTriggerTFF <= 0;
oSetCurrentPitch <= 0;
//oIncCurrentPitch <= 0;
if ( iUCodeDone == 0)
NextState <= `CU_TRIGGER_RGU;
else
NextState <= `CU_ACK_USERCONSTANTS;
end
//-----------------------------------------
`CU_TRIGGER_RGU:
begin
857,7 → 927,7
//oIncCurrentPitch <= 0;
if ( iUCodeDone == 0)
NextState <= `CU_TRIGGER_PCU;
NextState <= `CU_TRIGGER_USERPIXELSHADER;
else
NextState <= `CU_ACK_PSU;
1016,6 → 1086,82
end
//-----------------------------------------
//-----------------------------------------
/*
Here we no longer use GFU so set Enable to zero
*/
`CU_TRIGGER_USERPIXELSHADER:
begin
`ifdef DEBUG
`LOGME"%d Control: CU_TRIGGER_PSU\n",$time);
`endif
oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer <= `ENTRYPOINT_INDEX_PIXELSHADER;
oUCodeEnable <= 1;
oGFUEnable <= 0;//*
oIOWritePixel <= 0;
rResetHitFlop <= 0;
rHitFlopEnable <= 0;
oTriggerTFF <= 0;
oSetCurrentPitch <= 0;
//oIncCurrentPitch <= 0;
NextState <= `CU_WAIT_FOR_USERPIXELSHADER;
end
//-----------------------------------------
`CU_WAIT_FOR_USERPIXELSHADER:
begin
// `ifdef DEBUG
// `LOGME"%d Control: CU_TRIGGER_PSU\n",$time);
// `endif
oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer <= `ENTRYPOINT_INDEX_PIXELSHADER;
oUCodeEnable <= 0;
oGFUEnable <= 0;
oIOWritePixel <= 0;
rResetHitFlop <= 0;
rHitFlopEnable <= 0;
oTriggerTFF <= 0;
oSetCurrentPitch <= 0;
//oIncCurrentPitch <= 0;
if ( iUCodeDone )
NextState <= `CU_ACK_USERPIXELSHADER;
else
NextState <= `CU_WAIT_FOR_USERPIXELSHADER;
end
//-----------------------------------------
`CU_ACK_USERPIXELSHADER:
begin
`ifdef DEBUG
`LOGME"%d Control: CU_ACK_PSU\n",$time);
`endif
oRamBusOwner <= `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer <= 0; //*
oUCodeEnable <= 0; //*
oGFUEnable <= 0;
oIOWritePixel <= 0;
rResetHitFlop <= 0;
rHitFlopEnable <= 0;
oTriggerTFF <= 0;
oSetCurrentPitch <= 0;
//oIncCurrentPitch <= 0;
if ( iUCodeDone == 0)
NextState <= `CU_TRIGGER_PCU;
else
NextState <= `CU_ACK_USERPIXELSHADER;
end
//---------------------------------------------------
default:
begin
/rtl/EXE/Module_ExecutionFSM.v
331,7 → 331,8
`DIV: `LOGME"DIV");
`MUL: `LOGME"MUL");
`MAG: `LOGME"MAG");
`JGX: `LOGME"JGX");
`JGX: `LOGME"JGX");
`JLX: `LOGME"JLX");
`JGEX: `LOGME"JGEX");
`JGEY: `LOGME"JGEY");
`JGEZ: `LOGME"JGEZ");
/rtl/Collaterals/aDefinitions.v
85,8 → 85,10
 
//---------------------------------------------------------------------------------
//Defines the ucode memory entry point for the various ucode routines
//Please keep this syntax ENTRYPOINT_ADDR_* because the perl script that
//parses the user code expects this pattern in order to read in the tokens
 
 
//Internal Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd14 //E
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd17 //11
93,12 → 95,16
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd33 //21
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd121 //79
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd196 //C4
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd212 //D4
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd154 //9A
`define ENTRYPOINT_ADRR_DEBUG_LOG_REGISTERS `ROM_ADDRESS_WIDTH'd221 //DD
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd212 //D4
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd154 //9A
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd24 //18
//User Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd221 //DD
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd223 //DF
 
 
//Please keep this syntax ENTRYPOINT_INDEX_* because the perl script that
//parses the user code expects this pattern in order to read in the tokens
//Internal subroutines
`define ENTRYPOINT_INDEX_INITIAL `ROM_ADDRESS_WIDTH'h8000
`define ENTRYPOINT_INDEX_CPPU `ROM_ADDRESS_WIDTH'h8001
`define ENTRYPOINT_INDEX_RGU `ROM_ADDRESS_WIDTH'h8002
107,8 → 113,10
`define ENTRYPOINT_INDEX_PSU `ROM_ADDRESS_WIDTH'h8005
`define ENTRYPOINT_INDEX_PSU2 `ROM_ADDRESS_WIDTH'h8006
`define ENTRYPOINT_INDEX_TCC `ROM_ADDRESS_WIDTH'h8007
`define ENTRYPOINT_INDEX_DEBUG_LOG_REGISTERS `ROM_ADDRESS_WIDTH'h8008
`define ENTRYPOINT_INDEX_NPG `ROM_ADDRESS_WIDTH'h8009
`define ENTRYPOINT_INDEX_NPG `ROM_ADDRESS_WIDTH'h8008
//User defined subroutines
`define ENTRYPOINT_INDEX_USERCONSTANTS `ROM_ADDRESS_WIDTH'h8009
`define ENTRYPOINT_INDEX_PIXELSHADER `ROM_ADDRESS_WIDTH'h800A
 
`define USER_AABBIU_UCODE_ADDRESS `ROM_ADDRESS_WIDTH'b1000000000000000
//---------------------------------------------------------------------------------
204,11 → 212,11
 
 
//Output registers
`define OREG_PIXEL_COLOR `DATA_ADDRESS_WIDTH'd57 //0032
`define OREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd65 //0032
`define OREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd66 //0032
`define CREG_TEX_COLOR1 `DATA_ADDRESS_WIDTH'd67 //0032
`define CREG_TEX_COLOR2 `DATA_ADDRESS_WIDTH'd68 //0032
`define OREG_PIXEL_COLOR `DATA_ADDRESS_WIDTH'd57
`define OREG_TEX_COORD1 `DATA_ADDRESS_WIDTH'd65
`define OREG_TEX_COORD2 `DATA_ADDRESS_WIDTH'd66
`define CREG_TEX_COLOR1 `DATA_ADDRESS_WIDTH'd67
`define CREG_TEX_COLOR2 `DATA_ADDRESS_WIDTH'd68
`define CREG_TEX_COLOR3 `DATA_ADDRESS_WIDTH'd69
`define CREG_TEX_COLOR4 `DATA_ADDRESS_WIDTH'd70 //This is intentionally COLOR6
`define CREG_TEX_COLOR5 `DATA_ADDRESS_WIDTH'd71
223,6 → 231,14
`define CREG_UV2_LAST `DATA_ADDRESS_WIDTH'd80
`define OREG_PIXEL_PITCH `DATA_ADDRESS_WIDTH'd81
`define CREG_LAST_COL `DATA_ADDRESS_WIDTH'd82 //the last valid column, simply CREG_RESOLUTIONX - 1
`define CREG_TEXTURE_COLOR `DATA_ADDRESS_WIDTH'd83
`define C1 `DATA_ADDRESS_WIDTH'd84
`define C2 `DATA_ADDRESS_WIDTH'd85
`define C3 `DATA_ADDRESS_WIDTH'd86
`define C4 `DATA_ADDRESS_WIDTH'd87
`define C5 `DATA_ADDRESS_WIDTH'd88
`define C6 `DATA_ADDRESS_WIDTH'd89
`define C7 `DATA_ADDRESS_WIDTH'd90
//-------------------------------------------------------------
//*** Instruction Set ***
//The order of the instrucitons is important here!. Don't change
/rtl/Collaterals/Collaterals.v
379,6 → 379,7
end
endmodule
//------------------------------------------------
 
module FF16_POSEDGE_SYNCRONOUS_RESET
(
input wire Clock,
474,6 → 475,7
 
 
//------------------------------------------------
/*
module MUXFULLPARALELL_1Bit_1SEL
(
input wire Sel,
497,7 → 499,9
end
 
endmodule
*/
//--------------------------------------------------------------
/*
module FFD_OPCODE_POSEDGE
(
input wire Clock,
509,7 → 513,9
Q <= D;
endmodule
*/
//--------------------------------------------------------------
/*
module FFD16_POSEDGE
(
input wire Clock,
521,6 → 527,7
Q <= D;
endmodule
*/
//--------------------------------------------------------------
 
module FFT1
/rtl/MEM/Module_ROM.v
524,7 → 524,7
204: I = { `DOT ,`R3 ,`R2 ,`R1 };
205: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_TRI_DIFFUSE_LAST ,`CURRENT_LIGHT_DIFFUSE };
206: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_COLOR_ACC ,`R3 };
207: I = { `COPY ,`OREG_PIXEL_COLOR ,`CREG_COLOR_ACC ,`VOID };
207: I = { `COPY ,`CREG_TEXTURE_COLOR ,`CREG_COLOR_ACC ,`VOID };
208: I = { `JLEX ,`LABEL_DEBUG_PRINT_REGS ,`CREG_COLOR_ACC ,`R3 };
209: I = { `JMP ,`LABEL_DEBUG_PRINT_REGS ,`VOID ,`VOID };
210: I = { `NOP ,`RT_FALSE };//{ `INC ,`OREG_PIXEL_PITCH ,`VOID };
547,34 → 547,21
213: I = { `MUL ,`R2 ,`CREG_TEX_COLOR2 ,`OREG_TEXWEIGHT2 };
214: I = { `MUL ,`R3 ,`CREG_TEX_COLOR1 ,`OREG_TEXWEIGHT3 };
215: I = { `MUL ,`R4 ,`CREG_TEX_COLOR4 ,`OREG_TEXWEIGHT4 };
216: I = { `ADD ,`OREG_PIXEL_COLOR ,`R1 ,`R2 };
217: I = { `ADD ,`OREG_PIXEL_COLOR ,`OREG_PIXEL_COLOR ,`R3 };
218: I = { `ADD ,`OREG_PIXEL_COLOR ,`OREG_PIXEL_COLOR ,`R4 };
219: I = { `RETURN ,`RT_TRUE }; //{ `INC ,`OREG_PIXEL_PITCH ,`VOID };
216: I = { `ADD ,`CREG_TEXTURE_COLOR ,`R1 ,`R2 };
217: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R3 };
218: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R4 };
219: I = { `RETURN ,`RT_TRUE };
 
 
220: I = { `RETURN ,`RT_TRUE };
 
 
//-------------------------------------------------------------------------
//Debug Code
//TAG_DEBUG_LOG_REGISTERS:
 
//LABEL_DEBUG_PRINT_REGS:
/*
221: I = { `DEBUG_PRINT ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
222: I = { `DEBUG_PRINT ,`COLOR_ACC ,`COLOR_ACC ,`VOID };
223: I = { `DEBUG_PRINT ,`CREG_LAST_t ,`CREG_LAST_t ,`VOID };
224: I = { `DEBUG_PRINT ,`CREG_E1_LAST ,`CREG_E1_LAST ,`VOID };
225: I = { `DEBUG_PRINT ,`CREG_E2_LAST ,`CREG_E2_LAST ,`VOID };
226: I = { `DEBUG_PRINT ,`CREG_RAY_DIRECTION ,`CREG_RAY_DIRECTION ,`VOID };
227: I = { `DEBUG_PRINT ,`CREG_CAMERA_POSITION ,`CREG_CAMERA_POSITION ,`VOID };
228: I = { `DEBUG_PRINT ,`CREG_V0 ,`CREG_V0 ,`VOID };
229: I = { `DEBUG_PRINT ,`CREG_V1 ,`CREG_V1 ,`VOID };
230: I = { `DEBUG_PRINT ,`CREG_V2 ,`CREG_V2 ,`VOID };
231: I = { `RETURN ,`RT_TRUE };
*/
 
//-------------------------------------------------------------------------
//Default User constants
221: I = { `NOP ,`RT_FALSE };
222: I = { `RETURN ,`RT_TRUE };
//Default Pixel Shader (just outputs texture)
223: I = {`COPY ,`OREG_PIXEL_COLOR,`CREG_TEXTURE_COLOR,`VOID};
224: I = { `RETURN ,`RT_TRUE };
//-------------------------------------------------------------------------
 

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