URL
https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
Subversion Repositories theia_gpu
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- This comparison shows the changes necessary to convert path
/theia_gpu/trunk
- from Rev 73 to Rev 74
- ↔ Reverse comparison
Rev 73 → Rev 74
/rtl/MEM/Unit_MEM.v
34,23 → 34,41
( |
input wire Clock, |
input wire Reset, |
input wire iDataWriteEnable, |
input wire iFlipMemory, |
|
//Data bus for EXE Unit |
input wire iDataWriteEnable_EXE, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_EXE, |
output wire[`DATA_ROW_WIDTH-1:0] oData1_EXE, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_EXE, |
output wire[`DATA_ROW_WIDTH-1:0] oData2_EXE, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_EXE, |
input wire[`DATA_ROW_WIDTH-1:0] iData_EXE, |
|
//Data bus for IO Unit |
input wire iDataWriteEnable_IO, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1_IO, |
output wire[`DATA_ROW_WIDTH-1:0] oData1_IO, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2_IO, |
output wire[`DATA_ROW_WIDTH-1:0] oData2_IO, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress_IO, |
input wire[`DATA_ROW_WIDTH-1:0] iData_IO, |
|
//Instruction bus |
input wire iInstructionWriteEnable, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress1, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress2, |
input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionWriteAddress, |
input wire [`INSTRUCTION_WIDTH-1:0] iInstruction, |
output wire [`INSTRUCTION_WIDTH-1:0] oInstruction1, |
output wire [`INSTRUCTION_WIDTH-1:0] oInstruction2, |
input wire [`INSTRUCTION_WIDTH-1:0] iInstruction, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1, |
input wire[`DATA_ROW_WIDTH-1:0] oData1, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2, |
input wire[`DATA_ROW_WIDTH-1:0] oData2, |
input wire[`DATA_ADDRESS_WIDTH-1:0] iDataWriteAddress, |
input wire[`DATA_ROW_WIDTH-1:0] iData, |
|
|
//Control Register |
input wire[15:0] iControlRegister, |
output wire[15:0] oControlRegister |
|
|
); |
|
wire [`ROM_ADDRESS_WIDTH-1:0] wROMInstructionAddress,wRAMInstructionAddress; |
78,22 → 96,153
/* |
Data memory. |
*/ |
RAM_128_ROW_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH) DMEM |
`define SMEM_START_ADDR `DATA_ADDRESS_WIDTH'd32 |
`define RMEM_START_ADDR `DATA_ADDRESS_WIDTH'd64 |
`define OMEM_START_ADDR `DATA_ADDRESS_WIDTH'd128 |
|
wire wDataWriteEnable_RMEM,wDataWriteEnable_SMEM,wDataWriteEnable_IMEM,wDataWriteEnable_OMEM; |
wire [`DATA_ADDRESS_WIDTH-1:0] wDataWriteAddress_RMEM,wDataWriteAddress_SMEM; |
wire [`DATA_ADDRESS_WIDTH-1:0] wDataReadAddress_RMEM1,wDataReadAddress_RMEM2; |
wire [`DATA_ADDRESS_WIDTH-1:0] wDataReadAddress_SMEM1,wDataReadAddress_SMEM2; |
wire [`DATA_ROW_WIDTH-1:0] wData_SMEM1,wData_SMEM2,wData_RMEM1,wData_RMEM2,wData_IMEM1,wData_IMEM2; |
wire [`DATA_ROW_WIDTH-1:0] wIOData_SMEM1,wIOData_SMEM2,wData_OMEM1,wData_OMEM2; |
/* |
always @ (posedge Clock) |
begin |
if (wDataWriteEnable_OMEM) |
$display("%dns OMEM Writting %h to Addr %d (%h)", |
$time,iData_EXE,iDataWriteAddress_EXE,iDataWriteAddress_EXE); |
|
//if (iDataReadAddress1_IO >= 130) |
//$display("%dns OMEM Readin %h from %d (%h)", |
//$time,wData_OMEM1,iDataReadAddress1_IO,iDataReadAddress1_IO); |
|
end |
*/ |
assign wDataWriteEnable_OMEM = |
(iDataWriteAddress_EXE >= `OMEM_START_ADDR ) |
? iDataWriteEnable_EXE : 1'b0; |
|
assign wDataWriteEnable_IMEM = |
(iDataWriteAddress_IO < `SMEM_START_ADDR ) |
? iDataWriteEnable_IO : 1'b0; |
|
assign wDataWriteEnable_SMEM = |
(iDataWriteAddress_EXE >= `SMEM_START_ADDR && iDataWriteAddress_EXE < `RMEM_START_ADDR) |
? iDataWriteEnable_EXE : 1'b0; |
|
|
assign wDataWriteEnable_RMEM = |
(iDataWriteAddress_EXE >= `RMEM_START_ADDR && iDataWriteAddress_EXE < `OMEM_START_ADDR) |
? iDataWriteEnable_EXE : 1'b0; |
|
|
assign wDataWriteAddress_RMEM = iDataWriteAddress_EXE; |
assign wDataReadAddress_RMEM1 = iDataReadAddress1_EXE; |
assign wDataReadAddress_RMEM2 = iDataReadAddress2_EXE; |
assign wDataWriteAddress_SMEM = iDataWriteAddress_EXE; |
assign wDataReadAddress_SMEM1 = iDataReadAddress1_EXE; |
assign wDataReadAddress_SMEM2 = iDataReadAddress2_EXE; |
|
//assign oData1_EXE = ( iDataReadAddress1_EXE < `RMEM_START_ADDR ) ? wData_SMEM1 : wData_RMEM1; |
assign oData1_EXE = ( iDataReadAddress1_EXE < `RMEM_START_ADDR ) ? |
( ( iDataReadAddress1_EXE < `SMEM_START_ADDR ) ? wData_IMEM1 : wData_SMEM1 ) |
: wData_RMEM1; |
|
//assign oData2_EXE = ( iDataReadAddress2_EXE < `RMEM_START_ADDR ) ? wData_SMEM2 : wData_RMEM2; |
assign oData2_EXE = ( iDataReadAddress2_EXE < `RMEM_START_ADDR ) ? |
( ( iDataReadAddress2_EXE < `SMEM_START_ADDR ) ? wData_IMEM2 : wData_SMEM2 ) |
: wData_RMEM2; |
|
|
assign oData1_IO = ( iDataReadAddress1_IO < `OMEM_START_ADDR ) ? wIOData_SMEM1 : wData_OMEM1; |
assign oData2_IO = ( iDataReadAddress2_IO < `OMEM_START_ADDR ) ? wIOData_SMEM2 : wData_OMEM2; |
|
//assign oData1_IO = wIOData_SMEM1; |
//assign oData2_IO = wIOData_SMEM2; |
|
//Output registers written by EXE, Read by IO |
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,512) OMEM |
( |
.Clock( Clock ), |
.iWriteEnable( iDataWriteEnable ), |
.iReadAddress0( iDataReadAddress1 ), |
.iReadAddress1( iDataReadAddress2 ), |
.iWriteAddress( iDataWriteAddress ), |
.iDataIn( iData ), |
.oDataOut0( oData1 ), |
.oDataOut1( oData2 ) |
.iWriteEnable( wDataWriteEnable_OMEM ), |
.iReadAddress0( iDataReadAddress1_IO ), |
.iReadAddress1( iDataReadAddress2_IO ), |
.iWriteAddress( iDataWriteAddress_EXE ), |
.iDataIn( iData_EXE ), |
.oDataOut0( wData_OMEM1 ), |
.oDataOut1( wData_OMEM2 ) |
); |
|
//Input Registers, Written by IO, Read by EXE |
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,42) IMEM |
( |
.Clock( Clock ), |
.iWriteEnable( wDataWriteEnable_IMEM ), |
.iReadAddress0( iDataReadAddress1_EXE ), |
.iReadAddress1( iDataReadAddress2_EXE ), |
.iWriteAddress( iDataWriteAddress_IO ), |
.iDataIn( iData_IO ), |
.oDataOut0( wData_IMEM1 ), |
.oDataOut1( wData_IMEM2 ) |
); |
|
//Swap registers, while IO writes/write values, EXE reads/write values |
//the pointers get filped in the next iteration |
SWAP_MEM # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,512) SMEM |
( |
.Clock( Clock ), |
.iSelect( wFlipSelect ), |
|
.iWriteEnableA( wDataWriteEnable_SMEM ), |
.iReadAddressA0( wDataReadAddress_SMEM1 ), |
.iReadAddressA1( wDataReadAddress_SMEM2 ), |
.iWriteAddressA( wDataWriteAddress_SMEM ), |
.iDataInA( iData_EXE ), |
.oDataOutA0( wData_SMEM1 ), |
.oDataOutA1( wData_SMEM2 ), |
|
.iWriteEnableB( iDataWriteEnable_IO ), |
.iReadAddressB0( iDataReadAddress1_IO ), |
.iReadAddressB1( iDataReadAddress2_IO ), |
.iWriteAddressB( iDataWriteAddress_IO ), |
.iDataInB( iData_IO ), |
.oDataOutB0( wIOData_SMEM1 ), |
.oDataOutB1( wIOData_SMEM2 ) |
|
); |
|
//General purpose registers, EXE can R/W, IO can not see these sections |
//of the memory |
RAM_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH,256) RMEM |
( |
.Clock( Clock ), |
.iWriteEnable( wDataWriteEnable_RMEM ), |
.iReadAddress0( wDataReadAddress_RMEM1 ), |
.iReadAddress1( wDataReadAddress_RMEM2 ), |
.iWriteAddress( wDataWriteAddress_RMEM ), |
.iDataIn( iData_EXE ), |
.oDataOut0( wData_RMEM1 ), |
.oDataOut1( wData_RMEM2 ) |
); |
|
wire wFlipSelect; |
UPCOUNTER_POSEDGE # (1) UPC1 |
( |
.Clock(Clock), |
.Reset( Reset ), |
.Initial(1'b0), |
.Enable(iFlipMemory), |
.Q(wFlipSelect) |
); |
|
|
|
//------------------------------------------------------------------- |
/* |
Instruction memory. |
*/ |
RAM_128_ROW_DUAL_READ_PORT # (`INSTRUCTION_WIDTH,`ROM_ADDRESS_WIDTH) IMEM |
RAM_DUAL_READ_PORT # (`INSTRUCTION_WIDTH,`ROM_ADDRESS_WIDTH,512) INST_MEM |
( |
.Clock( Clock ), |
.iWriteEnable( iInstructionWriteEnable ), |
/rtl/MEM/Module_ROM.v
104,7 → 104,7
//Set the last 't' to very positive value(500) |
1: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 }; |
2: I = { `ZERO ,`OREG_PIXEL_COLOR ,`VOID ,`VOID }; |
3: I = { `NOP ,`RT_FALSE }; //{ `ZERO ,`CREG_PIXEL_2D_POSITION ,`VOID ,`VOID }; |
3: I = { `COPY ,`CREG_PIXEL_2D_POSITION,`CREG_PIXEL_2D_INITIAL_POSITION, `VOID }; |
4: I = { `ZERO ,`OREG_PIXEL_PITCH ,`VOID,`VOID}; |
5: I = { `ZERO ,`R1 ,`VOID ,`VOID }; |
6: I = { `ZERO ,`R2 ,`VOID ,`VOID }; |
114,8 → 114,9
//Harode texture size for now ... |
10: I = { `NOP ,`RT_FALSE };//{ `SETX ,`CREG_TEXTURE_SIZE ,32'h1FE0000 }; |
11: I = { `NOP ,`RT_FALSE };//{ `SETY ,`CREG_TEXTURE_SIZE ,32'h1FE0000 }; |
12: I = { `NOP ,`RT_FALSE };//{ `SETZ ,`CREG_TEXTURE_SIZE ,32'h1FE0000 }; |
13: I = { `RETURN ,`RT_TRUE }; |
12: I = { `RETURN ,`RT_TRUE }; |
13: I = { `NOP ,`RT_FALSE };//{ `SETZ ,`CREG_TEXTURE_SIZE ,32'h1FE0000 }; |
|
|
|
//---------------------------------------------------------------------- |
160,8 → 161,8
//TAG_AABBIU_UCODE_ADDRESS: |
|
33: I = { `ZERO ,`R3 ,`VOID ,`VOID }; |
34: I = { `ZERO ,`R5 ,`VOID ,`VOID }; |
35: I = { `NOP ,`RT_FALSE }; |
34: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 }; //{ `ZERO ,`R5 ,`VOID ,`VOID }; |
35: I = { `RETURN ,`RT_TRUE };//{ `ZERO ,`R6, `VOID, `VOID }; |
|
//LABEL_TEST_RAY_X_ORIGEN: |
36: I = { `JGEX ,`LABEL_ELSE_IFX ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN }; |
240,6 → 241,7
//LABEL_RAY_INSIDE_BOX: |
81: I = { `ZERO ,`R1 ,`VOID ,`VOID }; |
82: I = { `JEQX ,`LABEL_TEST_YZ_PLANE ,`R1 ,`RAY_INSIDE_BOX }; |
//BUG, need a NOP here, else pipeline gets confused |
83: I = { `RETURN ,`RT_TRUE }; |
|
//LABEL_TEST_YZ_PLANE: |
368,7 → 370,7
157: I = { `MUL ,`R1 ,`CREG_LAST_u ,`R1 }; |
158: I = { `MUL ,`R2 ,`CREG_LAST_v ,`R2 }; |
159: I = { `ADD ,`R1 ,`R1 ,`R2 }; |
160: I = { `ADD ,`R1 ,`R1 ,`CREG_UV0 }; |
160: I = { `ADD ,`R1 ,`R1 ,`CREG_UV0_LAST }; |
|
//R7x : fu = (u_coordinate) * gTexture.mWidth; |
//R7y : fv = (v_coordinate) * gTexture.mWidth; |
412,7 → 414,6
167: I = { `XCHANGEX ,`R4 ,`R2 ,`R1 }; |
|
//R2 = [v2*H, v1*H, 0] |
//R2 = FixedToInteger(R3*CREG_TEXTURE_SIZE) |
168: I = { `UNSCALE ,`R9 ,`R3 ,`VOID }; |
169: I = { `UNSCALE ,`R8 ,`CREG_TEXTURE_SIZE ,`VOID }; |
170: I = { `IMUL ,`R2 ,`R9 ,`R8 }; |
420,12 → 421,12
//OREG_TEX_COORD1 = [u1 + v2*H, u2 + v1*H, 0] |
//R4 = FixedToIinteger(R4) |
171: I = { `UNSCALE ,`R4 ,`R4 ,`VOID }; |
172: I = { `ADD ,`OREG_TEX_COORD1 ,`R2 ,`R4 }; |
172: I = { `ADD ,`R12 ,`R2 ,`R4 }; // { `ADD ,`OREG_TEX_COORD1 ,`R2 ,`R4 }; |
173: I = { `SETX ,`R5 ,32'h3 }; |
174: I = { `SETY ,`R5 ,32'h3 }; |
175: I = { `SETZ ,`R5 ,32'h3 }; |
//Multiply by 3 (the pitch) |
176: I = { `IMUL ,`OREG_TEX_COORD1 ,`OREG_TEX_COORD1 ,`R5 }; |
176: I = { `IMUL ,`OREG_TEX_COORD1 ,`R12 ,`R5 }; |
|
//R4 = [u2 u1 0] |
177: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YXZ }; |
432,9 → 433,9
|
|
//OREG_TEX_COORD2 [u2 + v2*H, u1 + v1*H, 0] |
178: I = { `ADD ,`OREG_TEX_COORD2 ,`R2 ,`R4 }; |
178: I = { `ADD ,`R12 ,`R2 ,`R4 }; |
//Multiply by 3 (the pitch) |
179: I = { `IMUL ,`OREG_TEX_COORD2 ,`OREG_TEX_COORD2 ,`R5 }; |
179: I = { `IMUL ,`OREG_TEX_COORD2 ,`R12 ,`R5 }; |
|
|
//Cool now get the weights |
465,12 → 466,12
//R5x: 1 - fracv |
//R5y: 1 - fracu |
//R5y: (1 - fracv)(1 - fracu) |
185: I = { `MULP ,`OREG_TEXWEIGHT1 ,`R5 ,`VOID }; |
185: I = { `MULP ,`CREG_TEXWEIGHT1 ,`R5 ,`VOID }; |
|
//OREG_TEXWEIGHT1.x = (1 - fracv)(1 - fracu) |
//OREG_TEXWEIGHT1.y = (1 - fracv)(1 - fracu) |
//OREG_TEXWEIGHT1.z = (1 - fracv)(1 - fracu) |
186: I = { `SWIZZLE3D ,`OREG_TEXWEIGHT1 ,`SWIZZLE_ZZZ }; |
//CREG_TEXWEIGHT1.x = (1 - fracv)(1 - fracu) |
//CREG_TEXWEIGHT1.y = (1 - fracv)(1 - fracu) |
//CREG_TEXWEIGHT1.z = (1 - fracv)(1 - fracu) |
186: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT1 ,`SWIZZLE_ZZZ }; |
|
|
//R6x: w2: fracu * (1 - fracv ) |
478,17 → 479,17
//R6z: 0 |
187: I = { `MUL ,`R6 ,`R4 ,`R5 }; |
|
//OREG_TEXWEIGHT2.x = fracu * (1 - fracv ) |
//OREG_TEXWEIGHT2.y = fracu * (1 - fracv ) |
//OREG_TEXWEIGHT2.z = fracu * (1 - fracv ) |
188: I = { `COPY ,`OREG_TEXWEIGHT2 ,`R6 ,`VOID }; |
189: I = { `SWIZZLE3D ,`OREG_TEXWEIGHT2 ,`SWIZZLE_XXX }; |
//CREG_TEXWEIGHT2.x = fracu * (1 - fracv ) |
//CREG_TEXWEIGHT2.y = fracu * (1 - fracv ) |
//CREG_TEXWEIGHT2.z = fracu * (1 - fracv ) |
188: I = { `COPY ,`CREG_TEXWEIGHT2 ,`R6 ,`VOID }; |
189: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT2 ,`SWIZZLE_XXX }; |
|
//OREG_TEXWEIGHT3.x = fracv * (1 - fracu ) |
//OREG_TEXWEIGHT3.y = fracv * (1 - fracu ) |
//OREG_TEXWEIGHT3.z = fracv * (1 - fracu ) |
190: I = { `COPY ,`OREG_TEXWEIGHT3 ,`R6 ,`VOID }; |
191: I = { `SWIZZLE3D ,`OREG_TEXWEIGHT3 ,`SWIZZLE_YYY }; |
//CREG_TEXWEIGHT3.x = fracv * (1 - fracu ) |
//CREG_TEXWEIGHT3.y = fracv * (1 - fracu ) |
//CREG_TEXWEIGHT3.z = fracv * (1 - fracu ) |
190: I = { `COPY ,`CREG_TEXWEIGHT3 ,`R6 ,`VOID }; |
191: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT3 ,`SWIZZLE_YYY }; |
|
|
//R4x: fracu |
496,11 → 497,11
//R4z: fracu * fracv |
192: I = { `MULP ,`R4 ,`R4 ,`VOID }; |
|
//OREG_TEXWEIGHT4.x = fracv * fracu |
//OREG_TEXWEIGHT4.y = fracv * fracu |
//OREG_TEXWEIGHT4.z = fracv * fracu |
193: I = { `COPY ,`OREG_TEXWEIGHT4 ,`R4 ,`VOID }; |
194: I = { `SWIZZLE3D ,`OREG_TEXWEIGHT4 ,`SWIZZLE_ZZZ }; |
//CREG_TEXWEIGHT4.x = fracv * fracu |
//CREG_TEXWEIGHT4.y = fracv * fracu |
//CREG_TEXWEIGHT4.z = fracv * fracu |
193: I = { `COPY ,`CREG_TEXWEIGHT4 ,`R4 ,`VOID }; |
194: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT4 ,`SWIZZLE_ZZZ }; |
|
|
//LABEL_TCC_EXIT: |
543,10 → 544,10
//TextureColor.G = c1.G * w1 + c2.G * w2 + c3.G * w3 + c4.G * w4; |
//TextureColor.B = c1.B * w1 + c2.B * w2 + c3.B * w3 + c4.B * w4; |
|
212: I = { `MUL ,`R1 ,`CREG_TEX_COLOR5 ,`OREG_TEXWEIGHT1 }; |
213: I = { `MUL ,`R2 ,`CREG_TEX_COLOR2 ,`OREG_TEXWEIGHT2 }; |
214: I = { `MUL ,`R3 ,`CREG_TEX_COLOR1 ,`OREG_TEXWEIGHT3 }; |
215: I = { `MUL ,`R4 ,`CREG_TEX_COLOR4 ,`OREG_TEXWEIGHT4 }; |
212: I = { `MUL ,`R1 ,`CREG_TEX_COLOR5 ,`CREG_TEXWEIGHT1 }; |
213: I = { `MUL ,`R2 ,`CREG_TEX_COLOR2 ,`CREG_TEXWEIGHT2 }; |
214: I = { `MUL ,`R3 ,`CREG_TEX_COLOR1 ,`CREG_TEXWEIGHT3 }; |
215: I = { `MUL ,`R4 ,`CREG_TEX_COLOR4 ,`CREG_TEXWEIGHT4 }; |
216: I = { `ADD ,`CREG_TEXTURE_COLOR ,`R1 ,`R2 }; |
217: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R3 }; |
218: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R4 }; |
/rtl/MEM/Module_RAM.v
23,7 → 23,7
//Dual port RAM. |
|
|
module RAM_128_ROW_DUAL_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH ) |
module RAM_DUAL_READ_PORT # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 ) |
( |
input wire Clock, |
input wire iWriteEnable, |
35,7 → 35,7
output reg [DATA_WIDTH-1:0] oDataOut1 |
); |
|
reg [DATA_WIDTH-1:0] Ram [128:0]; |
reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0]; |
|
always @(posedge Clock) |
begin |
/rtl/MEM/Module_SwapMemory.v
0,0 → 1,90
`timescale 1ns / 1ps |
`include "aDefinitions.v" |
|
module SWAP_MEM # ( parameter DATA_WIDTH=`DATA_ROW_WIDTH, parameter ADDR_WIDTH=`DATA_ADDRESS_WIDTH, parameter MEM_SIZE=128 ) |
( |
input wire Clock, |
input wire iSelect, |
input wire iWriteEnableA, |
input wire[ADDR_WIDTH-1:0] iReadAddressA0, |
input wire[ADDR_WIDTH-1:0] iReadAddressA1, |
input wire[ADDR_WIDTH-1:0] iWriteAddressA, |
input wire[DATA_WIDTH-1:0] iDataInA, |
output wire [DATA_WIDTH-1:0] oDataOutA0, |
output wire [DATA_WIDTH-1:0] oDataOutA1, |
|
|
input wire iWriteEnableB, |
input wire[ADDR_WIDTH-1:0] iReadAddressB0, |
input wire[ADDR_WIDTH-1:0] iReadAddressB1, |
input wire[ADDR_WIDTH-1:0] iWriteAddressB, |
input wire[DATA_WIDTH-1:0] iDataInB, |
output wire [DATA_WIDTH-1:0] oDataOutB0, |
output wire [DATA_WIDTH-1:0] oDataOutB1 |
); |
|
|
wire wWriteEnableA; |
wire[ADDR_WIDTH-1:0] wReadAddressA0; |
wire[ADDR_WIDTH-1:0] wReadAddressA1; |
wire[ADDR_WIDTH-1:0] wWriteAddressA; |
wire[DATA_WIDTH-1:0] wDataInA; |
wire [DATA_WIDTH-1:0] wDataOutA0; |
wire [DATA_WIDTH-1:0] wDataOutA1; |
|
wire wWriteEnableB; |
wire[ADDR_WIDTH-1:0] wReadAddressB0; |
wire[ADDR_WIDTH-1:0] wReadAddressB1; |
wire[ADDR_WIDTH-1:0] wWriteAddressB; |
wire[DATA_WIDTH-1:0] wDataInB; |
wire [DATA_WIDTH-1:0] wDataOutB0; |
wire [DATA_WIDTH-1:0] wDataOutB1; |
|
|
assign wWriteEnableA = ( iSelect ) ? iWriteEnableA : iWriteEnableB; |
assign wWriteEnableB = ( ~iSelect ) ? iWriteEnableA : iWriteEnableB; |
|
assign wReadAddressA0 = ( iSelect ) ? iReadAddressA0 : iReadAddressB0; |
assign wReadAddressB0 = ( ~iSelect ) ? iReadAddressA0 : iReadAddressB0; |
|
assign wReadAddressA1 = ( iSelect ) ? iReadAddressA1 : iReadAddressB1; |
assign wReadAddressB1 = ( ~iSelect ) ? iReadAddressA1 : iReadAddressB1; |
|
assign wWriteAddressA = ( iSelect ) ? iWriteAddressA : iWriteAddressB; |
assign wWriteAddressB = ( ~iSelect ) ? iWriteAddressA : iWriteAddressB; |
|
assign wDataInA = ( iSelect ) ? iDataInA : iDataInB; |
assign wDataInB = ( ~iSelect ) ? iDataInA : iDataInB; |
|
assign oDataOutA0 = ( iSelect ) ? wDataOutA0 : wDataOutB0; |
assign oDataOutB0 = ( ~iSelect ) ? wDataOutA0 : wDataOutB0; |
|
assign oDataOutA1 = ( iSelect ) ? wDataOutA1 : wDataOutB1; |
assign oDataOutB1 = ( ~iSelect ) ? wDataOutA1 : wDataOutB1; |
|
RAM_DUAL_READ_PORT # (DATA_WIDTH,ADDR_WIDTH,MEM_SIZE) MEM_A |
( |
.Clock( Clock ), |
.iWriteEnable( wWriteEnableA ), |
.iReadAddress0( wReadAddressA0 ), |
.iReadAddress1( wReadAddressA1 ), |
.iWriteAddress( wWriteAddressA ), |
.iDataIn( wDataInA ), |
.oDataOut0( wDataOutA0 ), |
.oDataOut1( wDataOutA1 ) |
); |
|
|
RAM_DUAL_READ_PORT # (DATA_WIDTH,ADDR_WIDTH,MEM_SIZE) MEM_B |
( |
.Clock( Clock ), |
.iWriteEnable( wWriteEnableB ), |
.iReadAddress0( wReadAddressB0 ), |
.iReadAddress1( wReadAddressB1 ), |
.iWriteAddress( wWriteAddressB ), |
.iDataIn( wDataInB ), |
.oDataOut0( wDataOutB0 ), |
.oDataOut1( wDataOutB1 ) |
); |
|
endmodule |