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/branches/icarus_version/testbench/TestBench_verilog.v
1,291 → 1,291
 
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
 
/*******************************************************************************
Module Description:
 
This is the Main test bench of the GPU. It simulates the behavior of
an external control unit or CPU that sends configuration information into DUT.
It also implements a second processs that simulates a Wishbone slave that sends
data from an external memory. These blocks are just behavioral CTE and therefore
are not meant to be synthethized.
 
*******************************************************************************/
 
 
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
`define RESOLUTION_WIDTH (rSceneParameters[13] >> `SCALE)
`define RESOLUTION_HEIGHT (rSceneParameters[14] >> `SCALE)
`define DELTA_ROW (32'h1 << `SCALE)
`define DELTA_COL (32'h1 << `SCALE)
`define TEXTURE_BUFFER_SIZE (256*256*3)
`define MAX_WIDTH 200
`define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
module TestBench_Theia;
 
 
//------------------------------------------------------------------------
//**WARNING: Declare all of your varaibles at the begining
//of the file. I hve noticed that sometimes the verilog
//simulator allows you to use some regs even if they have not been
//previously declared, leadeing to crahses or unexpected behavior
// Inputs
reg Clock;
reg Reset;
wire [`WB_WIDTH-1:0] DAT_O;
reg ACK_O;
wire ACK_I;
wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
wire WE_I,STB_I;
wire CYC_O,WE_O,TGC_O,STB_O;
wire [1:0] TGA_O;
wire [1:0] TGA_I;
reg [`WB_WIDTH-1:0] TMADR_O,TMDAT_O;
reg [`MAX_TMEM_BANKS-1:0] TMSEL_O;
reg TMWE_O;
reg [31:0] rControlRegister[2:0];
integer file, log;
reg [31:0] rSceneParameters[120:0];
reg [31:0] rVertexBuffer[7000:0];
reg [31:0] rInstructionBuffer[512:0];
reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
wire wDone;
wire [`MAX_CORES-1:0] RENDREN_O;
reg [`MAX_CORE_BITS-1:0] wOMEMBankSelect;
reg [`WB_WIDTH-1:0] wOMEMReadAddr; //Output adress (relative to current bank)
wire [`WB_WIDTH-1:0] wOMEMData; //Output data bus (Wishbone)
reg rHostEnable;
integer k,out2;
wire GRDY_I;
wire GACK_O;
wire STDONE_O;
wire wGPUCommitedResults;
wire wHostDataAvailable;
 
 
/**********************************************************************************
Theia, Ray Cast Programable graphic Processing Unit.
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
 
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
 
***********************************************************************************/
 
 
/*******************************************************************************
Module Description:
 
This is the Main test bench of the GPU. It simulates the behavior of
an external control unit or CPU that sends configuration information into DUT.
It also implements a second processs that simulates a Wishbone slave that sends
data from an external memory. These blocks are just behavioral CTE and therefore
are not meant to be synthethized.
 
*******************************************************************************/
 
 
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
`define RESOLUTION_WIDTH (rSceneParameters[13] >> `SCALE)
`define RESOLUTION_HEIGHT (rSceneParameters[14] >> `SCALE)
`define DELTA_ROW (32'h1 << `SCALE)
`define DELTA_COL (32'h1 << `SCALE)
`define TEXTURE_BUFFER_SIZE (256*256*3)
`define MAX_WIDTH 200
`define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
module TestBench_Theia;
 
 
//------------------------------------------------------------------------
//**WARNING: Declare all of your varaibles at the begining
//of the file. I hve noticed that sometimes the verilog
//simulator allows you to use some regs even if they have not been
//previously declared, leadeing to crahses or unexpected behavior
// Inputs
reg Clock;
reg Reset;
wire [`WB_WIDTH-1:0] DAT_O;
reg ACK_O;
wire ACK_I;
wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
wire WE_I,STB_I;
wire CYC_O,WE_O,TGC_O,STB_O;
wire [1:0] TGA_O;
wire [1:0] TGA_I;
reg [`WB_WIDTH-1:0] TMADR_O,TMDAT_O;
reg [`MAX_TMEM_BANKS-1:0] TMSEL_O;
reg TMWE_O;
reg [31:0] rControlRegister[2:0];
integer file, log;
reg [31:0] rSceneParameters[120:0];
reg [31:0] rVertexBuffer[7000:0];
reg [31:0] rInstructionBuffer[512:0];
reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
wire wDone;
wire [`MAX_CORES-1:0] RENDREN_O;
reg [`MAX_CORE_BITS-1:0] wOMEMBankSelect;
reg [`WB_WIDTH-1:0] wOMEMReadAddr; //Output adress (relative to current bank)
wire [`WB_WIDTH-1:0] wOMEMData; //Output data bus (Wishbone)
reg rHostEnable;
integer k,out2;
wire GRDY_I;
wire GACK_O;
wire STDONE_O;
wire wGPUCommitedResults;
wire wHostDataAvailable;
 
 
wire[`WB_WIDTH-1:0] wHostReadAddress;
wire[`WB_WIDTH-1:0] wMemorySize;
wire[`WB_WIDTH-1:0] wMemorySize;
wire[1:0] wMemSelect;
 
MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX2
(
.Sel( wMemSelect ),
.I1( rInstructionBuffer[0] ),
.I2( rSceneParameters[0] ),
.I3( rVertexBuffer[0] ),
.I4(0),
.O1(wMemorySize)
 
MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX2
(
.Sel( wMemSelect ),
.I1( rInstructionBuffer[0] ),
.I2( rSceneParameters[0] ),
.I3( rVertexBuffer[0] ),
.I4(0),
.O1(wMemorySize)
);
//---------------------------------------------
top Top
(
.Clock( Clock ),
.Reset( Reset ),
.iHostEnable( rHostEnable ),
.oHostReadAddress( wHostReadAddress),
//---------------------------------------------
top Top
(
.Clock( Clock ),
.Reset( Reset ),
.iHostEnable( rHostEnable ),
.oHostReadAddress( wHostReadAddress),
.iMemorySize( wMemorySize ),
.oMemSelect( wMemSelect ),
.iInstruction( rInstructionBuffer[wHostReadAddress] ),
.iParameter( rSceneParameters[wHostReadAddress] ),
.iVertex( rVertexBuffer[wHostReadAddress] ),
.iControlRegister( rControlRegister[0] ),
.iPrimitiveCount( (rVertexBuffer[6]+1) *7 ),
.iTMEMAdr( TMADR_O ),
.iTMEMData( TMDAT_O ),
.iTMEM_WE( TMWE_O ),
.oMemSelect( wMemSelect ),
.iInstruction( rInstructionBuffer[wHostReadAddress] ),
.iParameter( rSceneParameters[wHostReadAddress] ),
.iVertex( rVertexBuffer[wHostReadAddress] ),
.iControlRegister( rControlRegister[0] ),
.iPrimitiveCount( (rVertexBuffer[6]+1) *7 ),
.iTMEMAdr( TMADR_O ),
.iTMEMData( TMDAT_O ),
.iTMEM_WE( TMWE_O ),
.iTMEM_Sel( TMSEL_O ),
.iOMEMBankSelect( wOMEMBankSelect ),
.iOMEMReadAddress( wOMEMReadAddr ),
.iOMEMReadAddress( wOMEMReadAddr ),
.oOMEMData( wOMEMData ),
 
.iWidth(`RESOLUTION_WIDTH),
.iHeight(`RESOLUTION_HEIGHT),
.oDone( wDone )
 
 
);
//---------------------------------------------
//generate the clock signal here
always begin
#`CLOCK_CYCLE Clock = ! Clock;
end
//---------------------------------------------
 
//-------------------------------------------------------------------------------------
/*
This makes sure the simulation actually writes the results to the PPM image file
once all the cores are done executing
*/
`define PARTITION_SIZE `RESOLUTION_HEIGHT/`MAX_CORES
integer i,j,kk;
reg [31:0] R;
always @ ( * )
begin
 
 
if (wDone == 1'b1)
begin
 
$display("Partition Size = %d",`PARTITION_SIZE);
for (kk = 0; kk < `MAX_CORES; kk = kk+1)
begin
wOMEMBankSelect = kk;
$display("wOMEMBankSelect = %d\n",wOMEMBankSelect);
for (j=0; j < `PARTITION_SIZE; j=j+1)
begin
for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
begin
wOMEMReadAddr = i+j*`RESOLUTION_WIDTH*3;
#`CLOCK_PERIOD;
#1;
R = ((wOMEMData >> (`SCALE-8)) > 255) ? 255 : (wOMEMData >> (`SCALE-8));
$fwrite(out2,"%d " , R );
 
if ((i %3) == 0)
$fwrite(out2,"\n# %d %d\n",i/3,j);
end
end
end
 
.iWidth(`RESOLUTION_WIDTH),
.iHeight(`RESOLUTION_HEIGHT),
.oDone( wDone )
 
 
);
//---------------------------------------------
//generate the clock signal here
always begin
#`CLOCK_CYCLE Clock = ! Clock;
end
//---------------------------------------------
 
//-------------------------------------------------------------------------------------
/*
This makes sure the simulation actually writes the results to the PPM image file
once all the cores are done executing
*/
`define PARTITION_SIZE `RESOLUTION_HEIGHT/`MAX_CORES
integer i,j,kk;
reg [31:0] R;
always @ ( * )
begin
 
 
if (wDone == 1'b1)
begin
 
$display("Partition Size = %d",`PARTITION_SIZE);
for (kk = 0; kk < `MAX_CORES; kk = kk+1)
begin
wOMEMBankSelect = kk;
$display("wOMEMBankSelect = %d\n",wOMEMBankSelect);
for (j=0; j < `PARTITION_SIZE; j=j+1)
begin
for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
begin
wOMEMReadAddr = i+j*`RESOLUTION_WIDTH*3;
#`CLOCK_PERIOD;
#1;
R = ((wOMEMData >> (`SCALE-8)) > 255) ? 255 : (wOMEMData >> (`SCALE-8));
$fwrite(out2,"%d " , R );
 
if ((i %3) == 0)
$fwrite(out2,"\n# %d %d\n",i/3,j);
end
end
end
 
$fclose(out2);
$fwrite(log, "Simulation end time : %dns\n",$time);
$fclose(log);
 
$stop();
end
end
//-------------------------------------------------------------------------------------
 
reg [15:0] rTimeOut;
// `define MAX_INSTRUCTIONS 2
initial begin
// Initialize Inputs
Clock = 0;
Reset = 0;
rTimeOut = 0;
rHostEnable = 0;
//Read Config register values
$write("Loading control register.... ");
$readmemh("Creg.mem",rControlRegister);
$display("Done");
//Read configuration Data
$write("Loading scene parameters.... ");
$readmemh("Params.mem", rSceneParameters );
$display("Done");
//Read Scene Data
$write("Loading scene geometry.... ");
$readmemh("Vertex.mem",rVertexBuffer);
$display("Done");
$display("Number of primitives(%d): %d",rVertexBuffer[6],(rVertexBuffer[6]+1) *7);
//Read Texture Data
$write("Loading scene texture.... ");
$readmemh("Textures.mem",rTextures);
$display("Done");
 
//Read instruction data
$write("Loading code allocation table and user shaders.... ");
$readmemh("Instructions.mem",rInstructionBuffer);
$display("Done");
$display("Control Register : %b",rControlRegister[0]);
$display("Resolution : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
//Open output file
out2 = $fopen("Output.ppm");
$fwrite(out2,"P3\n");
$fwrite(out2,"#This file was generated by Theia's RTL simulation\n");
$fwrite(out2,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
$fwrite(out2,"255\n");
#10
Reset = 1;
 
// Wait 100 ns for global reset to finish
TMWE_O = 1;
#100 Reset = 0;
TMWE_O = 1;
$display("Intilializing TMEM @ %dns",$time);
//starts in 2 to skip Width and Height
for (k = 0;k < `TEXTURE_BUFFER_SIZE; k = k + 1)
begin
TMADR_O <= (k >> (`MAX_CORE_BITS));
TMSEL_O <= (k & (`MAX_TMEM_BANKS-1)); //X mod 2^n == X & (2^n - 1)
TMDAT_O <= rTextures[k];
#10;
if ((k % (256*3)) == 0)
begin
$write("|");
$fflush;
end
end
$display("\nDone Intilializing TMEM @ %dns",$time);
TMWE_O = 0;
rHostEnable = 1;
 
$fclose(out2);
$fwrite(log, "Simulation end time : %dns\n",$time);
$fclose(log);
 
$stop();
end
end
//-------------------------------------------------------------------------------------
 
reg [15:0] rTimeOut;
// `define MAX_INSTRUCTIONS 2
initial begin
// Initialize Inputs
Clock = 0;
Reset = 0;
rTimeOut = 0;
rHostEnable = 0;
//Read Config register values
$write("Loading control register.... ");
$readmemh("Creg.mem",rControlRegister);
$display("Done");
//Read configuration Data
$write("Loading scene parameters.... ");
$readmemh("Params.mem", rSceneParameters );
$display("Done");
//Read Scene Data
$write("Loading scene geometry.... ");
$readmemh("Vertex.mem",rVertexBuffer);
$display("Done");
$display("Number of primitives(%d): %d",rVertexBuffer[6],(rVertexBuffer[6]+1) *7);
//Read Texture Data
$write("Loading scene texture.... ");
$readmemh("Textures.mem",rTextures);
$display("Done");
 
//Read instruction data
$write("Loading code allocation table and user shaders.... ");
$readmemh("Instructions.mem",rInstructionBuffer);
$display("Done");
$display("Control Register : %b",rControlRegister[0]);
$display("Resolution : %d X %d",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
//Open output file
out2 = $fopen("Output.ppm");
$fwrite(out2,"P3\n");
$fwrite(out2,"#This file was generated by Theia's RTL simulation\n");
$fwrite(out2,"%d %d\n",`RESOLUTION_WIDTH, `RESOLUTION_HEIGHT );
$fwrite(out2,"255\n");
#10
Reset = 1;
 
// Wait 100 ns for global reset to finish
TMWE_O = 1;
#100 Reset = 0;
TMWE_O = 1;
$display("Intilializing TMEM @ %dns",$time);
//starts in 2 to skip Width and Height
for (k = 0;k < `TEXTURE_BUFFER_SIZE; k = k + 1)
begin
TMADR_O <= (k >> (`MAX_CORE_BITS));
TMSEL_O <= (k & (`MAX_TMEM_BANKS-1)); //X mod 2^n == X & (2^n - 1)
TMDAT_O <= rTextures[k];
#10;
if ((k % (256*3)) == 0)
begin
$write("|");
$fflush;
end
end
$display("\nDone Intilializing TMEM @ %dns",$time);
TMWE_O = 0;
rHostEnable = 1;
log = $fopen("Simulation.log");
$fwrite(log, "Simulation start time : %dns\n",$time);
$fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
log = $fopen("Simulation.log");
$fwrite(log, "Simulation start time : %dns\n",$time);
$fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
$fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
//Start dumping VCD
$display("-I- Starting VCD Dump\n");
// $dumpfile("TestBench_Theia.vcd");
// $dumpvars(0,TestBench_Theia);
end
 
endmodule
//Start dumping VCD
$display("-I- Starting VCD Dump\n");
// $dumpfile("TestBench_Theia.vcd");
// $dumpvars(0,TestBench_Theia);
end
 
endmodule
/branches/icarus_version/rtl/Module_ExecutionFSM.v
358,6 → 358,8
`SWIZZLE3D: `LOGME"SWIZZLE3D");
`MULP: `LOGME"MULP");
`XCHANGEX: `LOGME"XCHANGEX");
`XCHANGEY: `LOGME"XCHANGEY");
`XCHANGEZ: `LOGME"XCHANGEZ");
`IMUL: `LOGME"IMUL");
`UNSCALE: `LOGME"UNSCALE");
`RESCALE: `LOGME"UNSCALE");
/branches/icarus_version/rtl/Module_VectorALU.v
958,7 → 958,10
`MULP: ResultA = iChannel_Ax;
`NEG: ResultA = ~iChannel_Ax + 1'b1;
`XCHANGEX: ResultA = iChannel_Bx;
`XCHANGEY: ResultA = iChannel_Ax;
`XCHANGEZ: ResultA = iChannel_Ax;
 
 
default:
begin
`ifdef DEBUG
1004,6 → 1007,8
`MULP: ResultB = iChannel_Ay;
`NEG: ResultB = ~iChannel_Ay + 1'b1;
`XCHANGEX: ResultB = iChannel_Ay;
`XCHANGEY: ResultB = iChannel_By;
`XCHANGEZ: ResultB = iChannel_Ay;
default:
begin
1050,6 → 1055,8
`MULP: ResultC = wMultiplicationA_Result[31:0];
`NEG: ResultC = ~iChannel_Az + 1'b1;
`XCHANGEX: ResultC = iChannel_Az;
`XCHANGEY: ResultC = iChannel_Az;
`XCHANGEZ: ResultC = iChannel_Bz;
default:
begin
`ifdef DEBUG
1303,7 → 1310,7
wAddSubBOutputReady &&
wAddSubCOutputReady;
`XCHANGEX: OutputReady = wOutputDelay1Cycle;
`XCHANGEX,`XCHANGEY,`XCHANGEZ: OutputReady = wOutputDelay1Cycle;
default:
/branches/icarus_version/rtl/aDefinitions.v
30,8 → 30,8
//`define VERILATOR 1
`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
`define MAX_TMEM_BANKS 8 //The number of memory banks for TMEM
`define MAX_TMEM_BITS 3 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM
`define MAX_TMEM_BITS 2 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
//---------------------------------------------------------------------------------
//Verilog provides a `default_nettype none compiler directive. When
95,17 → 95,17
 
//Internal Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_INITIAL `ROM_ADDRESS_WIDTH'd0 //0 - This should always be zero
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd70
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd74
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd98
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd186
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd265
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd281
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd223
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd82
`define ENTRYPOINT_ADRR_CPPU `ROM_ADDRESS_WIDTH'd69
`define ENTRYPOINT_ADRR_RGU `ROM_ADDRESS_WIDTH'd73
`define ENTRYPOINT_ADRR_AABBIU `ROM_ADDRESS_WIDTH'd97
`define ENTRYPOINT_ADRR_BIU `ROM_ADDRESS_WIDTH'd185
`define ENTRYPOINT_ADRR_PSU `ROM_ADDRESS_WIDTH'd268
`define ENTRYPOINT_ADRR_PSU2 `ROM_ADDRESS_WIDTH'd284
`define ENTRYPOINT_ADRR_TCC `ROM_ADDRESS_WIDTH'd226
`define ENTRYPOINT_ADRR_NPG `ROM_ADDRESS_WIDTH'd81
//User Entry points (default ROM Address)
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd309
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd311
`define ENTRYPOINT_ADRR_USERCONSTANTS `ROM_ADDRESS_WIDTH'd312
`define ENTRYPOINT_ADRR_PIXELSHADER `ROM_ADDRESS_WIDTH'd314
`define ENTRYPOINT_ADRR_MAIN `ROM_ADDRESS_WIDTH'd37
 
//Please keep this syntax ENTRYPOINT_INDEX_* because the perl script that
/branches/icarus_version/rtl/Unit_Control.v
23,6 → 23,8
This is the main Finite State Machine.
 
**********************************************************************************/
 
 
 
`timescale 1ns / 1ps
`include "aDefinitions.v"
30,63 → 32,29
`include "Collaterals.v"
`endif
 
`define CU_AFTER_RESET_STATE 0
`define CU_WAIT_FOR_INITIAL_CONFIGURATION 1
`define CU_TRIGGER_CONFIGURATION_DATA_READ 2
`define CU_WAIT_FOR_CONFIG_DATA_READ 3
`define CU_ACK_CONFIG_DATA_READ 4
`define CU_PRECALCULATE_CONSTANTS 5
`define CU_WAIT_FOR_CONSTANT 6
`define CU_ACK_PRECALCULATE_CONSTANTS 7
`define CU_WAIT_FOR_TASK 8
`define CU_READ_TASK_DATA 9
`define CU_WAIT_TASK_DATA_READ 10
`define CU_ACK_TASK_DATA_READ 11
`define CU_TRIGGER_RGU 12
`define CU_WAIT_FOR_RGU 13
`define CU_ACK_RGU 14
`define CU_TRIGGER_GEO 15
`define CU_WAIT_FOR_GEO_SYNC 16
//`define CU_CHECK_AABBIU_REQUEST 17
`define CU_TRIGGER_TCC 17
//`define CU_CHECK_BIU_REQUEST 18
//`define CU_TRIGGER_TFF 18
//`define CU_CHECK_GEO_DONE 19
//`define CU_WAIT_FOR_TFF 19
`define CU_TRIGGER_AABBIU 20
`define CU_WAIT_FOR_AABBIU 21
`define CU_TRIGGER_MAIN 22
`define CU_WAIT_FOR_MAIN 23
`define CU_ACK_MAIN 24
`define CU_TRIGGER_PSU 25
`define CU_WAIT_FOR_PSU 26
`define CU_ACK_PSU 27
//`define CU_TRIGGER_PCU 28
`define CU_WAIT_FOR_PCU 29
`define CU_ACK_PCU 30
`define CU_CHECK_HIT 31
`define CU_CLEAR_REGISTERS 32
`define CU_WAIT_CLEAR_REGISTERS 33
`define CU_ACK_CLEAR_REGISTERS 34
`define CU_TRIGGER_PSU_WITH_TEXTURE 35
`define WAIT_FOR_TCC 36
`define CU_TRIGGER_NPU 37
`define CU_WAIT_NPU 38
`define CU_ACK_NPU 39
`define CU_PERFORM_INTIAL_CONFIGURATION 40
`define CU_SET_PICTH 41
`define CU_TRIGGER_USERCONSTANTS 42
`define CU_WAIT_USERCONSTANTS 43
`define CU_ACK_USERCONSTANTS 44
`define CU_TRIGGER_USERPIXELSHADER 45
`define CU_WAIT_FOR_USERPIXELSHADER 46
`define CU_ACK_USERPIXELSHADER 47
`define CU_DONE 48
`define CU_WAIT_FOR_RENDER_ENABLE 49
`define CU_ACK_TCC 50
`define CU_WAIT_FOR_HOST_DATA_AVAILABLE 51
`define CU_WAIT_FOR_HOST_DATA_ACK 52
`define CU_COMMIT_PIXEL_RESULT 53
`define CU_AFTER_RESET_STATE 0
`define CU_WAIT_FOR_INITIAL_CONFIGURATION 1
`define CU_TRIGGER_CONFIGURATION_DATA_READ 2
`define CU_WAIT_FOR_CONFIG_DATA_READ 3
`define CU_ACK_CONFIG_DATA_READ 4
`define CU_PRECALCULATE_CONSTANTS 5
`define CU_WAIT_FOR_CONSTANT 6
`define CU_ACK_PRECALCULATE_CONSTANTS 7
`define CU_TRIGGER_MAIN 8
`define CU_WAIT_FOR_MAIN 9
`define CU_ACK_MAIN 10
`define CU_CLEAR_REGISTERS 11
`define CU_WAIT_CLEAR_REGISTERS 12
`define CU_ACK_CLEAR_REGISTERS 13
`define CU_PERFORM_INTIAL_CONFIGURATION 14
`define CU_TRIGGER_USERCONSTANTS 15
`define CU_WAIT_USERCONSTANTS 16
`define CU_ACK_USERCONSTANTS 17
`define CU_DONE 18
`define CU_WAIT_FOR_RENDER_ENABLE 19
`define CU_WAIT_FOR_HOST_DATA_AVAILABLE 20
`define CU_WAIT_FOR_HOST_DATA_ACK 21
`define CU_COMMIT_PIXEL_RESULT 22
//--------------------------------------------------------------
module ControlUnit
(
159,12 → 127,6
);
//--------------------------------------------------------------
 
`ifdef DEBUG_CU
always @ ( wHit )
begin
$display( "*** Triangle HIT ***\n");
end
`endif
 
//Next states logic and Reset sequence
always @(posedge Clock or posedge Reset)
211,12 → 173,7
`CU_WAIT_FOR_INITIAL_CONFIGURATION:
begin
//$display("CORE: %d CU_WAIT_FOR_INITIAL_CONFIGURATION", iDebug_CoreID);
// `ifdef DEBUG_CU
// $display("%d Control: CU_WAIT_FOR_INITIAL_CONFIGURATION\n",$time);
// `endif
//oRamBusOwner = 0;
oCodeInstructioPointer = 0;
oGFUEnable = 0;
oUCodeEnable = 0;
272,7 → 229,6
$display("%d CU_CLEAR_REGISTERS\n",$time);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_INITIAL;
oGFUEnable = 0;
oUCodeEnable = 1; //*
286,19 → 242,13
oDone = 0;
oResultCommited = 0;
////$display("\n\n %d XOXOXOXOX FLIP XOXOXOXOXOX\n\n",$time);
//oIncCurrentPitch = 0;
NextState = `CU_WAIT_CLEAR_REGISTERS;
end
//-----------------------------------------
`CU_WAIT_CLEAR_REGISTERS:
begin
// `ifdef DEBUG_CU
// $display("%d CU_WAIT_CLEAR_REGISTERS\n",$time);
// `endif
//$display("CORE: %d CU_WAIT_CLEAR_REGISTERS", iDebug_CoreID);
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
 
oCodeInstructioPointer = `ENTRYPOINT_INDEX_INITIAL;
oGFUEnable = 0;
oUCodeEnable = 0;
353,14 → 303,6
`CU_WAIT_FOR_CONFIG_DATA_READ:
begin
 
// `ifdef DEBUG_CU
// $display("%d Control: CU_WAIT_FOR_CONFIG_DATA_READ\n",$time);
// `endif
 
 
//$display("CORE: %d CU_WAIT_FOR_CONFIG_DATA_READ", iDebug_CoreID);
 
//oRamBusOwner = 0;//`REG_BUS_OWNED_BY_BCU;
oCodeInstructioPointer = 0;
oGFUEnable = 0;
oUCodeEnable = 0;
575,244 → 517,7
else
NextState = `CU_WAIT_FOR_RENDER_ENABLE;
end
//-----------------------------------------
/*
`CU_TRIGGER_RGU:
begin
`ifdef DEBUG_CU
$display("CORE: %d CU_TRIGGER_RGU", iDebug_CoreID);
`endif
 
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_RGU;
oGFUEnable = 0;
oUCodeEnable = 1;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 0;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
NextState = `CU_WAIT_FOR_RGU;
end
//-----------------------------------------
`CU_WAIT_FOR_RGU:
begin
 
// `ifdef DEBUG_CU
// $display("%d Control: CU_WAIT_FOR_RGU\n",$time);
// `endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = 0;
oGFUEnable = 0;
oUCodeEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 0;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone )
NextState = `CU_ACK_RGU;
else
NextState = `CU_WAIT_FOR_RGU;
end
//-----------------------------------------
`CU_ACK_RGU:
begin
 
`ifdef DEBUG_CU
$display("CORE: %d CU_ACK_RGU", iDebug_CoreID);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = 0;
oGFUEnable = 0;
oUCodeEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone == 0 & iRenderEnable == 1)
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;//`CU_TRIGGER_GEO;///////////// GET RID OF GEO!!!
else
NextState = `CU_ACK_RGU;
end
*/
//-----------------------------------------
`CU_TRIGGER_TCC:
begin
////$display("CU_TRIGGER_TCC");
`ifdef DEBUG_CU
$display("%d CORE %d Control: CU_TRIGGER_TCC\n",$time,iDebug_CoreID);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_TCC;
oUCodeEnable = 1; //*
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0; //We need u,v from last IO read cycle
oResultCommited = 0;
////$display("\n\n %d XOXOXOXOX FLIP XOXOXOXOXOX\n\n",$time);
//oIncCurrentPitch = 0;
oDone = 0;
NextState = `WAIT_FOR_TCC;
end
//-----------------------------------------
`WAIT_FOR_TCC:
begin
////$display("WAIT_FOR_TCC");
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_TCC;
oUCodeEnable = 0; //*
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone )
NextState = `CU_ACK_TCC;
else
NextState = `WAIT_FOR_TCC;
end
//-----------------------------------------
`CU_ACK_TCC:
begin
////$display("WAIT_FOR_TCC");
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_TCC;
oUCodeEnable = 0; //*
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 0;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone == 0 && iSceneTraverseComplete == 1'b1) //DDDD
NextState = `CU_TRIGGER_PSU_WITH_TEXTURE;
else if (iUCodeDone == 0 && iSceneTraverseComplete == 1'b0)
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;
else
NextState = `CU_ACK_TCC;
end
//-----------------------------------------
/*
Was there any hit at all?
At this point, all the triangles in the list
have been traversed looking for a hit with our ray.
There are 3 possibilities:
1) The was not a single hit, then just paint a black
pixel on the screen and send it via PCU.
2)There was a hit and Texturing is not enabled, then trigger the PSU with
no texturing
2) There was a hit and Texturing is enabled, then fetch the texture
values corresponding to the triangle that we hitted.
*/
`CU_CHECK_HIT:
begin
`ifdef DEBUG_CU
$display("%d CORE %d Control: CU_CHECK_HIT\n",$time,iDebug_CoreID);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_GFU;
oCodeInstructioPointer = 0;
oUCodeEnable = 0;
oGFUEnable = 0; ///CHANGED Aug 15
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 0;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
if (wHit)
begin
//$display("HIT");
NextState = `CU_TRIGGER_PSU_WITH_TEXTURE;
end
else
NextState = `CU_TRIGGER_USERPIXELSHADER;//666
end
//-----------------------------------------
`CU_TRIGGER_PSU_WITH_TEXTURE:
begin
`ifdef DEBUG_CU
$display("%d Control: CU_TRIGGER_PSU_WITH_TEXTURE\n",$time);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_PSU2;
oUCodeEnable = 1;
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 1;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 0;//////NEW NEW NEW NEW
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
////$display("\n\n %d XOXOXOXOX FLIP XOXOXOXOXOX\n\n",$time);
//oIncCurrentPitch = 0;
NextState = `CU_WAIT_FOR_PSU;
end
//-----------------------------------------
`CU_WAIT_FOR_HOST_DATA_ACK:
begin
oCodeInstructioPointer = 0;
929,7 → 634,7
//oRamBusOwner = `REG_BUS_OWNED_BY_GFU;
oCodeInstructioPointer = 0; //*
oUCodeEnable = 0; //*
oGFUEnable = 0; //Changed Aug 15
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 1;
939,17 → 644,7
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
// $stop();
/*
if ( iUCodeDone == 1'b0 & iSceneTraverseComplete == 1'b1)
NextState = `CU_CHECK_HIT;
else if ( iUCodeDone == 1'b0 & iSceneTraverseComplete == 1'b0) //ERROR!!! What if iSceneTraverseComplete will become 1 a cycle after this??
NextState = `CU_WAIT_FOR_HOST_DATA_ACK;//`CU_WAIT_FOR_HOST_DATA_AVAILABLE;
else
NextState = `CU_ACK_MAIN;
*/
if (iUCodeDone == 1'b0 && iUCodeReturnValue == 0)
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;
else if (iUCodeDone == 1'b0 && iUCodeReturnValue == 1)
957,10 → 652,10
else
NextState = `CU_ACK_MAIN;
end
//-----------------------------------------
`CU_COMMIT_PIXEL_RESULT:
begin
end
//-----------------------------------------
`CU_COMMIT_PIXEL_RESULT:
begin
oCodeInstructioPointer = 0;
oUCodeEnable = 0;
oGFUEnable = 0;
970,160 → 665,15
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 0;
oFlipMem = 0;
oDone = 0;
oFlipMem = 0;
oDone = 0;
oResultCommited = 1;
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;
end
//-----------------------------------------
`CU_WAIT_FOR_PSU:
begin
// `ifdef DEBUG_CU
// $display("%d Control: CU_TRIGGER_PSU\n",$time);
// `endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_PSU;
oUCodeEnable = 0;
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone )
NextState = `CU_ACK_PSU;
else
NextState = `CU_WAIT_FOR_PSU;
end
end
//-----------------------------------------
`CU_ACK_PSU:
begin
`ifdef DEBUG_CU
$display("%d CORE: %d Control: CU_ACK_PSU\n",$time, iDebug_CoreID);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = 0; //*
oUCodeEnable = 0; //*
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone == 0)
NextState = `CU_TRIGGER_USERPIXELSHADER;
else
NextState = `CU_ACK_PSU;
end
//-----------------------------------------
//-----------------------------------------
`CU_TRIGGER_NPU: //Next Pixel Unit
begin
`ifdef DEBUG_CU
$display("%d CORE: %d Control: CU_TRIGGER_NPU\n",$time, iDebug_CoreID);
`endif
//$write("*");
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_NPG; //*
oUCodeEnable = 1; //*
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
 
NextState = `CU_WAIT_NPU;
end
//-----------------------------------------
`CU_WAIT_NPU:
begin
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_NPG;
oUCodeEnable = 0;
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone )
NextState = `CU_ACK_NPU;
else
NextState = `CU_WAIT_NPU;
end
//-----------------------------------------
/*
Next Pixel generation: here we either goto
to RGU for the next pixel, or we have no
more pixels so we are done we our picture!
*/
`CU_ACK_NPU:
begin
`ifdef DEBUG_CU
$display("%d CORE: %d Control: CU_ACK_NPU\n",$time, iDebug_CoreID);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = 0; //*
oUCodeEnable = 0; //*
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone == 0 && iUCodeReturnValue == 1)
NextState = `CU_WAIT_FOR_HOST_DATA_AVAILABLE;//`CU_TRIGGER_RGU;
else if (iUCodeDone == 0 && iUCodeReturnValue == 0)
NextState = `CU_DONE;
else
NextState = `CU_ACK_NPU;
end
//-----------------------------------------
`CU_DONE:
begin
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
1145,93 → 695,6
NextState = `CU_DONE;
end
//-----------------------------------------
/*
Here we no longer use GFU so set Enable to zero
*/
`CU_TRIGGER_USERPIXELSHADER:
begin
`ifdef DEBUG_CU
$display("%d Control: CU_TRIGGER_PSU\n",$time);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_PIXELSHADER;
oUCodeEnable = 1;
oGFUEnable = 0;//*
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
NextState = `CU_WAIT_FOR_USERPIXELSHADER;
end
//-----------------------------------------
`CU_WAIT_FOR_USERPIXELSHADER:
begin
// `ifdef DEBUG_CU
// $display("%d Control: CU_TRIGGER_PSU\n",$time);
// `endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = `ENTRYPOINT_INDEX_PIXELSHADER;
oUCodeEnable = 0;
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 0;
//oIncCurrentPitch = 0;
if ( iUCodeDone )
NextState = `CU_ACK_USERPIXELSHADER;
else
NextState = `CU_WAIT_FOR_USERPIXELSHADER;
end
//-----------------------------------------
`CU_ACK_USERPIXELSHADER:
begin
`ifdef DEBUG_CU
$display("%d Control: CU_ACK_PSU\n",$time);
`endif
//oRamBusOwner = `REG_BUS_OWNED_BY_UCODE;
oCodeInstructioPointer = 0; //*
oUCodeEnable = 0; //*
oGFUEnable = 0;
oIOWritePixel = 0;
rResetHitFlop = 0;
rHitFlopEnable = 0;
oTriggerTFF = 0;
oSetCurrentPitch = 0;
oFlipMemEnabled = 1;
oFlipMem = 0;
oDone = 0;
oResultCommited = 1;
//oIncCurrentPitch = 0;
if ( iUCodeDone == 0)
NextState = `CU_TRIGGER_NPU;//`CU_TRIGGER_PCU;
else
NextState = `CU_ACK_USERPIXELSHADER;
end
//---------------------------------------------------
default:
begin
/branches/icarus_version/rtl/Theia.v
130,9 → 130,9
wire [`MAX_CORES-1:0] wRCommited;
 
 
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
assign HDL_O = wHostDataLatched[0] & wHostDataLatched[1] & wHostDataLatched[2] & wHostDataLatched[3];
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
assign HDL_O = wHostDataLatched[0] & wHostDataLatched[1] & wHostDataLatched[2] & wHostDataLatched[3];
assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
 
 
 
309,7 → 309,7
(
.Clock( CLK_I ),
.Reset( RST_I ),
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
/branches/icarus_version/rtl/Module_ROM.v
51,58 → 51,58
`define CURRENT_LIGHT_DIFFUSE 16'h6
 
//-----------------------------------------------------------------
`define TAG_PIXELSHADER 16'd311
`define TAG_USERCONSTANTS 16'd309
`define TAG_PSU_UCODE_ADRESS2 16'd281
`define TAG_PSU_UCODE_ADRESS 16'd265
`define LABEL_TCC_EXIT 16'd264
`define TAG_TCC_UCODE_ADDRESS 16'd223
`define LABEL_BIU4 16'd222
`define TAG_PIXELSHADER 16'd314
`define TAG_USERCONSTANTS 16'd312
`define TAG_PSU_UCODE_ADRESS2 16'd284
`define TAG_PSU_UCODE_ADRESS 16'd268
`define LABEL_TCC_EXIT 16'd267
`define TAG_TCC_UCODE_ADDRESS 16'd226
`define LABEL_BIU4 16'd225
`define LABEL_BIU3 16'd211
`define LABEL_BIU2 16'd207
`define LABEL_BIU1 16'd204
`define TAG_BIU_UCODE_ADDRESS 16'd186
`define LABEL_HIT 16'd184
`define LABEL15 16'd182
`define LABEL14 16'd180
`define LABEL13 16'd178
`define LABEL_TEST_XY_PLANE 16'd173
`define LABEL12 16'd171
`define LABEL11 16'd169
`define LABEL10 16'd167
`define LABEL_TEST_XZ_PLANE 16'd161
`define LABEL9 16'd159
`define LABEL8 16'd157
`define LABEL7 16'd155
`define LABEL_TEST_YZ_PLANE 16'd149
`define LABEL_RAY_INSIDE_BOX 16'd146
`define LABEL_ELSEZ 16'd145
`define LABEL6 16'd142
`define LABEL_ELESE_IFZ 16'd138
`define LABEL5 16'd135
`define LABEL_TEST_RAY_Z_ORIGEN 16'd131
`define LABEL_ELSEY 16'd130
`define LABEL4 16'd127
`define LABEL_ELESE_IFY 16'd123
`define LABEL3 16'd120
`define LABEL_TEST_RAY_Y_ORIGEN 16'd116
`define LABEL_ELSEX 16'd115
`define LABEL2 16'd112
`define LABEL_ELSE_IFX 16'd108
`define LABEL1 16'd105
`define LABEL_TEST_RAY_X_ORIGEN 16'd101
`define TAG_AABBIU_UCODE_ADDRESS 16'd98
`define LABEL_ALLDONE 16'd96
`define LABEL_NPG_NEXT_ROW 16'd91
`define TAG_NPG_UCODE_ADDRESS 16'd82
`define TAG_RGU_UCODE_ADDRESS 16'd74
`define TAG_CPPU_UCODE_ADDRESS 16'd70
`define LABEL_MAIN_RENDER_DONE 16'd69
`define LABEL_MAIN_IS_NO_HIT 16'd62
`define LABEL_MAIN_IS_HIT 16'd51
`define LABEL_MAIN_CHECK_HIT 16'd50
`define LABEL_DEC_PRIM_COUNT 16'd47
`define LABEL_MAIN_TEST_INTERSECTION 16'd42
`define LABEL_BIU2 16'd205
`define LABEL_BIU1 16'd202
`define TAG_BIU_UCODE_ADDRESS 16'd185
`define LABEL_HIT 16'd183
`define LABEL15 16'd181
`define LABEL14 16'd179
`define LABEL13 16'd177
`define LABEL_TEST_XY_PLANE 16'd172
`define LABEL12 16'd170
`define LABEL11 16'd168
`define LABEL10 16'd166
`define LABEL_TEST_XZ_PLANE 16'd160
`define LABEL9 16'd158
`define LABEL8 16'd156
`define LABEL7 16'd154
`define LABEL_TEST_YZ_PLANE 16'd148
`define LABEL_RAY_INSIDE_BOX 16'd145
`define LABEL_ELSEZ 16'd144
`define LABEL6 16'd141
`define LABEL_ELESE_IFZ 16'd137
`define LABEL5 16'd134
`define LABEL_TEST_RAY_Z_ORIGEN 16'd130
`define LABEL_ELSEY 16'd129
`define LABEL4 16'd126
`define LABEL_ELESE_IFY 16'd122
`define LABEL3 16'd119
`define LABEL_TEST_RAY_Y_ORIGEN 16'd115
`define LABEL_ELSEX 16'd114
`define LABEL2 16'd111
`define LABEL_ELSE_IFX 16'd107
`define LABEL1 16'd104
`define LABEL_TEST_RAY_X_ORIGEN 16'd100
`define TAG_AABBIU_UCODE_ADDRESS 16'd97
`define LABEL_ALLDONE 16'd95
`define LABEL_NPG_NEXT_ROW 16'd90
`define TAG_NPG_UCODE_ADDRESS 16'd81
`define TAG_RGU_UCODE_ADDRESS 16'd73
`define TAG_CPPU_UCODE_ADDRESS 16'd69
`define LABEL_MAIN_RENDER_DONE 16'd68
`define LABEL_MAIN_IS_NO_HIT 16'd61
`define LABEL_MAIN_IS_HIT 16'd50
`define LABEL_MAIN_CHECK_HIT 16'd49
`define LABEL_DEC_PRIM_COUNT 16'd46
`define LABEL_MAIN_TEST_INTERSECTION 16'd41
`define TAG_ADRR_MAIN 16'd37
 
 
112,8 → 112,6
//This is the first code that gets executed after the machine is
//externally configured ie after the MST_I goes from 1 to zero.
//It sets initial values for some of the internal registers
 
 
 
0: I = { `ZERO ,`CREG_LAST_t ,`VOID ,`VOID };
//Set the last 't' to very positive value(500)
185,56 → 183,56
//---------------------------------------------------------------------
//This is the main sub-routine
//TAG_ADRR_MAIN:
37: I = { `NOP ,`RT_FALSE };
//Generate the ray, but this is wrong, it has to generate only once for all the triangles..
38: I = { `JNEX ,`LABEL_MAIN_TEST_INTERSECTION ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES };
39: I = { `CALL ,`ENTRYPOINT_ADRR_RGU ,`VOID ,`VOID };
40: I = { `ZERO ,`CREG_HIT ,`VOID ,`VOID };
41: I = { `RESCALE ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
37: I = { `JNEX ,`LABEL_MAIN_TEST_INTERSECTION ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES };
38: I = { `CALL ,`ENTRYPOINT_ADRR_RGU ,`VOID ,`VOID };
39: I = { `ZERO ,`CREG_HIT ,`VOID ,`VOID };
40: I = { `RESCALE ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
//LABEL_MAIN_TEST_INTERSECTION:
//Check ofr triangle intersection
42: I = { `NOP ,`RT_FALSE };
43: I = { `CALL ,`ENTRYPOINT_ADRR_BIU ,`VOID ,`VOID };
44: I = { `NOP ,`RT_FALSE };
41: I = { `NOP ,`RT_FALSE };
42: I = { `CALL ,`ENTRYPOINT_ADRR_BIU ,`VOID ,`VOID };
43: I = { `NOP ,`RT_FALSE };
45: I = { `JEQX ,`LABEL_DEC_PRIM_COUNT ,`R99 ,`CREG_ZERO };
46: I = { `COPY ,`CREG_HIT ,`R99 ,`VOID };
44: I = { `JEQX ,`LABEL_DEC_PRIM_COUNT ,`R99 ,`CREG_ZERO };
45: I = { `COPY ,`CREG_HIT ,`R99 ,`VOID };
//LABEL_DEC_PRIM_COUNT:
47: I = { `DEC ,`CREG_PRIMITIVE_COUNT ,`CREG_PRIMITIVE_COUNT ,`VOID };
48: I = { `JEQX ,`LABEL_MAIN_CHECK_HIT ,`CREG_PRIMITIVE_COUNT ,`CREG_ZERO };
49: I = { `RETURN ,`RT_FALSE };
46: I = { `DEC ,`CREG_PRIMITIVE_COUNT ,`CREG_PRIMITIVE_COUNT ,`VOID };
47: I = { `JEQX ,`LABEL_MAIN_CHECK_HIT ,`CREG_PRIMITIVE_COUNT ,`CREG_ZERO };
48: I = { `RETURN ,`RT_FALSE };
//LABEL_MAIN_CHECK_HIT:
50: I = { `JEQX ,`LABEL_MAIN_IS_NO_HIT ,`CREG_HIT ,`CREG_ZERO };
49: I = { `JEQX ,`LABEL_MAIN_IS_NO_HIT ,`CREG_HIT ,`CREG_ZERO };
//LABEL_MAIN_IS_HIT:
51: I = { `NOP ,`RT_FALSE };
52: I = { `CALL ,`ENTRYPOINT_ADRR_TCC ,`VOID ,`VOID };
53: I = { `NOP ,`RT_FALSE };
54: I = { `CALL ,`ENTRYPOINT_ADRR_PSU2 ,`VOID ,`VOID };
55: I = { `NOP ,`RT_FALSE };
56: I = { `CALL ,`ENTRYPOINT_ADRR_PIXELSHADER ,`VOID ,`VOID };
57: I = { `NOP ,`RT_FALSE };
58: I = { `CALL ,`ENTRYPOINT_ADRR_NPG ,`VOID ,`VOID };
59: I = { `NOP ,`RT_FALSE };
60: I = { `JEQX ,`LABEL_MAIN_RENDER_DONE ,`R99 ,`CREG_ZERO };
61: I = { `RETURN ,`RT_TRUE };
50: I = { `NOP ,`RT_FALSE };
51: I = { `CALL ,`ENTRYPOINT_ADRR_TCC ,`VOID ,`VOID };
52: I = { `NOP ,`RT_FALSE };
53: I = { `CALL ,`ENTRYPOINT_ADRR_PSU2 ,`VOID ,`VOID };
54: I = { `NOP ,`RT_FALSE };
55: I = { `CALL ,`ENTRYPOINT_ADRR_PIXELSHADER ,`VOID ,`VOID };
56: I = { `NOP ,`RT_FALSE };
57: I = { `CALL ,`ENTRYPOINT_ADRR_NPG ,`VOID ,`VOID };
58: I = { `NOP ,`RT_FALSE };
59: I = { `JEQX ,`LABEL_MAIN_RENDER_DONE ,`R99 ,`CREG_ZERO };
60: I = { `RETURN ,`RT_TRUE };
 
//LABEL_MAIN_IS_NO_HIT:
62: I = { `NOP ,`RT_FALSE };
63: I = { `CALL ,`ENTRYPOINT_ADRR_PIXELSHADER ,`VOID ,`VOID };
64: I = { `NOP ,`RT_FALSE };
65: I = { `CALL ,`ENTRYPOINT_ADRR_NPG ,`VOID ,`VOID };
66: I = { `NOP ,`RT_FALSE };
67: I = { `JNEX ,`LABEL_MAIN_RENDER_DONE ,`R99 ,`CREG_ZERO };
61: I = { `NOP ,`RT_FALSE };
62: I = { `CALL ,`ENTRYPOINT_ADRR_PIXELSHADER ,`VOID ,`VOID };
63: I = { `NOP ,`RT_FALSE };
64: I = { `CALL ,`ENTRYPOINT_ADRR_NPG ,`VOID ,`VOID };
65: I = { `NOP ,`RT_FALSE };
66: I = { `JNEX ,`LABEL_MAIN_RENDER_DONE ,`R99 ,`CREG_ZERO };
67: I = { `RETURN ,`RT_TRUE };
//LABEL_MAIN_RENDER_DONE:
68: I = { `RETURN ,`RT_TRUE };
//LABEL_MAIN_RENDER_DONE:
69: I = { `RETURN ,`RT_TRUE };
 
 
//----------------------------------------------------------------------
242,10 → 240,10
//TAG_CPPU_UCODE_ADDRESS:
 
 
70: I = { `SUB ,`R1 ,`CREG_PROJECTION_WINDOW_MAX ,`CREG_PROJECTION_WINDOW_MIN };
71: I = { `DIV ,`CREG_PROJECTION_WINDOW_SCALE ,`R1 ,`CREG_RESOLUTION };
72: I = { `COPY ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
73: I = { `RETURN ,`RT_FALSE };
69: I = { `SUB ,`R1 ,`CREG_PROJECTION_WINDOW_MAX ,`CREG_PROJECTION_WINDOW_MIN };
70: I = { `DIV ,`CREG_PROJECTION_WINDOW_SCALE ,`R1 ,`CREG_RESOLUTION };
71: I = { `COPY ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
72: I = { `RETURN ,`RT_FALSE };
 
//----------------------------------------------------------------------
//Micro code for RGU
252,224 → 250,238
//TAG_RGU_UCODE_ADDRESS:
 
 
74: I = { `MUL ,`R1 ,`CREG_PIXEL_2D_POSITION ,`CREG_PROJECTION_WINDOW_SCALE };
75: I = { `ADD ,`R1 ,`R1 ,`CREG_PROJECTION_WINDOW_MIN };
76: I = { `SUB ,`CREG_UNORMALIZED_DIRECTION ,`R1 ,`CREG_CAMERA_POSITION };
77: I = { `MAG ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`VOID };
78: I = { `DIV ,`CREG_RAY_DIRECTION ,`CREG_UNORMALIZED_DIRECTION ,`R2 };
79: I = { `DEC ,`CREG_LAST_COL ,`CREG_PIXEL_2D_FINAL_POSITION ,`VOID };
80: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
73: I = { `MUL ,`R1 ,`CREG_PIXEL_2D_POSITION ,`CREG_PROJECTION_WINDOW_SCALE };
74: I = { `ADD ,`R1 ,`R1 ,`CREG_PROJECTION_WINDOW_MIN };
75: I = { `SUB ,`CREG_UNORMALIZED_DIRECTION ,`R1 ,`CREG_CAMERA_POSITION };
76: I = { `MAG ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`VOID };
77: I = { `DIV ,`CREG_RAY_DIRECTION ,`CREG_UNORMALIZED_DIRECTION ,`R2 };
78: I = { `DEC ,`CREG_LAST_COL ,`CREG_PIXEL_2D_FINAL_POSITION ,`VOID };
79: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
81: I = { `RET ,`R99 ,`TRUE };
80: I = { `RET ,`R99 ,`TRUE };
//----------------------------------------------------------------------
//Next Pixel generation Code (NPG)
//TAG_NPG_UCODE_ADDRESS:
 
82: I = { `COPY ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
81: I = { `COPY ,`CREG_PRIMITIVE_COUNT ,`CREG_MAX_PRIMITIVES ,`VOID };
 
83: I = { `ZERO ,`CREG_TEXTURE_COLOR ,`VOID ,`VOID };
84: I = { `SETX ,`CREG_TEXTURE_COLOR ,32'h60000 };
85: I = { `ADD ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_3 };
82: I = { `ZERO ,`CREG_TEXTURE_COLOR ,`VOID ,`VOID };
83: I = { `SETX ,`CREG_TEXTURE_COLOR ,32'h60000 };
84: I = { `ADD ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_3 };
 
86: I = { `ADD ,`CREG_PIXEL_PITCH ,`CREG_PIXEL_PITCH ,`CREG_3 };
87: I = { `COPY ,`OREG_ADDR_O ,`CREG_PIXEL_PITCH ,`VOID };
88: I = { `JGEX ,`LABEL_NPG_NEXT_ROW ,`CREG_PIXEL_2D_POSITION ,`CREG_LAST_COL };
89: I = { `INCX ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
90: I = { `RET ,`R99 ,`FALSE };
85: I = { `ADD ,`CREG_PIXEL_PITCH ,`CREG_PIXEL_PITCH ,`CREG_3 };
86: I = { `COPY ,`OREG_ADDR_O ,`CREG_PIXEL_PITCH ,`VOID };
87: I = { `JGEX ,`LABEL_NPG_NEXT_ROW ,`CREG_PIXEL_2D_POSITION ,`CREG_LAST_COL };
88: I = { `INCX ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
89: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_NPG_NEXT_ROW:
91: I = { `SETX ,`CREG_PIXEL_2D_POSITION ,32'h0 };
92: I = { `INCY ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
93: I = { `JGEY ,`LABEL_ALLDONE ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_FINAL_POSITION };
94: I = { `NOP ,`RT_FALSE };
95: I = { `RET ,`R99 ,`FALSE };
90: I = { `SETX ,`CREG_PIXEL_2D_POSITION ,32'h0 };
91: I = { `INCY ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_POSITION ,`VOID };
92: I = { `JGEY ,`LABEL_ALLDONE ,`CREG_PIXEL_2D_POSITION ,`CREG_PIXEL_2D_FINAL_POSITION };
93: I = { `NOP ,`RT_FALSE };
94: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_ALLDONE:
96: I = { `NOP ,`RT_FALSE };
97: I = { `RET ,`R99 ,`TRUE };
95: I = { `NOP ,`RT_FALSE };
96: I = { `RET ,`R99 ,`TRUE };
 
//----------------------------------------------------------------------
//Micro code for AABBIU
//TAG_AABBIU_UCODE_ADDRESS:
98: I = { `ZERO ,`R3 ,`VOID ,`VOID };
99: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
100: I = { `RETURN ,`RT_TRUE };
97: I = { `ZERO ,`R3 ,`VOID ,`VOID };
98: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
99: I = { `RETURN ,`RT_TRUE };
 
//LABEL_TEST_RAY_X_ORIGEN:
101: I = { `JGEX ,`LABEL_ELSE_IFX ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
102: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
103: I = { `JLEX ,`LABEL1 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
104: I = { `RETURN ,`RT_FALSE };
100: I = { `JGEX ,`LABEL_ELSE_IFX ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
101: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
102: I = { `JLEX ,`LABEL1 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
103: I = { `RETURN ,`RT_FALSE };
 
//LABEL1:
105: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
106: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
107: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
104: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
105: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
106: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELSE_IFX:
108: I = { `JLEX ,`LABEL_ELSEX ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
109: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
110: I = { `JGEX ,`LABEL2 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
111: I = { `RETURN ,`RT_FALSE };
107: I = { `JLEX ,`LABEL_ELSEX ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
108: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
109: I = { `JGEX ,`LABEL2 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
110: I = { `RETURN ,`RT_FALSE };
//LABEL2:
112: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
113: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
114: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
111: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
112: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
113: I = { `JMP ,`LABEL_TEST_RAY_Y_ORIGEN ,`VOID ,`VOID };
//LABEL_ELSEX:
115: I = { `SETX ,`R5 ,32'b1 };
114: I = { `SETX ,`R5 ,32'b1 };
 
//LABEL_TEST_RAY_Y_ORIGEN:
116: I = { `JGEY ,`LABEL_ELESE_IFY ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
117: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
118: I = { `JLEY ,`LABEL3 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
119: I = { `RETURN ,`RT_FALSE };
115: I = { `JGEY ,`LABEL_ELESE_IFY ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
116: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
117: I = { `JLEY ,`LABEL3 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
118: I = { `RETURN ,`RT_FALSE };
 
//LABEL3:
120: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
121: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
122: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
119: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
120: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
121: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELESE_IFY:
123: I = { `JLEY ,`LABEL_ELSEY ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
124: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
125: I = { `JGEY ,`LABEL4 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
126: I = { `RETURN ,`RT_FALSE };
122: I = { `JLEY ,`LABEL_ELSEY ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
123: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
124: I = { `JGEY ,`LABEL4 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
125: I = { `RETURN ,`RT_FALSE };
 
//LABEL4:
127: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
128: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
129: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
126: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
127: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
128: I = { `JMP ,`LABEL_TEST_RAY_Z_ORIGEN ,`VOID ,`VOID };
 
//LABEL_ELSEY:
130: I = { `SETY ,`R5 ,32'b1 };
129: I = { `SETY ,`R5 ,32'b1 };
 
//LABEL_TEST_RAY_Z_ORIGEN:
131: I = { `JGEZ ,`LABEL_ELESE_IFZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
132: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
133: I = { `JLEZ ,`LABEL5 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
134: I = { `RETURN ,`RT_FALSE };
130: I = { `JGEZ ,`LABEL_ELESE_IFZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMIN };
131: I = { `SUB ,`R1 ,`CREG_AABBMIN ,`CREG_CAMERA_POSITION };
132: I = { `JLEZ ,`LABEL5 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
133: I = { `RETURN ,`RT_FALSE };
 
//LABEL5:
135: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
136: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
137: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
134: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
135: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
136: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
 
//LABEL_ELESE_IFZ:
138: I = { `JLEZ ,`LABEL_ELSEZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
139: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
140: I = { `JGEZ ,`LABEL6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
141: I = { `RETURN ,`RT_FALSE };
137: I = { `JLEZ ,`LABEL_ELSEZ ,`CREG_CAMERA_POSITION ,`CREG_AABBMAX };
138: I = { `SUB ,`R1 ,`CREG_AABBMAX ,`CREG_CAMERA_POSITION };
139: I = { `JGEZ ,`LABEL6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
140: I = { `RETURN ,`RT_FALSE };
 
//LABEL6:
142: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
143: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
144: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
141: I = { `SETX ,`RAY_INSIDE_BOX ,32'd0 };
142: I = { `DIV ,`R6 ,`R1 ,`CREG_UNORMALIZED_DIRECTION };
143: I = { `JMP ,`LABEL_RAY_INSIDE_BOX ,`VOID ,`VOID };
 
//LABEL_ELSEZ:
145: I = { `SETZ ,`R5 ,32'b1 };
144: I = { `SETZ ,`R5 ,32'b1 };
 
//LABEL_RAY_INSIDE_BOX:
146: I = { `ZERO ,`R1 ,`VOID ,`VOID };
147: I = { `JEQX ,`LABEL_TEST_YZ_PLANE ,`R1 ,`RAY_INSIDE_BOX };
145: I = { `ZERO ,`R1 ,`VOID ,`VOID };
146: I = { `JEQX ,`LABEL_TEST_YZ_PLANE ,`R1 ,`RAY_INSIDE_BOX };
//BUG need a NOP here else pipeline gets confused
148: I = { `RETURN ,`RT_TRUE };
147: I = { `RETURN ,`RT_TRUE };
 
//LABEL_TEST_YZ_PLANE:
149: I = { `JNEX ,`LABEL_TEST_XZ_PLANE ,`R5 ,`R1 };
150: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_XXX };
151: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
152: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
153: I = { `JGEY ,`LABEL7 ,`R2 ,`CREG_AABBMIN };
154: I = { `RETURN ,`RT_FALSE };
148: I = { `JNEX ,`LABEL_TEST_XZ_PLANE ,`R5 ,`R1 };
149: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_XXX };
150: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
151: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
152: I = { `JGEY ,`LABEL7 ,`R2 ,`CREG_AABBMIN };
153: I = { `RETURN ,`RT_FALSE };
 
//LABEL7:
155: I = { `JLEY ,`LABEL8 ,`R2 ,`CREG_AABBMAX };
156: I = { `RETURN ,`RT_FALSE };
154: I = { `JLEY ,`LABEL8 ,`R2 ,`CREG_AABBMAX };
155: I = { `RETURN ,`RT_FALSE };
 
//LABEL8:
157: I = { `JGEZ ,`LABEL9 ,`R2 ,`CREG_AABBMIN };
158: I = { `RETURN ,`RT_FALSE };
156: I = { `JGEZ ,`LABEL9 ,`R2 ,`CREG_AABBMIN };
157: I = { `RETURN ,`RT_FALSE };
 
//LABEL9:
159: I = { `JLEZ ,`LABEL_TEST_XZ_PLANE ,`R2 ,`CREG_AABBMAX };
160: I = { `RETURN ,`RT_FALSE };
158: I = { `JLEZ ,`LABEL_TEST_XZ_PLANE ,`R2 ,`CREG_AABBMAX };
159: I = { `RETURN ,`RT_FALSE };
 
//LABEL_TEST_XZ_PLANE:
161: I = { `JNEY ,`LABEL_TEST_XY_PLANE ,`R5 ,`R1 };
162: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_YYY };
163: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
164: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
165: I = { `JGEX ,`LABEL10 ,`R2 ,`CREG_AABBMIN };
166: I = { `RETURN ,`RT_FALSE };
160: I = { `JNEY ,`LABEL_TEST_XY_PLANE ,`R5 ,`R1 };
161: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_YYY };
162: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
163: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
164: I = { `JGEX ,`LABEL10 ,`R2 ,`CREG_AABBMIN };
165: I = { `RETURN ,`RT_FALSE };
 
//LABEL10:
167: I = { `JLEX ,`LABEL11 ,`R2 ,`CREG_AABBMAX };
168: I = { `RETURN ,`RT_FALSE };
166: I = { `JLEX ,`LABEL11 ,`R2 ,`CREG_AABBMAX };
167: I = { `RETURN ,`RT_FALSE };
 
//LABEL11:
169: I = { `JGEZ ,`LABEL12 ,`R2 ,`CREG_AABBMIN };
170: I = { `RETURN ,`RT_FALSE };
168: I = { `JGEZ ,`LABEL12 ,`R2 ,`CREG_AABBMIN };
169: I = { `RETURN ,`RT_FALSE };
 
//LABEL12:
171: I = { `JLEZ ,`LABEL_TEST_XY_PLANE ,`R2 ,`CREG_AABBMAX };
172: I = { `RETURN ,`RT_FALSE };
170: I = { `JLEZ ,`LABEL_TEST_XY_PLANE ,`R2 ,`CREG_AABBMAX };
171: I = { `RETURN ,`RT_FALSE };
 
//LABEL_TEST_XY_PLANE:
173: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_ZZZ };
174: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
175: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
176: I = { `JGEX ,`LABEL13 ,`R2 ,`CREG_AABBMIN };
177: I = { `RETURN ,`RT_FALSE };
172: I = { `SWIZZLE3D ,`R6 ,`SWIZZLE_ZZZ };
173: I = { `MUL ,`R2 ,`CREG_UNORMALIZED_DIRECTION ,`R6 };
174: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
175: I = { `JGEX ,`LABEL13 ,`R2 ,`CREG_AABBMIN };
176: I = { `RETURN ,`RT_FALSE };
 
//LABEL13:
178: I = { `JLEX ,`LABEL14 ,`R2 ,`CREG_AABBMAX };
179: I = { `RETURN ,`RT_FALSE };
177: I = { `JLEX ,`LABEL14 ,`R2 ,`CREG_AABBMAX };
178: I = { `RETURN ,`RT_FALSE };
 
//LABEL14:
180: I = { `JGEY ,`LABEL15 ,`R2 ,`CREG_AABBMIN };
181: I = { `RETURN ,`RT_FALSE };
179: I = { `JGEY ,`LABEL15 ,`R2 ,`CREG_AABBMIN };
180: I = { `RETURN ,`RT_FALSE };
 
//LABEL15:
182: I = { `JLEY ,`LABEL_HIT ,`R2 ,`CREG_AABBMAX };
183: I = { `RETURN ,`RT_FALSE };
181: I = { `JLEY ,`LABEL_HIT ,`R2 ,`CREG_AABBMAX };
182: I = { `RETURN ,`RT_FALSE };
 
//LABEL_HIT:
184: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
185: I = { `RETURN ,`RT_TRUE };
183: I = { `SETX ,`CREG_LAST_t ,32'h1F40000 };
184: I = { `RETURN ,`RT_TRUE };
 
//------------------------------------------------------------------------
//BIU Micro code
//TAG_BIU_UCODE_ADDRESS:
186: I = { `ZERO ,`OREG_PIXEL_COLOR ,`VOID ,`VOID };
187: I = { `SETX ,`R3 ,`ONE };
188: I = { `SETX ,`R1 ,32'h00000 };
189: I = { `SUB ,`CREG_E1 ,`CREG_V1 ,`CREG_V0 };
190: I = { `SUB ,`CREG_E2 ,`CREG_V2 ,`CREG_V0 };
191: I = { `SUB ,`CREG_T ,`CREG_CAMERA_POSITION ,`CREG_V0 };
192: I = { `CROSS ,`CREG_P ,`CREG_RAY_DIRECTION ,`CREG_E2 };
193: I = { `CROSS ,`CREG_Q ,`CREG_T ,`CREG_E1 };
194: I = { `DOT ,`CREG_H1 ,`CREG_Q ,`CREG_E2 };
195: I = { `DOT ,`CREG_H2 ,`CREG_P ,`CREG_T };
196: I = { `DOT ,`CREG_H3 ,`CREG_Q ,`CREG_RAY_DIRECTION };
185: I = { `ZERO ,`OREG_PIXEL_COLOR ,`VOID ,`VOID };
186: I = { `SETY ,`R3 ,`ONE };
//SETX R1 32'h00000
187: I = { `SUB ,`CREG_E1 ,`CREG_V1 ,`CREG_V0 };
188: I = { `SUB ,`CREG_E2 ,`CREG_V2 ,`CREG_V0 };
189: I = { `SUB ,`CREG_T ,`CREG_CAMERA_POSITION ,`CREG_V0 };
190: I = { `CROSS ,`CREG_P ,`CREG_RAY_DIRECTION ,`CREG_E2 };
191: I = { `CROSS ,`CREG_Q ,`CREG_T ,`CREG_E1 };
 
192: I = { `DOT ,`CREG_H1 ,`CREG_Q ,`CREG_E2 };
193: I = { `DOT ,`R1 ,`CREG_P ,`CREG_T };
194: I = { `XCHANGEY ,`CREG_H1 ,`CREG_H1 ,`R1 };
195: I = { `DOT ,`R1 ,`CREG_Q ,`CREG_RAY_DIRECTION };
196: I = { `XCHANGEZ ,`CREG_H1 ,`CREG_H1 ,`R1 };
 
//DOT CREG_H1 CREG_Q CREG_E2
//DOT CREG_H2 CREG_P CREG_T
//DOT CREG_H3 CREG_Q CREG_RAY_DIRECTION
197: I = { `DOT ,`CREG_DELTA ,`CREG_P ,`CREG_E1 };
 
198: I = { `DIV ,`CREG_t ,`CREG_H1 ,`CREG_DELTA };
199: I = { `DIV ,`CREG_u ,`CREG_H2 ,`CREG_DELTA };
200: I = { `DIV ,`CREG_v ,`CREG_H3 ,`CREG_DELTA };
201: I = { `JGEX ,`LABEL_BIU1 ,`CREG_u ,`R1 };
202: I = { `NOP ,`RT_FALSE };
203: I = { `RET ,`R99 ,`FALSE };
//DIV CREG_t CREG_H1 CREG_DELTA
//DIV CREG_u CREG_H2 CREG_DELTA
//DIV CREG_v CREG_H3 CREG_DELTA
199: I = { `JGEY ,`LABEL_BIU1 ,`CREG_t ,`CREG_ZERO };
200: I = { `NOP ,`RT_FALSE };
201: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU1:
204: I = { `JGEX ,`LABEL_BIU2 ,`CREG_v ,`R1 };
205: I = { `NOP ,`RT_FALSE };
206: I = { `RET ,`R99 ,`FALSE };
//JGEX LABEL_BIU2 CREG_v R1
202: I = { `JGEZ ,`LABEL_BIU2 ,`CREG_t ,`CREG_ZERO };
203: I = { `NOP ,`RT_FALSE };
204: I = { `RET ,`R99 ,`FALSE };
 
//LABEL_BIU2:
207: I = { `ADD ,`R2 ,`CREG_u ,`CREG_v };
208: I = { `JLEX ,`LABEL_BIU3 ,`R2 ,`R3 };
//ADD R2 CREG_u CREG_v
205: I = { `COPY ,`R1 ,`CREG_t ,`VOID };
206: I = { `SWIZZLE3D ,`R1 ,`SWIZZLE_ZZZ };
207: I = { `ADD ,`R2 ,`R1 ,`CREG_t };
208: I = { `JLEY ,`LABEL_BIU3 ,`R2 ,`R3 };
//JLEX LABEL_BIU3 R2 R3
209: I = { `NOP ,`RT_FALSE };
210: I = { `RET ,`R99 ,`FALSE };
 
476,17 → 488,21
//LABEL_BIU3:
211: I = { `JGEX ,`LABEL_BIU4 ,`CREG_t ,`CREG_LAST_t };
212: I = { `COPY ,`CREG_LAST_t ,`CREG_t ,`VOID };
213: I = { `COPY ,`CREG_LAST_u ,`CREG_u ,`VOID };
214: I = { `COPY ,`CREG_LAST_v ,`CREG_v ,`VOID };
215: I = { `COPY ,`CREG_E1_LAST ,`CREG_E1 ,`VOID };
216: I = { `COPY ,`CREG_E2_LAST ,`CREG_E2 ,`VOID };
217: I = { `COPY ,`CREG_UV0_LAST ,`CREG_UV0 ,`VOID };
218: I = { `COPY ,`CREG_UV1_LAST ,`CREG_UV1 ,`VOID };
219: I = { `COPY ,`CREG_UV2_LAST ,`CREG_UV2 ,`VOID };
220: I = { `COPY ,`CREG_TRI_DIFFUSE_LAST ,`CREG_TRI_DIFFUSE ,`VOID };
221: I = { `RET ,`R99 ,`TRUE };
213: I = { `SWIZZLE3D ,`CREG_LAST_t ,`SWIZZLE_XXX };
214: I = { `COPY ,`CREG_LAST_u ,`CREG_t ,`VOID };
215: I = { `SWIZZLE3D ,`CREG_LAST_u ,`SWIZZLE_YYY };
216: I = { `COPY ,`CREG_LAST_v ,`CREG_t ,`VOID };
217: I = { `SWIZZLE3D ,`CREG_LAST_v ,`SWIZZLE_ZZZ };
 
218: I = { `COPY ,`CREG_E1_LAST ,`CREG_E1 ,`VOID };
219: I = { `COPY ,`CREG_E2_LAST ,`CREG_E2 ,`VOID };
220: I = { `COPY ,`CREG_UV0_LAST ,`CREG_UV0 ,`VOID };
221: I = { `COPY ,`CREG_UV1_LAST ,`CREG_UV1 ,`VOID };
222: I = { `COPY ,`CREG_UV2_LAST ,`CREG_UV2 ,`VOID };
223: I = { `COPY ,`CREG_TRI_DIFFUSE_LAST ,`CREG_TRI_DIFFUSE ,`VOID };
224: I = { `RET ,`R99 ,`TRUE };
//LABEL_BIU4:
222: I = { `RET ,`R99 ,`FALSE };
225: I = { `RET ,`R99 ,`FALSE };
 
 
//-------------------------------------------------------------------------
494,7 → 510,7
 
//TAG_TCC_UCODE_ADDRESS:
//Do this calculation only if this triangle is the one closest to the camera
223: I = { `JGX ,`LABEL_TCC_EXIT ,`CREG_t ,`CREG_LAST_t };
226: I = { `JGX ,`LABEL_TCC_EXIT ,`CREG_t ,`CREG_LAST_t };
 
//First get the UV coodrinates and store in R1
//R1x: u_coordinate = U0 + last_u * (U1 - U0) + last_v * (U2 - U0)
501,17 → 517,17
//R1y: v_coordinate = V0 + last_u * (V1 - V0) + last_v * (V2 - V0)
//R1z: 0
 
224: I = { `SUB ,`R1 ,`CREG_UV1_LAST ,`CREG_UV0_LAST };
225: I = { `SUB ,`R2 ,`CREG_UV2_LAST ,`CREG_UV0_LAST };
226: I = { `MUL ,`R1 ,`CREG_LAST_u ,`R1 };
227: I = { `MUL ,`R2 ,`CREG_LAST_v ,`R2 };
228: I = { `ADD ,`R1 ,`R1 ,`R2 };
229: I = { `ADD ,`R1 ,`R1 ,`CREG_UV0_LAST };
227: I = { `SUB ,`R1 ,`CREG_UV1_LAST ,`CREG_UV0_LAST };
228: I = { `SUB ,`R2 ,`CREG_UV2_LAST ,`CREG_UV0_LAST };
229: I = { `MUL ,`R1 ,`CREG_LAST_u ,`R1 };
230: I = { `MUL ,`R2 ,`CREG_LAST_v ,`R2 };
231: I = { `ADD ,`R1 ,`R1 ,`R2 };
232: I = { `ADD ,`R1 ,`R1 ,`CREG_UV0_LAST };
 
//R7x : fu = (u_coordinate) * gTexture.mWidth
//R7y : fv = (v_coordinate) * gTexture.mWidth
//R7z : 0
230: I = { `MUL ,`R7 ,`R1 ,`CREG_TEXTURE_SIZE };
233: I = { `MUL ,`R7 ,`R1 ,`CREG_TEXTURE_SIZE };
 
//R1x: u1 = ((int)fu) % gTexture.mWidth
//R1y: v1 = ((int)fv) % gTexture.mHeight
524,9 → 540,9
// textures are assumed to be squares!
//x % 2^n == x & (2^n - 1).
 
231: I = { `MOD ,`R1 ,`R7 ,`CREG_TEXTURE_SIZE };
232: I = { `INC ,`R2 ,`R1 ,`VOID };
233: I = { `MOD ,`R2 ,`R2 ,`CREG_TEXTURE_SIZE };
234: I = { `MOD ,`R1 ,`R7 ,`CREG_TEXTURE_SIZE };
235: I = { `INC ,`R2 ,`R1 ,`VOID };
236: I = { `MOD ,`R2 ,`R2 ,`CREG_TEXTURE_SIZE };
 
//Cool now we should store the values in the appropiate registers
//OREG_TEX_COORD1.x = u1 + v1 * gTexture.mWidth
540,40 → 556,40
//R2= [u2 v2 0]
 
//R2 = [v2 u2 0]
234: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YXZ };
237: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YXZ };
 
//R3 = [v2 v1 0]
235: I = { `XCHANGEX ,`R3 ,`R1 ,`R2 };
238: I = { `XCHANGEX ,`R3 ,`R1 ,`R2 };
 
 
//R4 = [u1 u2 0]
236: I = { `XCHANGEX ,`R4 ,`R2 ,`R1 };
239: I = { `XCHANGEX ,`R4 ,`R2 ,`R1 };
 
//R2 = [v2*H v1*H 0]
237: I = { `UNSCALE ,`R9 ,`R3 ,`VOID };
238: I = { `UNSCALE ,`R8 ,`CREG_TEXTURE_SIZE ,`VOID };
239: I = { `IMUL ,`R2 ,`R9 ,`R8 };
240: I = { `UNSCALE ,`R9 ,`R3 ,`VOID };
241: I = { `UNSCALE ,`R8 ,`CREG_TEXTURE_SIZE ,`VOID };
242: I = { `IMUL ,`R2 ,`R9 ,`R8 };
 
//OREG_TEX_COORD1 = [u1 + v2*H u2 + v1*H 0]
//R4 = FixedToIinteger(R4)
240: I = { `UNSCALE ,`R4 ,`R4 ,`VOID };
241: I = { `ADD ,`R12 ,`R2 ,`R4 };
242: I = { `SETX ,`R5 ,32'h3 };
243: I = { `SETY ,`R5 ,32'h3 };
244: I = { `SETZ ,`R5 ,32'h3 };
243: I = { `UNSCALE ,`R4 ,`R4 ,`VOID };
244: I = { `ADD ,`R12 ,`R2 ,`R4 };
245: I = { `SETX ,`R5 ,32'h3 };
246: I = { `SETY ,`R5 ,32'h3 };
247: I = { `SETZ ,`R5 ,32'h3 };
//Multiply by 3 (the pitch)
//IMUL OREG_TEX_COORD1 R12 R5
245: I = { `IMUL ,`CREG_TEX_COORD1 ,`R12 ,`R5 };
248: I = { `IMUL ,`CREG_TEX_COORD1 ,`R12 ,`R5 };
 
//R4 = [u2 u1 0]
246: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YXZ };
249: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YXZ };
 
 
//OREG_TEX_COORD2 [u2 + v2*H u1 + v1*H 0]
247: I = { `ADD ,`R12 ,`R2 ,`R4 };
250: I = { `ADD ,`R12 ,`R2 ,`R4 };
//Multiply by 3 (the pitch)
//IMUL OREG_TEX_COORD2 R12 R5
248: I = { `IMUL ,`CREG_TEX_COORD2 ,`R12 ,`R5 };
251: I = { `IMUL ,`CREG_TEX_COORD2 ,`R12 ,`R5 };
 
 
//Cool now get the weights
586,64 → 602,64
//R4x: fracu
//R4y: fracv
//R4z: 0
249: I = { `FRAC ,`R4 ,`R7 ,`VOID };
252: I = { `FRAC ,`R4 ,`R7 ,`VOID };
 
//R5x: fracv
//R5y: fracu
//R5z: 0
250: I = { `COPY ,`R5 ,`R4 ,`VOID };
251: I = { `SWIZZLE3D ,`R5 ,`SWIZZLE_YXZ };
253: I = { `COPY ,`R5 ,`R4 ,`VOID };
254: I = { `SWIZZLE3D ,`R5 ,`SWIZZLE_YXZ };
 
 
//R5x: 1 - fracv
//R5y: 1 - fracu
//R5y: 1
252: I = { `NEG ,`R5 ,`R5 ,`VOID };
253: I = { `INC ,`R5 ,`R5 ,`VOID };
255: I = { `NEG ,`R5 ,`R5 ,`VOID };
256: I = { `INC ,`R5 ,`R5 ,`VOID };
 
//R5x: 1 - fracv
//R5y: 1 - fracu
//R5y: (1 - fracv)(1 - fracu)
254: I = { `MULP ,`CREG_TEXWEIGHT1 ,`R5 ,`VOID };
257: I = { `MULP ,`CREG_TEXWEIGHT1 ,`R5 ,`VOID };
 
//CREG_TEXWEIGHT1.x = (1 - fracv)(1 - fracu)
//CREG_TEXWEIGHT1.y = (1 - fracv)(1 - fracu)
//CREG_TEXWEIGHT1.z = (1 - fracv)(1 - fracu)
255: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT1 ,`SWIZZLE_ZZZ };
258: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT1 ,`SWIZZLE_ZZZ };
 
 
//R6x: w2: fracu * (1 - fracv )
//R6y: w3: fracv * (1 - fracu )
//R6z: 0
256: I = { `MUL ,`R6 ,`R4 ,`R5 };
259: I = { `MUL ,`R6 ,`R4 ,`R5 };
 
//CREG_TEXWEIGHT2.x = fracu * (1 - fracv )
//CREG_TEXWEIGHT2.y = fracu * (1 - fracv )
//CREG_TEXWEIGHT2.z = fracu * (1 - fracv )
257: I = { `COPY ,`CREG_TEXWEIGHT2 ,`R6 ,`VOID };
258: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT2 ,`SWIZZLE_XXX };
260: I = { `COPY ,`CREG_TEXWEIGHT2 ,`R6 ,`VOID };
261: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT2 ,`SWIZZLE_XXX };
 
//CREG_TEXWEIGHT3.x = fracv * (1 - fracu )
//CREG_TEXWEIGHT3.y = fracv * (1 - fracu )
//CREG_TEXWEIGHT3.z = fracv * (1 - fracu )
259: I = { `COPY ,`CREG_TEXWEIGHT3 ,`R6 ,`VOID };
260: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT3 ,`SWIZZLE_YYY };
262: I = { `COPY ,`CREG_TEXWEIGHT3 ,`R6 ,`VOID };
263: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT3 ,`SWIZZLE_YYY };
 
 
//R4x: fracu
//R4y: fracv
//R4z: fracu * fracv
261: I = { `MULP ,`R4 ,`R4 ,`VOID };
264: I = { `MULP ,`R4 ,`R4 ,`VOID };
 
//CREG_TEXWEIGHT4.x = fracv * fracu
//CREG_TEXWEIGHT4.y = fracv * fracu
//CREG_TEXWEIGHT4.z = fracv * fracu
262: I = { `COPY ,`CREG_TEXWEIGHT4 ,`R4 ,`VOID };
263: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT4 ,`SWIZZLE_ZZZ };
265: I = { `COPY ,`CREG_TEXWEIGHT4 ,`R4 ,`VOID };
266: I = { `SWIZZLE3D ,`CREG_TEXWEIGHT4 ,`SWIZZLE_ZZZ };
 
 
//LABEL_TCC_EXIT:
264: I = { `RET ,`R99 ,32'h0 };
267: I = { `RET ,`R99 ,32'h0 };
 
 
//-------------------------------------------------------------------------
652,22 → 668,22
//This pixel shader has diffuse light but no textures
 
265: I = { `CROSS ,`R1 ,`CREG_E1_LAST ,`CREG_E2_LAST };
266: I = { `MAG ,`R2 ,`R1 ,`VOID };
267: I = { `DIV ,`R1 ,`R1 ,`R2 };
268: I = { `MUL ,`R2 ,`CREG_RAY_DIRECTION ,`CREG_LAST_t };
269: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
270: I = { `SUB ,`R2 ,`CURRENT_LIGHT_POS ,`R2 };
271: I = { `MAG ,`R3 ,`R2 ,`VOID };
272: I = { `DIV ,`R2 ,`R2 ,`R3 };
273: I = { `DOT ,`R3 ,`R2 ,`R1 };
274: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_TRI_DIFFUSE_LAST ,`CURRENT_LIGHT_DIFFUSE };
275: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_COLOR_ACC ,`R3 };
276: I = { `COPY ,`CREG_TEXTURE_COLOR ,`CREG_COLOR_ACC ,`VOID };
277: I = { `NOP ,`RT_FALSE };
278: I = { `NOP ,`RT_FALSE };
279: I = { `NOP ,`RT_FALSE };
280: I = { `RET ,`R99 ,`TRUE };
268: I = { `CROSS ,`R1 ,`CREG_E1_LAST ,`CREG_E2_LAST };
269: I = { `MAG ,`R2 ,`R1 ,`VOID };
270: I = { `DIV ,`R1 ,`R1 ,`R2 };
271: I = { `MUL ,`R2 ,`CREG_RAY_DIRECTION ,`CREG_LAST_t };
272: I = { `ADD ,`R2 ,`R2 ,`CREG_CAMERA_POSITION };
273: I = { `SUB ,`R2 ,`CURRENT_LIGHT_POS ,`R2 };
274: I = { `MAG ,`R3 ,`R2 ,`VOID };
275: I = { `DIV ,`R2 ,`R2 ,`R3 };
276: I = { `DOT ,`R3 ,`R2 ,`R1 };
277: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_TRI_DIFFUSE_LAST ,`CURRENT_LIGHT_DIFFUSE };
278: I = { `MUL ,`CREG_COLOR_ACC ,`CREG_COLOR_ACC ,`R3 };
279: I = { `COPY ,`CREG_TEXTURE_COLOR ,`CREG_COLOR_ACC ,`VOID };
280: I = { `NOP ,`RT_FALSE };
281: I = { `NOP ,`RT_FALSE };
282: I = { `NOP ,`RT_FALSE };
283: I = { `RET ,`R99 ,`TRUE };
 
//-------------------------------------------------------------------------
//Pixel Shader #2
677,30 → 693,30
 
 
 
281: I = { `COPY ,`R1 ,`CREG_TEX_COORD1 ,`VOID };
282: I = { `COPY ,`R2 ,`CREG_TEX_COORD1 ,`VOID };
283: I = { `COPY ,`R3 ,`CREG_TEX_COORD2 ,`VOID };
284: I = { `COPY ,`R4 ,`CREG_TEX_COORD2 ,`VOID };
284: I = { `COPY ,`R1 ,`CREG_TEX_COORD1 ,`VOID };
285: I = { `COPY ,`R2 ,`CREG_TEX_COORD1 ,`VOID };
286: I = { `COPY ,`R3 ,`CREG_TEX_COORD2 ,`VOID };
287: I = { `COPY ,`R4 ,`CREG_TEX_COORD2 ,`VOID };
 
 
285: I = { `SWIZZLE3D ,`R1 ,`SWIZZLE_XXX };
286: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YYY };
287: I = { `SWIZZLE3D ,`R3 ,`SWIZZLE_XXX };
288: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YYY };
289: I = { `ADD ,`R1 ,`R1 ,`CREG_012 };
290: I = { `ADD ,`R2 ,`R2 ,`CREG_012 };
291: I = { `ADD ,`R3 ,`R3 ,`CREG_012 };
292: I = { `ADD ,`R4 ,`R4 ,`CREG_012 };
288: I = { `SWIZZLE3D ,`R1 ,`SWIZZLE_XXX };
289: I = { `SWIZZLE3D ,`R2 ,`SWIZZLE_YYY };
290: I = { `SWIZZLE3D ,`R3 ,`SWIZZLE_XXX };
291: I = { `SWIZZLE3D ,`R4 ,`SWIZZLE_YYY };
292: I = { `ADD ,`R1 ,`R1 ,`CREG_012 };
293: I = { `ADD ,`R2 ,`R2 ,`CREG_012 };
294: I = { `ADD ,`R3 ,`R3 ,`CREG_012 };
295: I = { `ADD ,`R4 ,`R4 ,`CREG_012 };
 
 
293: I = { `TMREAD ,`CREG_TEX_COLOR1 ,`R1 ,`VOID };
294: I = { `NOP ,`RT_FALSE };
295: I = { `TMREAD ,`CREG_TEX_COLOR2 ,`R2 ,`VOID };
296: I = { `NOP ,`RT_FALSE };
297: I = { `TMREAD ,`CREG_TEX_COLOR3 ,`R3 ,`VOID };
298: I = { `NOP ,`RT_FALSE };
299: I = { `TMREAD ,`CREG_TEX_COLOR4 ,`R4 ,`VOID };
300: I = { `NOP ,`RT_FALSE };
296: I = { `TMREAD ,`CREG_TEX_COLOR1 ,`R1 ,`VOID };
297: I = { `NOP ,`RT_FALSE };
298: I = { `TMREAD ,`CREG_TEX_COLOR2 ,`R2 ,`VOID };
299: I = { `NOP ,`RT_FALSE };
300: I = { `TMREAD ,`CREG_TEX_COLOR3 ,`R3 ,`VOID };
301: I = { `NOP ,`RT_FALSE };
302: I = { `TMREAD ,`CREG_TEX_COLOR4 ,`R4 ,`VOID };
303: I = { `NOP ,`RT_FALSE };
 
 
 
715,15 → 731,15
//MUL R3 CREG_TEX_COLOR1 CREG_TEXWEIGHT3
//MUL R4 CREG_TEX_COLOR3 CREG_TEXWEIGHT4
 
301: I = { `MUL ,`R1 ,`CREG_TEX_COLOR3 ,`CREG_TEXWEIGHT1 };
302: I = { `MUL ,`R2 ,`CREG_TEX_COLOR2 ,`CREG_TEXWEIGHT2 };
303: I = { `MUL ,`R3 ,`CREG_TEX_COLOR1 ,`CREG_TEXWEIGHT3 };
304: I = { `MUL ,`R4 ,`CREG_TEX_COLOR4 ,`CREG_TEXWEIGHT4 };
304: I = { `MUL ,`R1 ,`CREG_TEX_COLOR3 ,`CREG_TEXWEIGHT1 };
305: I = { `MUL ,`R2 ,`CREG_TEX_COLOR2 ,`CREG_TEXWEIGHT2 };
306: I = { `MUL ,`R3 ,`CREG_TEX_COLOR1 ,`CREG_TEXWEIGHT3 };
307: I = { `MUL ,`R4 ,`CREG_TEX_COLOR4 ,`CREG_TEXWEIGHT4 };
 
305: I = { `ADD ,`CREG_TEXTURE_COLOR ,`R1 ,`R2 };
306: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R3 };
307: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R4 };
308: I = { `RET ,`R99 ,`TRUE };
308: I = { `ADD ,`CREG_TEXTURE_COLOR ,`R1 ,`R2 };
309: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R3 };
310: I = { `ADD ,`CREG_TEXTURE_COLOR ,`CREG_TEXTURE_COLOR ,`R4 };
311: I = { `RET ,`R99 ,`TRUE };
 
 
//-------------------------------------------------------------------------
730,18 → 746,17
//Default User constants
//TAG_USERCONSTANTS:
 
309: I = { `NOP ,`RT_FALSE };
310: I = { `RETURN ,`RT_FALSE };
312: I = { `NOP ,`RT_FALSE };
313: I = { `RETURN ,`RT_FALSE };
 
//TAG_PIXELSHADER:
//Default Pixel Shader (just outputs texture)
311: I = { `OMWRITE ,`OREG_PIXEL_COLOR ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_TEXTURE_COLOR };
312: I = { `NOP ,`RT_FALSE };
313: I = { `RET ,`R99 ,`TRUE };
314: I = { `NOP ,`RT_FALSE };
314: I = { `OMWRITE ,`OREG_PIXEL_COLOR ,`CREG_CURRENT_OUTPUT_PIXEL ,`CREG_TEXTURE_COLOR };
315: I = { `NOP ,`RT_FALSE };
316: I = { `RET ,`R99 ,`TRUE };
317: I = { `NOP ,`RT_FALSE };
 
 
 
//-------------------------------------------------------------------------
 
/branches/icarus_version/examples/scenes/example1/Instructions.mem
2,15 → 2,15
//--------------------------------------
//Subroutine Entry Point Table
00000000 00000000 //ENTRYPOINT_ADRR_INITIAL
00000000 00000046 //ENTRYPOINT_ADRR_CPPU
00000000 0000004A //ENTRYPOINT_ADRR_RGU
00000000 00000062 //ENTRYPOINT_ADRR_AABBIU
00000000 000000BA //ENTRYPOINT_ADRR_BIU
00000000 00000109 //ENTRYPOINT_ADRR_PSU
00000000 00000119 //ENTRYPOINT_ADRR_PSU2
00000000 000000DF //ENTRYPOINT_ADRR_TCC
00000000 00000052 //ENTRYPOINT_ADRR_NPG
00000000 00000135 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 00000045 //ENTRYPOINT_ADRR_CPPU
00000000 00000049 //ENTRYPOINT_ADRR_RGU
00000000 00000061 //ENTRYPOINT_ADRR_AABBIU
00000000 000000B9 //ENTRYPOINT_ADRR_BIU
00000000 0000010C //ENTRYPOINT_ADRR_PSU
00000000 0000011C //ENTRYPOINT_ADRR_PSU2
00000000 000000E2 //ENTRYPOINT_ADRR_TCC
00000000 00000051 //ENTRYPOINT_ADRR_NPG
00000000 00000138 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 0000800C //ENTRYPOINT_ADRR_PIXELSHADER
00000000 00000025 //ENTRYPOINT_ADRR_MAIN
//--------------------------------------
/branches/icarus_version/examples/scenes/example2/Instructions.mem
2,15 → 2,15
//--------------------------------------
//Subroutine Entry Point Table
00000000 00000000 //ENTRYPOINT_ADRR_INITIAL
00000000 00000046 //ENTRYPOINT_ADRR_CPPU
00000000 0000004A //ENTRYPOINT_ADRR_RGU
00000000 00000062 //ENTRYPOINT_ADRR_AABBIU
00000000 000000BA //ENTRYPOINT_ADRR_BIU
00000000 00000109 //ENTRYPOINT_ADRR_PSU
00000000 00000119 //ENTRYPOINT_ADRR_PSU2
00000000 000000DF //ENTRYPOINT_ADRR_TCC
00000000 00000052 //ENTRYPOINT_ADRR_NPG
00000000 00000135 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 00000045 //ENTRYPOINT_ADRR_CPPU
00000000 00000049 //ENTRYPOINT_ADRR_RGU
00000000 00000061 //ENTRYPOINT_ADRR_AABBIU
00000000 000000B9 //ENTRYPOINT_ADRR_BIU
00000000 0000010C //ENTRYPOINT_ADRR_PSU
00000000 0000011C //ENTRYPOINT_ADRR_PSU2
00000000 000000E2 //ENTRYPOINT_ADRR_TCC
00000000 00000051 //ENTRYPOINT_ADRR_NPG
00000000 00000138 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 0000800C //ENTRYPOINT_ADRR_PIXELSHADER
00000000 00000025 //ENTRYPOINT_ADRR_MAIN
//--------------------------------------
/branches/icarus_version/examples/scenes/example3/Instructions.mem
2,15 → 2,15
//--------------------------------------
//Subroutine Entry Point Table
00000000 00000000 //ENTRYPOINT_ADRR_INITIAL
00000000 00000046 //ENTRYPOINT_ADRR_CPPU
00000000 0000004A //ENTRYPOINT_ADRR_RGU
00000000 00000062 //ENTRYPOINT_ADRR_AABBIU
00000000 000000BA //ENTRYPOINT_ADRR_BIU
00000000 00000109 //ENTRYPOINT_ADRR_PSU
00000000 00000119 //ENTRYPOINT_ADRR_PSU2
00000000 000000DF //ENTRYPOINT_ADRR_TCC
00000000 00000052 //ENTRYPOINT_ADRR_NPG
00000000 00000135 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 00000045 //ENTRYPOINT_ADRR_CPPU
00000000 00000049 //ENTRYPOINT_ADRR_RGU
00000000 00000061 //ENTRYPOINT_ADRR_AABBIU
00000000 000000B9 //ENTRYPOINT_ADRR_BIU
00000000 0000010C //ENTRYPOINT_ADRR_PSU
00000000 0000011C //ENTRYPOINT_ADRR_PSU2
00000000 000000E2 //ENTRYPOINT_ADRR_TCC
00000000 00000051 //ENTRYPOINT_ADRR_NPG
00000000 00000138 //ENTRYPOINT_ADRR_USERCONSTANTS
00000000 0000800C //ENTRYPOINT_ADRR_PIXELSHADER
00000000 00000025 //ENTRYPOINT_ADRR_MAIN
//--------------------------------------

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