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URL https://opencores.org/ocsvn/thor/thor/trunk

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  • This comparison shows the changes necessary to convert path 
    /thor/trunk/FT64/rtl/lib
    from Rev 43 to Rev 46
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Rev 43 → Rev 46

/ParallelToSerial.v
0,0 → 1,47
// ============================================================================
// 2006,2007,2011 Robert Finch
// robfinch@<remove>sympatico.ca
//
// ParallelToSerial.v
// Parallel to serial data converter (shift register).
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module ParallelToSerial(rst, clk, ce, ld, qin, d, qh);
parameter WID=8;
input rst; // reset
input clk; // clock
input ce; // clock enable
input ld; // load
input qin; // serial shifting input
input [WID:1] d; // data to load
output qh; // serial output
 
reg [WID:1] q;
 
always @(posedge clk)
if (rst)
q <= 0;
else if (ce) begin
if (ld)
q <= d;
else
q <= {q[WID-1:1],qin};
end
 
assign qh = q[WID];
 
endmodule
/VT151.v
0,0 → 1,56
// ============================================================================
// 2007 Robert Finch
// robfinch@<remove>sympatico.ca
//
// 74LS151 mux
// 8-to-1 mux with enable
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module VT151(e_n, s, i0, i1, i2, i3, i4, i5, i6, i7, z, z_n);
parameter WID=1;
input e_n;
input [2:0] s;
input [WID:1] i0;
input [WID:1] i1;
input [WID:1] i2;
input [WID:1] i3;
input [WID:1] i4;
input [WID:1] i5;
input [WID:1] i6;
input [WID:1] i7;
output [WID:1] z;
output [WID:1] z_n;
 
reg [WID:1] z;
 
always @(e_n or s or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
case({e_n,s})
4'b0000: z <= i0;
4'b0001: z <= i1;
4'b0010: z <= i2;
4'b0011: z <= i3;
4'b0100: z <= i4;
4'b0101: z <= i5;
4'b0110: z <= i6;
4'b0111: z <= i7;
default: z <= {WID{1'b0}};
endcase
 
assign z_n = ~z;
 
endmodule
/VT163.v
0,0 → 1,50
// ============================================================================
// 2007 Robert Finch
// robfinch@<remove>sympatico.ca
//
// VT163 - 74LS163 counter
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
// Webpack 9.1i xc3s1000-4ft256
// 4 slices / 8 LUTs / 324.675 MHz
 
module VT163(clk, clr_n, ent, enp, ld_n, d, q, rco);
parameter WID=4;
input clk;
input clr_n; // clear active low
input ent; // clock enable
input enp; // clock enable
input ld_n; // load active low
input [WID:1] d;
output [WID:1] q;
reg [WID:1] q;
output rco;
 
assign rco = &{q[WID:1],ent};
 
always @(posedge clk)
begin
if (!clr_n)
q <= {WID{1'b0}};
else if (!ld_n)
q <= d;
else if (enp & ent)
q <= q + {{WID-1{1'b0}},1'b1};
end
 
endmodule
/change_det.v
0,0 → 1,41
// ============================================================================
// 2006 Robert Finch
// robfinch@<remove>sympatico.ca
//
// change_det.v
// - detects a change in a value
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module change_det(rst, clk, ce, i, cd);
parameter WID=32;
input rst; // reset
input clk; // clock
input ce; // clock enable
input [WID:1] i; // input signal
output cd; // change detected
 
reg [WID:1] hold;
 
always @(posedge clk)
if (rst)
hold <= i;
else if (ce)
hold <= i;
 
assign cd = i != hold;
 
endmodule
/counter.v
0,0 → 1,49
// ============================================================================
// (C) 2007 Robert Finch
// All Rights Reserved.
//
// counter.v
// generic up counter
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module counter(rst, clk, ce, ld, d, q, tc);
parameter WID=8;
parameter pMaxCnt={WID{1'b1}};
input rst;
input clk;
input ce;
input ld;
input [WID:1] d;
output [WID:1] q;
reg [WID:1] q;
output tc;
 
assign tc = &q;
 
always @(posedge clk)
if (rst)
q <= 1'b0;
else if (ce) begin
if (ld)
q <= d;
else if (tc)
q <= 1'b0;
else
q <= q + 1'b1;
end
 
endmodule
/down_counter.v
0,0 → 1,58
// ============================================================================
// down_counter.v
// - counts down
//
//
// 2010 Robert Finch
// pfingh>remove<@birdcomputer.ca
//
//
// This source code is available for evaluation and validation purposes
// only. This copyright statement and disclaimer must remain present in
// the file.
//
//
// NO WARRANTY.
// THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
// EXPRESS OR IMPLIED. The user must assume the entire risk of using the
// Work.
//
// IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
// INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
// THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
//
// IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
// IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
// REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
// LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
// AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
// LOSSES RELATING TO SUCH UNAUTHORIZED USE.
//
//
// Verilog 1995
// ============================================================================
 
module down_counter(rst, clk, ce, ld, d, q, z);
parameter WID=8;
input rst;
input clk;
input ce;
input ld;
input [WID:1] d;
output [WID:1] q;
reg [WID:1] q;
output z;
 
always @(posedge clk)
if (rst)
q <= 0;
else if (ce) begin
if (ld)
q <= d;
else
q <= q + {WID{1'b1}};
end
 
assign z = q == 0;
 
endmodule
/vtdl.v
0,0 → 1,59
//=============================================================================
// (C) 2007,2012 Robert Finch, Stratford
// robfinch<remove>@opencores.org
//
//
// vtdl - variable tap delay line
// (dynamic shift register)
//
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//
// Notes:
//
// This module acts like a clocked delay line with a variable tap.
// Miscellaneous usage in rate control circuitry such as fifo's.
// Capable of delaying a signal bus.
// Signal bus width is specified with the WID parameter.
//
// Verilog 1995
// Ref: Webpack9.1i xc3s1000-4ft256
// 4 slices / 8 LUTs / < 10ns
//=============================================================================
//
module vtdl(clk, ce, a, d, q);
parameter WID = 8;
parameter DEP = 16;
localparam AMSB = DEP>64?6:DEP>32?5:DEP>16?4:DEP>8?3:DEP>4?2:DEP>2?1:0;
input clk;
input ce;
input [AMSB:0] a;
input [WID-1:0] d;
output [WID-1:0] q;
 
reg [WID-1:0] m [DEP-1:0];
integer n;
 
always @(posedge clk)
if (ce) begin
for (n = 1; n < DEP; n = n + 1)
m[n] <= m[n-1];
m[0] <= d;
end
 
assign q = m[a];
 
endmodule

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