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https://opencores.org/ocsvn/thor/thor/trunk
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- This comparison shows the changes necessary to convert path
/thor/trunk/FT64v5/rtl/common
- from Rev 53 to Rev 55
- ↔ Reverse comparison
Rev 53 → Rev 55
/FT64_alu.v
1114,9 → 1114,9
`LUI: |
begin |
if (instr[7:6]==2'b01) |
o[63:0] = {instr[47:13],30'd0}; |
o = {instr[47:13],30'd0}; |
else |
o[63:0] = {{15{instr[31]}},instr[31:13],30'd0}; |
o = {{15{instr[31]}},instr[31:13],30'd0}; |
end |
`ADDI: o[63:0] = a + b; |
`SLTI: o[63:0] = $signed(a) < $signed(b); |
1143,17 → 1143,18
end |
`LWR,`SWC,`CAS: |
begin |
o[63:0] = a + b; |
o = a + b; |
end |
`LV,`SV: begin |
o[63:0] = a + b + {ven,3'b0}; |
o = a + b + {ven,3'b0}; |
end |
`CSRRW: case(instr[27:18]) |
10'h044: o[63:0] = BIG ? csr | {thrd,24'h0} : 64'hDDDDDDDDDDDDDDDD; |
default: o[63:0] = BIG ? csr : 64'hDDDDDDDDDDDDDDDD; |
`CSRRW: |
case(instr[27:18]) |
10'h044: o = BIG ? (csr | {39'd0,thrd,24'h0}) : 64'hDDDDDDDDDDDDDDDD; |
default: o = BIG ? csr : 64'hDDDDDDDDDDDDDDDD; |
endcase |
`BITFIELD: o[63:0] = BIG ? bfout : 64'hCCCCCCCCCCCCCCCC; |
default: o[63:0] = 64'hDEADDEADDEADDEAD; |
`BITFIELD: o = BIG ? bfout : 64'hCCCCCCCCCCCCCCCC; |
default: o = 64'hDEADDEADDEADDEAD; |
endcase |
end |
|
/FT64_config.vh
24,6 → 24,7
// |
`define SIM 1'b1 |
//`define SUPPORT_SMT 1'b1 |
`define SUPPORT_VECTOR 1'b1 |
//`define DEBUG_LOGIC 1'b1 |
|
`define AMSB 31 |
/FT64_defines.vh
221,6 → 221,7
`define JAL 6'h18 |
`define CALL 6'h19 |
`define INC 6'h1A |
`define LFx 6'h1B |
`define SGTUI 6'h1C |
`define LWR 6'h1D |
`define CACHE 6'h1E |
237,7 → 238,9
`define LUI 6'h27 |
`define JMP 6'h28 |
`define RET 6'h29 |
`define SFx 6'h2B |
`define SGTI 6'h2C |
`define CMPRSSD 6'h2D |
`define MODI 6'h2E |
`define AMO 6'h2F |
`define AMO_SWAP 6'h00 |
/FT64_idecoder.v
737,6 → 737,7
`CAS: IsRFW = TRUE; |
`AMO: IsRFW = TRUE; |
`CSRRW: IsRFW = TRUE; |
`LUI: IsRFW = TRUE; |
default: IsRFW = FALSE; |
endcase |
endfunction |
940,11 → 941,14
bus <= 144'h0; |
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} : |
{{50{instr[31]}},instr[31:18]}; |
case(instr[7:6]) |
2'b00: bus[`IB_LN] <= 3'd4; |
2'b01: bus[`IB_LN] <= 3'd6; |
default: bus[`IB_LN] <= 3'd2; |
endcase |
if (instr[`INSTRUCTION_OP]==`CMPRSSD) |
bus[`IB_LN] <= 3'd2; |
else |
case(instr[7:6]) |
2'b00: bus[`IB_LN] <= 3'd4; |
2'b01: bus[`IB_LN] <= 3'd6; |
default: bus[`IB_LN] <= 3'd2; |
endcase |
// bus[`IB_RT] <= fnRt(instr,ven,vl,thrd) | {thrd,7'b0}; |
// bus[`IB_RC] <= fnRc(instr,ven,thrd) | {thrd,7'b0}; |
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0}; |
/FT64_mpu.v
40,7 → 40,7
input pit_clk2; |
input pit_gate2; |
output pit_out2; |
output [2:0] irq_o; |
output [3:0] irq_o; |
input i1; |
input i2; |
input i3; |
100,7 → 100,7
wire crd_ack; |
wire [63:0] crd_dato; |
wire ack; |
wire [2:0] ol; |
wire [1:0] ol; |
wire [31:0] pcr; |
wire [63:0] pcr2; |
wire icl; // instruction cache load |