URL
https://opencores.org/ocsvn/thor/thor/trunk
Subversion Repositories thor
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- This comparison shows the changes necessary to convert path
/thor/trunk/FT64v5/rtl/common
- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/FT64_InsLength.v
25,6 → 25,7
// without the use of this module. |
// ============================================================================ |
// |
`include "FT64_config.vh" |
`include "FT64_defines.vh" |
|
module FT64_InsLength(ins, len); |
32,9 → 33,11
output reg [2:0] len; |
|
always @* |
`ifdef SUPPORT_DCI |
if (ins[`INSTRUCTION_OP]==`CMPRSSD) |
len <= 3'd2; |
else |
`endif |
case(ins[7:6]) |
2'd0: len <= 3'd4; |
2'd1: len <= 3'd6; |
/FT64_cache.v
740,16 → 740,18
// ----------------------------------------------------------------------------- |
// ----------------------------------------------------------------------------- |
|
module FT64_dcache_tag(wclk, wr, wadr, rclk, radr, hit0, hit1); |
module FT64_dcache_tag(wclk, wr, wadr, rclk, radr, whit, hit0, hit1); |
input wclk; |
input wr; |
input [37:0] wadr; |
input rclk; |
input [37:0] radr; |
output reg whit; |
output reg hit0; |
output reg hit1; |
|
wire [31:0] tago0, tago1; |
wire [31:0] wtago; |
wire [37:0] radrp8 = radr + 32'd32; |
|
FT64_dcache_tag2 u1 ( |
758,6 → 760,7
.wea(wr), // input wire [0 : 0] wea |
.addra(wadr[13:5]), // input wire [8 : 0] addra |
.dina(wadr[37:14]), // input wire [31 : 0] dina |
.douta(wtago), |
.clkb(rclk), // input wire clkb |
.web(1'b0), |
.dinb(32'd0), |
784,6 → 787,8
hit0 <= tago0[23:0]==radr[37:14]; |
always @(posedge rclk) |
hit1 <= tago1[23:0]==radrp8[37:14]; |
always @(posedge wclk) |
whit <= wtago[23:0]==wadr[37:14]; |
|
endmodule |
|
790,12 → 795,13
// ----------------------------------------------------------------------------- |
// ----------------------------------------------------------------------------- |
|
module FT64_dcache(rst, wclk, wr, sel, wadr, i, li, rclk, rdsize, radr, o, lo, hit, hit0, hit1); |
module FT64_dcache(rst, wclk, wr, sel, wadr, whit, i, li, rclk, rdsize, radr, o, lo, hit, hit0, hit1); |
input rst; |
input wclk; |
input wr; |
input [7:0] sel; |
input [37:0] wadr; |
output whit; |
input [63:0] i; |
input [255:0] li; // line input |
input rclk; |
849,6 → 855,7
.wadr(wadr), |
.rclk(rclk), |
.radr(radr), |
.whit(whit), |
.hit0(hit0a), |
.hit1(hit1a) |
); |
/FT64_config.vh
25,6 → 25,7
`define SIM 1'b1 |
//`define SUPPORT_SMT 1'b1 |
`define SUPPORT_VECTOR 1'b1 |
//`define SUPPORT_DCI 1'b1 // dynamically compressed instructions |
//`define DEBUG_LOGIC 1'b1 |
|
`define AMSB 31 |
36,7 → 37,7
//`define SUPPORT_DBG 1'b1 |
`define FULL_ISSUE_LOGIC 1'b1 |
|
`define WAYS 2 // number of ways parallel (not working yet) |
`define WAYS 2 // number of ways parallel (1-3 3 not working yet) |
`define NUM_IDU 2 // number of instruction decode units (1-3) |
`define NUM_ALU 2 // number of ALU's (1-2) |
`define NUM_MEM 2 // number of memory queues (1-3) |
/FT64_idecoder.v
942,9 → 942,11
bus <= 144'h0; |
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} : |
{{50{instr[31]}},instr[31:18]}; |
`ifdef SUPPORT_DCI |
if (instr[`INSTRUCTION_OP]==`CMPRSSD) |
bus[`IB_LN] <= 3'd2; |
else |
`endif |
case(instr[7:6]) |
2'b00: bus[`IB_LN] <= 3'd4; |
2'b01: bus[`IB_LN] <= 3'd6; |