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    /thor/trunk/FT64v5/rtl/common
    from Rev 57 to Rev 58
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Rev 57 → Rev 58

/FT64_cache.v
38,11 → 38,12
module FT64_L1_icache_mem(rst, clk, wr, en, lineno, i, o, ov, invall, invline);
parameter pLines = 64;
parameter pLineWidth = 288;
localparam pLNMSB = pLines==128 ? 6 : 5;
input rst;
input clk;
input wr;
input [8:0] en;
input [5:0] lineno;
input [pLNMSB:0] lineno;
input [pLineWidth-1:0] i;
output [pLineWidth-1:0] o;
output [8:0] ov;
191,29 → 192,32
// -----------------------------------------------------------------------------
 
module FT64_L1_icache_cmptag4way(rst, clk, nxt, wr, adr, lineno, hit);
parameter pLines = 64;
localparam pLNMSB = pLines==128 ? 6 : 5;
localparam pMSB = pLines==128 ? 9 : 8;
input rst;
input clk;
input nxt;
input wr;
input [37:0] adr;
output reg [5:0] lineno;
output reg [pLNMSB:0] lineno;
output hit;
 
(* ram_style="distributed" *)
reg [32:0] mem0 [0:15];
reg [32:0] mem1 [0:15];
reg [32:0] mem2 [0:15];
reg [32:0] mem3 [0:15];
reg [32:0] mem0 [0:pLines/4-1];
reg [32:0] mem1 [0:pLines/4-1];
reg [32:0] mem2 [0:pLines/4-1];
reg [32:0] mem3 [0:pLines/4-1];
reg [37:0] rradr;
integer n;
initial begin
for (n = 0; n < 16; n = n + 1)
begin
mem0[n] = 0;
mem1[n] = 0;
mem2[n] = 0;
mem3[n] = 0;
end
for (n = 0; n < pLines/4; n = n + 1)
begin
mem0[n] = 0;
mem1[n] = 0;
mem2[n] = 0;
mem3[n] = 0;
end
end
 
wire [21:0] lfsro;
225,24 → 229,24
else begin
if (wr) begin
case(lfsro[1:0])
2'b00: begin mem0[adr[8:5]] <= adr[37:5]; wlineno <= {2'b00,adr[8:5]}; end
2'b01: begin mem1[adr[8:5]] <= adr[37:5]; wlineno <= {2'b01,adr[8:5]}; end
2'b10: begin mem2[adr[8:5]] <= adr[37:5]; wlineno <= {2'b10,adr[8:5]}; end
2'b11: begin mem3[adr[8:5]] <= adr[37:5]; wlineno <= {2'b11,adr[8:5]}; end
2'b00: begin mem0[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b00,adr[pMSB:5]}; end
2'b01: begin mem1[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b01,adr[pMSB:5]}; end
2'b10: begin mem2[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b10,adr[pMSB:5]}; end
2'b11: begin mem3[adr[pMSB:5]] <= adr[37:5]; wlineno <= {2'b11,adr[pMSB:5]}; end
endcase
end
end
 
wire hit0 = mem0[adr[8:5]]==adr[37:5];
wire hit1 = mem1[adr[8:5]]==adr[37:5];
wire hit2 = mem2[adr[8:5]]==adr[37:5];
wire hit3 = mem3[adr[8:5]]==adr[37:5];
wire hit0 = mem0[adr[pMSB:5]]==adr[37:5];
wire hit1 = mem1[adr[pMSB:5]]==adr[37:5];
wire hit2 = mem2[adr[pMSB:5]]==adr[37:5];
wire hit3 = mem3[adr[pMSB:5]]==adr[37:5];
always @*
//if (wr2) lineno = wlineno;
if (hit0) lineno = {2'b00,adr[8:5]};
else if (hit1) lineno = {2'b01,adr[8:5]};
else if (hit2) lineno = {2'b10,adr[8:5]};
else lineno = {2'b11,adr[8:5]};
if (hit0) lineno = {2'b00,adr[pMSB:5]};
else if (hit1) lineno = {2'b01,adr[pMSB:5]};
else if (hit2) lineno = {2'b10,adr[pMSB:5]};
else lineno = {2'b11,adr[pMSB:5]};
assign hit = hit0|hit1|hit2|hit3;
endmodule
 
303,8 → 307,11
// -----------------------------------------------------------------------------
 
module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, hit, invall, invline);
parameter pSize = 2;
parameter CAMTAGS = 1'b0; // 32 way
parameter FOURWAY = 1'b1;
localparam pLines = pSize==4 ? 128 : 64;
localparam pLNMSB = pSize==4 ? 6 : 5;
input rst;
input clk;
input nxt;
322,8 → 329,8
wire [287:0] ic;
reg [287:0] i1, i2;
wire [8:0] lv; // line valid
wire [5:0] lineno;
wire [5:0] wlineno;
wire [pLNMSB:0] lineno;
wire [pLNMSB:0] wlineno;
wire taghit;
reg wr1,wr2;
reg [8:0] en1, en2;
351,7 → 358,7
generate begin : tags
if (FOURWAY) begin
 
FT64_L1_icache_mem u1
FT64_L1_icache_mem #(.pLines(pLines)) u1
(
.rst(rst),
.clk(clk),
365,7 → 372,7
.invline(invline1)
);
 
FT64_L1_icache_cmptag4way u3
FT64_L1_icache_cmptag4way #(.pLines(pLines)) u3
(
.rst(rst),
.clk(clk),
/FT64_config.vh
27,21 → 27,42
`define SUPPORT_VECTOR 1'b1
//`define SUPPORT_DCI 1'b1 // dynamically compressed instructions
//`define DEBUG_LOGIC 1'b1
`define L1_ICACHE_SIZE 4 // 2 or 4 for 2 or 4 kB
 
// One way to tweak the size of the core a little bit is to limit the number
// of address bits processed. The test system for instance has only 512MB of
// memory, so the address size is limited to 32 bits.
`define AMSB 31
`define ABITS `AMSB:0
`define QBITS 3:0
 
 
`define QBITS 3:0 // bitfield representing a queue entry index
`define QENTRIES 10 // changing this still requires changing code in FT64.
`define XBITS 7:0
 
//`define SUPPORT_DBG 1'b1
 
// Issue logic is not really required for every possible distance from
// the head of the queue. Later queue entries tend to depend on prior
// ones and hence may not be ready to be issued. Also note that
// instruction decode takes a cycle making the last entry or two in the
// queue not ready to be issued. Commenting out this line will limit
// much of the issue logic to the first six queue slots relative to the
// head of the queue.
`define FULL_ISSUE_LOGIC 1'b1
 
// The WAYS config define affects things like the number of ports on the
// register file, the number of ports on the instruction cache, and how
// many entries are contained in the fetch buffers. It also indirectly
// affects how many instructions are queued.
`define WAYS 2 // number of ways parallel (1-3 3 not working yet)
`define NUM_IDU 2 // number of instruction decode units (1-3)
`define NUM_ALU 2 // number of ALU's (1-2)
`define NUM_MEM 2 // number of memory queues (1-3)
`define NUM_FPU 2 // number of floating-point units (0-2)
// Note that even with just a single commit bus, multiple instructions may
// commit if they do not target any registers. Up to three instruction may
// commit even with just a single bus.
`define NUM_CMT 2 // number of commit busses (1-2)
// Comment out the following to remove FCU enhancements (branch predictor, BTB, RSB)
`define FCU_ENH 1
/FT64_iexpander.v
58,7 → 58,7
default:
begin
expand[47:32] = 16'h0000;
expand[31:18] = {{6{cinstr[11]}},cinstr[11:8],cinstr[5]};
expand[31:18] = {{9{cinstr[11]}},cinstr[11:8],cinstr[5]};
expand[17:13] = cinstr[4:0];
expand[12:8] = cinstr[4:0];
expand[7:6] = 2'b10;

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