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  • This comparison shows the changes necessary to convert path 
    /thor/trunk/FT64v5/rtl/common
    from Rev 58 to Rev 59
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  •

Rev 58 → Rev 59

/FT64_cache.v
26,9 → 26,6
//
`define TRUE 1'b1
`define FALSE 1'b0
`define BRK 6'd0
`define FLT_EXF 9'd497
`define FLT_IBE 9'd509
 
// -----------------------------------------------------------------------------
// Small, 64 line cache memory (2kiB) made from distributed RAM. Access is
37,7 → 34,7
 
module FT64_L1_icache_mem(rst, clk, wr, en, lineno, i, o, ov, invall, invline);
parameter pLines = 64;
parameter pLineWidth = 288;
parameter pLineWidth = 290;
localparam pLNMSB = pLines==128 ? 6 : 5;
input rst;
input clk;
50,6 → 47,8
input invall;
input invline;
 
integer n;
 
(* ram_style="distributed" *)
reg [pLineWidth-1:0] mem [0:pLines-1];
reg [pLines-1:0] valid0;
62,6 → 61,11
reg [pLines-1:0] valid7;
reg [pLines-1:0] valid8;
 
initial begin
for (n = 0; n < pLines; n = n + 1)
mem[n][289:288] <= 2'b00;
end
 
always @(posedge clk)
if (wr & en[0]) mem[lineno][31:0] <= i[31:0];
always @(posedge clk)
79,7 → 83,7
always @(posedge clk)
if (wr & en[7]) mem[lineno][255:224] <= i[255:224];
always @(posedge clk)
if (wr & en[8]) mem[lineno][287:256] <= i[287:256];
if (wr & en[8]) mem[lineno][289:256] <= i[289:256];
always @(posedge clk)
if (rst) begin
valid0 <= 64'd0;
306,7 → 310,7
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
 
module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, hit, invall, invline);
module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, fault, hit, invall, invline);
parameter pSize = 2;
parameter CAMTAGS = 1'b0; // 32 way
parameter FOURWAY = 1'b1;
320,14 → 324,15
input [8:0] en;
input [37:0] adr;
input [37:0] wadr;
input [287:0] i;
input [289:0] i;
output reg [47:0] o;
output reg [1:0] fault;
output hit;
input invall;
input invline;
 
wire [287:0] ic;
reg [287:0] i1, i2;
wire [289:0] ic;
reg [289:0] i1, i2;
wire [8:0] lv; // line valid
wire [pLNMSB:0] lineno;
wire [pLNMSB:0] wlineno;
343,7 → 348,7
always @(posedge clk)
wr2 <= wr1;
always @(posedge clk)
i1 <= i[287:0];
i1 <= i[289:0];
always @(posedge clk)
i2 <= i1;
always @(posedge clk)
421,6 → 426,8
//always @(radr or ic0 or ic1)
always @(adr or ic)
o <= ic >> {adr[4:1],4'h0};
always @*
fault <= ic[289:288];
 
assign wr_ack = wr2;
 
429,13 → 436,14
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
 
module FT64_L2_icache_mem(clk, wr, lineno, sel, i, o, ov, invall, invline);
module FT64_L2_icache_mem(clk, wr, lineno, sel, i, fault, o, ov, invall, invline);
input clk;
input wr;
input [8:0] lineno;
input [2:0] sel;
input [63:0] i;
output [287:0] o;
input [1:0] fault;
output [289:0] o;
output reg ov;
input invall;
input invline;
446,6 → 454,7
reg [63:0] mem2 [0:511];
reg [63:0] mem3 [0:511];
reg [31:0] mem4 [0:511];
reg [1:0] memf [0:511];
reg [511:0] valid;
reg [8:0] rrcl;
 
453,8 → 462,10
wire [8:0] cache_line;
integer n;
initial begin
for (n = 0; n < 512; n = n + 1)
for (n = 0; n < 512; n = n + 1) begin
valid[n] <= 0;
memf[n] <= 2'b00;
end
end
 
always @(posedge clk)
466,11 → 477,11
begin
if (wr) begin
case(sel[2:0])
3'd0: mem0[lineno] <= i;
3'd1: mem1[lineno] <= i;
3'd2: mem2[lineno] <= i;
3'd3: mem3[lineno] <= i;
3'd4: mem4[lineno] <= i[31:0];
3'd0: begin mem0[lineno] <= i; memf[lineno] <= fault; end
3'd1: begin mem1[lineno] <= i; memf[lineno] <= memf[lineno] | fault; end
3'd2: begin mem2[lineno] <= i; memf[lineno] <= memf[lineno] | fault; end
3'd3: begin mem3[lineno] <= i; memf[lineno] <= memf[lineno] | fault; end
3'd4: begin mem4[lineno] <= i[31:0]; memf[lineno] <= memf[lineno] | fault; end
endcase
end
end
481,7 → 492,7
always @(posedge clk)
ov <= valid[lineno];
 
assign o = {mem4[rrcl],mem3[rrcl],mem2[rrcl],mem1[rrcl],mem0[rrcl]};
assign o = {memf[rrcl],mem4[rrcl],mem3[rrcl],mem2[rrcl],mem1[rrcl],mem0[rrcl]};
 
endmodule
 
508,7 → 519,7
input exv_i;
input [63:0] i;
input err_i;
output [287:0] o;
output [289:0] o;
output hit;
input invall;
input invline;
519,6 → 530,7
reg wr1,wr2;
reg [2:0] sel1,sel2;
reg [63:0] i1,i2;
reg [1:0] f1, f2;
reg [37:0] last_adr;
 
// Must update the cache memory on the cycle after a write to the tag memmory.
533,7 → 545,11
sel2 <= sel1;
always @(posedge clk)
last_adr <= adr;
 
always @(posedge clk)
f1 <= {err_i,exv_i};
always @(posedge clk)
f2 <= f1;
reg [3:0] rdackx;
always @(posedge clk)
if (rst)
547,10 → 563,8
 
assign rd_ack = rdackx[3] & ~(last_adr!=adr || wr || wr1 || wr2);
 
// An exception is forced to be stored in the event of an error loading the
// the instruction line.
always @(posedge clk)
i1 <= err_i ? {2{15'd0,1'b0,`FLT_IBE,2'b00,`BRK}} : exv_i ? {2{15'd0,1'b0,`FLT_EXF,2'b00,`BRK}} : i;
i1 <= i;
always @(posedge clk)
i2 <= i1;
 
564,6 → 578,7
.lineno(lineno),
.sel(sel2),
.i(i2),
.fault(f2),
.o(o),
.ov(lv),
.invall(invall),
/FT64_config.vh
22,12 → 22,15
//
// ============================================================================
//
// The following line is to enable simulation versions of some modules.
// Comment out for synthesis.
`define SIM 1'b1
 
//`define SUPPORT_SMT 1'b1
`define SUPPORT_VECTOR 1'b1
//`define SUPPORT_VECTOR 1'b1
//`define SUPPORT_DCI 1'b1 // dynamically compressed instructions
//`define DEBUG_LOGIC 1'b1
`define L1_ICACHE_SIZE 4 // 2 or 4 for 2 or 4 kB
`define L1_ICACHE_SIZE 2 // 2 or 4 for 2 or 4 kB
 
// One way to tweak the size of the core a little bit is to limit the number
// of address bits processed. The test system for instance has only 512MB of
55,15 → 58,15
// register file, the number of ports on the instruction cache, and how
// many entries are contained in the fetch buffers. It also indirectly
// affects how many instructions are queued.
`define WAYS 2 // number of ways parallel (1-3 3 not working yet)
`define NUM_IDU 2 // number of instruction decode units (1-3)
`define NUM_ALU 2 // number of ALU's (1-2)
`define NUM_MEM 2 // number of memory queues (1-3)
`define NUM_FPU 2 // number of floating-point units (0-2)
`define WAYS 1 // number of ways parallel (1-3 3 not working yet)
`define NUM_IDU 1 // number of instruction decode units (1-3)
`define NUM_ALU 1 // number of ALU's (1-2)
`define NUM_MEM 1 // number of memory queues (1-3)
`define NUM_FPU 1 // number of floating-point units (0-2)
// Note that even with just a single commit bus, multiple instructions may
// commit if they do not target any registers. Up to three instruction may
// commit even with just a single bus.
`define NUM_CMT 2 // number of commit busses (1-2)
`define NUM_CMT 1 // number of commit busses (1-2)
// Comment out the following to remove FCU enhancements (branch predictor, BTB, RSB)
`define FCU_ENH 1
// Comment out the following to remove bypassing logic on the functional units
/FT64_defines.vh
303,6 → 303,8
`define EXR 8'h7F
 
`define NOP_INSN {42'd0,`NOP}
`define INSN_FLT_EXF 16'h1180
`define INSN_FLT_IBE 16'h10A0
 
`define CSR_CR0 11'h000
`define CSR_HARTID 11'h001
/FT64_iexpander.v
72,8 → 72,8
expand[7:6] = 2'b10;
expand[15:8] = {3'd1,cinstr[11:8],cinstr[5]};
expand[16] = 1'b0;
expand[19:17] = 3'd0;
expand[23:20] = 4'd1;
expand[20:17] = 4'd0;
expand[23:21] = 3'd1;
expand[31:24] = 8'd0;
end
// LDI

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